Questions tagged [pmos]

A p-channel metal-oxide semiconductor (pMOS) transistor which has has p-type carriers used in the channel. The channel is established by a negative voltage on the gate which inverts the substrate (NWell) under the gate which turns the device on. The term may also be used to describe logic circuits built around pMOS transistors.

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Buck using discretes - Driving p-MOSFET using n-MOSFET

We are designing a buck using discretes. I have a problem with OFF time of Control MOSFET(U1) and driver(T1). In OFF time, Gate of U1 is rising very slowly to 12V which makes U1 always ON. Which in ...
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Is there a popular small signal PFET equivalent to NFETs 2N7000 or BS170?

Some days ago I was considering using a small signal P-Channel MOSFET in a design of mine, but could not find a suitable part. The specs I was looking for were something like the following: \$I_D = -...
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Using p-channel mosfet on high side of h-bridge, do I really need a driver chip?

I know there are fancy h-bridge ic's to drive high side of h-bridge but I guess that is when I have to drive n channel mosfet. I am planning on using p channel mosfets on high side and n channel ttl ...
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525 views

term “fat” when referring to NMOS and PMOS

I'm uncertain of the term "fat" when referring to NMOS and PMOS. Tried google and nothing. Could I get a little clarification?
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A good reference for modeling pmos transistors in LTspice?

I've been trying to learn how to use LTspice, and I'm attempting to create a model for a pFET I've been using/will use on a real board. However, since my specific transistor isn't already in LTspice'...
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353 views

Working principle of floating gate tunneling oxide

Floating gate tunneling oxide (FLOTOX) is used in electrically alterable rom. Tunneling of charge takes place through tunneling oxide into the floating gate. What is the working principle of this? How ...
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nMOS passing 1's poorly and pMOS passing 0's poorly

I came across the statement in a digital design book that "nMOS transistors pass 0's well but pass 1's poorly" and "pMOS pass 1's well but 0's poorly". What exactly do these statements mean and why ...
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71 views

Mask Programmable Array Concept

I am having trouble understanding a lecture slide for Mask Programmable Arrays. The cell on the right is supposed to represent a 4-input NOR gate. But I just cant wrap my head around which pads ...
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Digital Logic and Assertion levels

I'm struggling to get my head around assertion levels and how it relates to logic levels / functions. For example. Let's say we have 2 input signals, A and B So A assertive high and A assertive low....
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After all the transients have settled down what would be the output voltage

Vo(0)=5 , what is Vo(infinity) Can you please explain to me how i can get the answer.
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Micro SD card power circuit failure

Description I am designing a system in which there's a circuit that controls the power applied to a micro SD card (enable/disable). The circuit is the following: The power control circuit is done ...
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Reverse polarity protection - PMOS vs Schottkey diode

I have a circuit running from 2 AA cells in series, meaning I get 3.0V when fresh (or 2.4V if NIMH cells) and it goes down to 2.0V, that's when my circuit cannot function anymore (no DC/DC onboard). ...
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540 views

Operational Amplifier Single Supply Negative Output

I've built a comparator circuit that I want to use to drive a PMOS transistor. I only need negative output, but I'm on a single 12V/24V battery supply. I know I can create a virtual ground and split ...
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673 views

Adjustable PMOS current source

I'm trying to design a current source that can be adjusted from 0mA to 25mA (for an input voltage of 0V to 3V) using a dual P-Channel FET (NTZD3152P). I've based my design on some PMOS current ...
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348 views

Motor activation using MOSFET

I need to switch a motor on and off by cutting it's battery connection and even though I could use a relay, I would rather to use a MOSFET, so things will be smaller and quieter. The problem is, I am ...
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130 views

Controlling a 300V node with 5V from a micro-controller

The goal is to drive a 47k load that requires at least 5mA of current. The design is as shown, with FET values matching their part number: An LTSpice simulation (with generic pmos and nmos devices) ...
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Explain the use of NPN and pMOSFET in this 8x8x8 LED cube

I've got part of a circuit diagram for an 8x8x8 RGB LED cube from http://www.kevindarrah.com. See the entire schematic. I'm having trouble working out how it does what it does. I know that a high ...
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206 views

Voltage regulator device selection

I intend to design a CMOS voltage regulator that takes 2.5V supply and outputs 1.2V. I am starting off with an opamp+pass transistor design. Will there be a specific advantage to using an NMOS ...
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Designing stable PMOS voltage regulator

As a follow-on to the question "Using forward voltage drop of diodes with linear regulator" I am looking into designing PMOS voltage regulators. General Topology A common problem with the intuitive ...
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434 views

Adding switch debounce to discharge circuit

We use the attached circuit for some diagnostic timing prior to doing experiments. Basically when the momentary switch is closed, from a location away from the generator box, the left side of C2 is ...
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what happens when transistors are interchanged in CMOS?

A basic cmos inverter will have a P-transistor upside and N-transistor down side. what happens if we reverse the p and n transistors?
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229 views

PMOS cutoff not working well

I have designed a PMOS (FDN306) based power on off switch. When I turn off the switch by connecting gate and source (via Schmitt Trigger), I see a output voltage of 50mV. This is with 3.9V Source ...
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Solving PMOS Analysis Problem

I am trying to analyze a PMOS circuit, but cannot seem to set it up correctly. Here is the circuit: $$K_P=\frac{250 \mu A}{V^2}$$ where $$V_T = -1V$$ I have simulated the circuit with Pspice, but ...
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P-Channel MOSFET high side switch

I am trying to reduce the power dissipation of a P-Channel MOSFET high side switch. So my question is: is there any way in which this circuit can be modified so that the P-Channel MOSFET will ...
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Where are the depletion PMOS transistors?

In school, I was taught about PMOS and NMOS transistors, and about enhancement- and depletion-mode transistors. Here's the short version of what I understand: Enhancement means that the channel is ...
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Why old PMOS/NMOS logic needed multiple voltages?

Why does old PMOS/NMOS logic needed multiple voltages like +5, -5, and +12 volts? For example, old Intel 8080 processors, old DRAMs, e.t.c... I'm interested in the causes on the physical/layout ...