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Questions tagged [power-integrity]

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Sony IMX421 Eval board with IMX422 Sensor - produces odd repeating patterns instead of true images

I am working on an application that involves use of a Sony IMX422 CMOS image sensor - namely writing VHDL code to act as a receiver interface to the sensor over an SLVS bus. the setup involves a ...
CNfan's user avatar
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How do you de-embed a shorted 2-port fixture?

I've been working through reproducing Steve Sandler's 2-port shunt-through measurements (2019 SIJ article, Picotest slide-deck). My target is to measure capacitors with ESR down to 1 mΩ with an ...
Daniel's user avatar
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2 votes
0 answers
164 views

Power integrity design review of LED driver and audio amplifier PCB

I am seeking advice on improving the power integrity of a PCB featuring a HT16K33 driving 6 segment LEDs and a YX8002 (equivalent to LM4871) audio amplifier. Decoupling capacitors C7 and C16 are ...
sephalon's user avatar
5 votes
3 answers
2k views

Is it possible to know through simulation whether we have the right number of decoupling capacitors?

More decoupling capacitors than a certain amount does not improve the power integrity much. I am not sure if this is a case of diminishing returns or a case of reaching a wall. How exactly can we ...
quantum231's user avatar
2 votes
1 answer
158 views

Connecting '-' terminal of the power supply to the earth GND

I've already asked a similar question in the past, but I want to make sure I understood things correctly. Attached is the current lab setup for my chip testing. The green square represents the main ...
Emm386's user avatar
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3 votes
1 answer
95 views

Track vs Via impact on power integrity

This question is from perspective of power integrity and not signal integrity. Power can be delivered from VRM to an IC using copper tracks and vias. Both of these have inductance and we want to ...
quantum231's user avatar
0 votes
1 answer
357 views

FPGA decoupling capacitors

FPGAs have among the largest packages and the most voltage rails. This is especially true of the high end devices e.g Stratix, Virtex Ultrascale+ e.t.c. This means a whole lot of decoupling capacitors....
quantum231's user avatar
0 votes
1 answer
465 views

Shall I connect '-' terminal of power supply to earth GND (green terminal)?

Attached is the current lab setup for my chip testing. The green square represents the main PCB board, and little blue square represents the chip. The chip needs separate VDD voltage for its analog ...
Emm386's user avatar
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2 votes
2 answers
76 views

Using main board power supply rails in add-on boards

Many boards come with board-board connectors that can be used to connect another PCB to add new functionality. There are many examples of this. Some that come to mind are Arduino shield, Click boards™,...
quantum231's user avatar
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1 answer
171 views

Is there any benefit of the power plane capacitance to PDN?

PWR and GND plane make a capacitor with the dielectic in between them. The closer the two planes are physically, the higher the electrical coupling and thus the capacitance between them. Power ...
quantum231's user avatar
3 votes
1 answer
135 views

Bulk capacitance near a processor affecting converter transient response

Here is my question: why do manufacturers of processors and FPGAs prescribe adding hundreds or thousands of microfarads of bulk capacitance next to their part? The IGLOO2, for example, recommends a ...
moriarti's user avatar
0 votes
1 answer
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How to calculate target impedance for the power trace if it is connected to multiple loads?

In this image, the source 3.3V, which is going to three loads(U1,U2,U3), that consumes current of 2A,0.5A and 1A respectively, As the total current is 3.5A. Lets consider allowable ripple, U1-2% U2-3% ...
Selva97's user avatar
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1 vote
0 answers
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S parameter model of the capacitor

For same capacitor, there is no s-parameter model, so can we use the model from other manufacturer of the same spec. Eg: Caps with model - C0603C104K5RACTU - KEMET - Cap, Cer-X7R, 0.1uF, 50V, 10%, ...
Selva97's user avatar
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10 votes
6 answers
3k views

How does current flow in multiple vias?

How does current travel in multiple vias from one layer to other? For example, we connect four vias, each of which has a limit of 1.3A each from power plane to sink device. If the sink draws 4A of ...
Selva97's user avatar
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0 answers
237 views

I2C bus pollutes power rail

Working on a new revision of a design with a new I2C LED driver connected to SAM S70 Cortex-M7, I noticed some high speed ripple on 5V rail when using a 1Ghz scope. The PCB has 2 I2C buses and both ...
Max Morgunov's user avatar
1 vote
0 answers
60 views

EMI EMC analysis of converters

Probably not the best place to ask this question, I'll remove it if not received well. I am trying to perform EMI/EMC analysis of my resonant buck converter PCB. I tried to use ANSYS SIwave for this, ...
SM32's user avatar
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8 votes
2 answers
3k views

Is one big via better than multiple small vias when changing power traces and ground between layers?

I'm confused about the via placement in power traces either to change layers as part of routing the main supply or to get to component pins from a layer different to where the power trace is located, ...
m4l490n's user avatar
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1 answer
179 views

Reusing heatsink vias for ground plane connection

This a more elaborate phrasing of my previous question on the subject, which did not get much love. I would appreciate a clear and thorough answer since it is my last question (after a long journey) ...
Manos's user avatar
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0 answers
343 views

Power line between data lines

I am finalizing my design which connects a USB Controller (FT601) with the FPGA (MachXO2). There is last thing I am not particularly happy about and I would like your feedback on that. In the ...
Manos's user avatar
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0 answers
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Measured my PCB with Handheld LCR Meter - can you tell me anything?

This is a 5x4cm 8-layer PCB. It has 2 sets of dedicated VCC/GND planes plus ground plane polygons on top and bottom. It is not high speed. The top digital speed is 1Mhz SPI. It has 3 micros running on ...
Bill's user avatar
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2 votes
1 answer
5k views

What is difference between IBIS model and IBIS-AMI model and what are specific application of these two models?

I am working on PCIe 3.0 compliance testing from signal integrity and power integrity point of view. I would like to understand the difference between IBIS and IBIS-AMI model and which model is good ...
Anil Pandey's user avatar
0 votes
1 answer
128 views

Prerequisites for Power Integrity Analysis

I try to learn about the topic of Power Integrity Analysis of an PCB, i.e. analysing the Power Distribution network (PDN) of a PCB to locate the regions of biggest noise or DC voltage droop. ...
Junius's user avatar
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1 vote
1 answer
840 views

estimate (measure) parasitic inductance of a lead frame of a chip package

UPDATE: How to measure (/make a good approximation of) parasitic inductance of a lead frame of a chip package? This parameter is very important at high frequencies (1GHz and more) because it affects ...
Sergei Gorbikov's user avatar