Questions tagged [power-integrity]

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6 answers
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How does current flow in multiple vias?

How does current travel in multiple vias from one layer to other? For example, we connect four vias, each of which has a limit of 1.3A each from power plane to sink device. If the sink draws 4A of ...
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  • 395
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0 answers
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I2C bus pollutes power rail

Working on a new revision of a design with a new I2C LED driver connected to SAM S70 Cortex-M7, I noticed some high speed ripple on 5V rail when using a 1Ghz scope. The PCB has 2 I2C buses and both ...
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1 vote
0 answers
36 views

EMI EMC analysis of converters

Probably not the best place to ask this question, I'll remove it if not received well. I am trying to perform EMI/EMC analysis of my resonant buck converter PCB. I tried to use ANSYS SIwave for this, ...
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8 votes
2 answers
2k views

Is one big via better than multiple small vias when changing power traces and ground between layers?

I'm confused about the via placement in power traces either to change layers as part of routing the main supply or to get to component pins from a layer different to where the power trace is located, ...
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  • 343
0 votes
1 answer
117 views

Reusing heatsink vias for ground plane connection

This a more elaborate phrasing of my previous question on the subject, which did not get much love. I would appreciate a clear and thorough answer since it is my last question (after a long journey) ...
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  • 335
0 votes
0 answers
176 views

Power line between data lines

I am finalizing my design which connects a USB Controller (FT601) with the FPGA (MachXO2). There is last thing I am not particularly happy about and I would like your feedback on that. In the ...
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  • 335
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0 answers
61 views

Measured my PCB with Handheld LCR Meter - can you tell me anything?

This is a 5x4cm 8-layer PCB. It has 2 sets of dedicated VCC/GND planes plus ground plane polygons on top and bottom. It is not high speed. The top digital speed is 1Mhz SPI. It has 3 micros running on ...
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1 vote
1 answer
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What is difference between IBIS model and IBIS-AMI model and what are specific application of these two models?

I am working on PCIe 3.0 compliance testing from signal integrity and power integrity point of view. I would like to understand the difference between IBIS and IBIS-AMI model and which model is good ...
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0 votes
1 answer
94 views

Prerequisites for Power Integrity Analysis

I try to learn about the topic of Power Integrity Analysis of an PCB, i.e. analysing the Power Distribution network (PDN) of a PCB to locate the regions of biggest noise or DC voltage droop. ...
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1 vote
1 answer
482 views

estimate (measure) parasitic inductance of a lead frame of a chip package

UPDATE: How to measure (/make a good approximation of) parasitic inductance of a lead frame of a chip package? This parameter is very important at high frequencies (1GHz and more) because it affects ...
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