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Questions tagged [power-integrity]

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2answers
102 views

Is one big via better than multiple small vias when changing power traces and ground between layers?

I'm confused about the via placement in power traces either to change layers as part of routing the main supply or to get to component pins from a layer different to where the power trace is located, ...
0
votes
1answer
64 views

Reusing heatsink vias for ground plane connection

This a more elaborate phrasing of my previous question on the subject, which did not get much love. I would appreciate a clear and thorough answer since it is my last question (after a long journey) ...
0
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0answers
68 views

Power line between data lines

I am finalizing my design which connects a USB Controller (FT601) with the FPGA (MachXO2). There is last thing I am not particularly happy about and I would like your feedback on that. In the ...
0
votes
0answers
44 views

How to perform parasitic extraction in CST Studio?

I'd like as the title suggests to perform a parasitic extraction of an inverter PCB design using PEEC Method in CST Studio Suite but, unfortunately I can't seem to find documentation or resources ...
0
votes
0answers
54 views

Measured my PCB with Handheld LCR Meter - can you tell me anything?

This is a 5x4cm 8-layer PCB. It has 2 sets of dedicated VCC/GND planes plus ground plane polygons on top and bottom. It is not high speed. The top digital speed is 1Mhz SPI. It has 3 micros running on ...
1
vote
1answer
2k views

What is difference between IBIS model and IBIS-AMI model and what are specific application of these two models?

I am working on PCIe 3.0 compliance testing from signal integrity and power integrity point of view. I would like to understand the difference between IBIS and IBIS-AMI model and which model is good ...
0
votes
1answer
60 views

Prerequisites for Power Integrity Analysis

I try to learn about the topic of Power Integrity Analysis of an PCB, i.e. analysing the Power Distribution network (PDN) of a PCB to locate the regions of biggest noise or DC voltage droop. ...
0
votes
1answer
269 views

estimate (measure) parasitic inductance of a lead frame of a chip package

UPDATE: How to measure (/make a good approximation of) parasitic inductance of a lead frame of a chip package? This parameter is very important at high frequencies (1GHz and more) because it affects ...