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Questions tagged [power-sequencing]

Power sequencing involves circuits with multiple power rails to analog or digital electronics. Upon powering a circuit the rails must be sequenced with time to reach their designed voltages to ensure proper device operation. This is most common with digital devices such as FPGA's or Processors with multiple voltage rails and high current loads. If the rails are sequenced wrong the device might power on in an undetermined state and may not function properly

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Delay in discharging of the capacitor for sequencing purpose

Our aim is to sequence 2 different power supplies i.e. 5 V and -48 V. On sequence is first "5 V is generated" and then "-48 V is generated" with 120 ms delay. Off sequence is first ...
Sahasra Vaiishnavi's user avatar
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Device Power On Reset Requirements in SoC

I need to release the RESETn signal after all power supplies and clocks are stable, and de-assertion should be at least 100 ms (I'm using 47nF in CT to create delay of ~200ms). My idea is to connect ...
Knowledge's user avatar
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Reset supervisor with PGOOD of other supplies

I'm attempting to use Resetn of some IC device of TI that sense 4 voltages and after some threshold the IC output release the ResetN, but I'm afraid that it is not enough and I want to ensure the ...
Knowledge's user avatar
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Checking if the correct power is on

I'm making a device with an stm32 nucleo-f303k8 board that I power with 12V directly through one of its pins. However it can also draw power from USB and it can happen than USB will be connected first,...
Radar32's user avatar
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Level shifter: clamping (input+VccA) when input and VccA are powered from same signal

I'm currently testing a PCB I designed, and found out the following circuit don't work properly: the SYS_EN signal is connected to a 1.8V rail through a 10k pull-up resistor. TXU0101DRYRU5 is a level ...
Sandro's user avatar
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Power sequencing: enable signal hold below threshold if asserted after supply

Short version: When I power my PCB and the SYS_EN signals at the same time, all voltage rails turn on. If I first power the PCB, then pull high the SYS_EN signal, the 3.3V and 1.8V rails don't turn on....
Sandro's user avatar
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2 votes
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TFT LCD voltages and sequencing

In the recent project I am working on I want to connect a TFT LCD to ESP32-S3. I would be using the LCD hardware interface of ESP32, so I only need to take proper care of display power management. The ...
fafaldo's user avatar
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Power Good Connection for Regulator Sequencing

For powering Artix 7 FPGA I need power sequencing. In the Artix-7 data sheet it states that the recommended power-on sequence is VCCINT (1.0 V), VCCBRAM (1.0 V), VCCAUX (1.8 V), and VCCO (3.3 V). ...
Cenk's user avatar
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Sequential LED turn signal

I am trying to build a 4 LED sequential turn signal using the ne555 timer module and some comparators. I am having trouble with my next steps when trying to figure out what is wrong with my design. ...
Myles's user avatar
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How to power sequence two supplies for an LNA in the correct order when turning on and off?

I am using this LNA in my design and I have an issue with how the devices is being powered. The turn off/turn On procedure is as following: Apply drain voltage first (5 V) THEN apply gate voltage (3 V)...
Breakwin's user avatar
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Interview FPGA question about what I would power first

I have been asked this question in an interview, and I wondered what the correct answer was and why. What should you power on first in an FPGA? Is it the Core Logic, I/O blocks, or the memory?
Zarif Rahman's user avatar
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subcircuits powering (predetermined time delay, ~8 seconds)

In order to control inrush current, and also to make sure some subcircuits and modules are OK on startup, I need a predetermined time delay between delivering power to these subcircuits. (Automatic ...
Elementronics's user avatar
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What is the purpose of the resistor between the p_in+ and p_out of the Op-Amp in this circuit?

I found a very interesting sequence biasing circuit. https://www.qorvo.com/products/d/da007774 I understand how it works by now. But I still do not understand why there is a 1 Meg resistor (R7) ...
NightElf's user avatar
1 vote
3 answers
205 views

Power sequencing two +5V rails without a voltage drop

I'm new to power sequencing and wanting input on the best way to solve this problem. I have two separate +5V rails on my PCB coming from a rectified wall source and USB. Due to back powering issues, I ...
Nathan B.'s user avatar
1 vote
1 answer
184 views

Schematic review: prioritized power ORing

I am in the process of designing a circuit which will allow me to safely OR two power supplies. Constraints: 5V up to 5A from Vin_hi_prio up to 2A from ...
jaskij's user avatar
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Problem in simulation results in PSPICE using LM3880 sequencer

When simulating this simple sequencer circuit in PSPICE, I obtained these results which are not the wanted ones: I was supposed to have sequences but here I don't know what it is. The right sequence ...
Adlen Medjek's user avatar
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Why there are 2 definitions for high level logic input in the following datasheet?

I was referring a power sequencer datasheet at https://www.dialog-semiconductor.com/sites/default/files/slg7nt4618_ds_r024_03102016.pdf Iam confused with 2 definitions for the high level (circled ...
Dynamic_equilibrium's user avatar
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1 answer
117 views

What is a programmable power-up sequencer?

What is a programmable power-up sequencer ? How to use it in a PMIC to power AM335x TI microprocessor ?
Moonshine's user avatar
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1 answer
350 views

Startup sequence of Microcontroller [closed]

Which would be the startup sequence of a Microcontroller. Clock - Power - Reset Power - Clock - Reset I think it would be the second one because clock is always running, right? The noises in the ...
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1 vote
2 answers
398 views

Low Dropout Regulator Enable Delay

I have a main buck DCDC 5V that feeds to five different LDOs(3.3V). To create power sequencing, I would like to use a resistor and a capacitor at the input of the enable pin of each LDOs and by ...
adnan's user avatar
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How to use the LM3880DBV circuit in a multi rail power supply?

I'm struggling a little bit here with the LM3880DBV circuit usage in a multi rail power supply circuit So, here is my power supply circuit block schematic: And this is how I sequenced my circuit: ...
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2 votes
1 answer
222 views

LTM8073 integrated DC-DC buck converter issues

I have a board with two LTM8073 "silent switcher µModule regulators" by Analog Devices/Linear Technology being used to provide two separate power supplies. This is a 10-layer dual-sided board that was ...
Edgar Brown's user avatar
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The relay controller circuit in a pre-amp stopped working properly

I have a pre-amp with a controller circuit which controls input signal micro-relays and a power supply relay. While the input signal micro-relays work normally, all of a sudden the 30 second delay for ...
Tom's user avatar
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1 vote
1 answer
255 views

Power-down sequencing with a "hard" power switch (stepper driver)

I'm designing a stepper motor controller and would like to have some advice on sequencing the shutdown process with a "hard" power switch. The Toshiba TB6560 driver that I'm using requires a specific ...
higrafey's user avatar
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1 vote
1 answer
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Voltage sequencing on power up

I'm pretty new to PCB design, so my question may be obvious for some of you. I am wiring the layout of an LCD screen on a PCB using KiCad. When I came to powering up, the datasheet of the AT070TN92 ...
Badam Mamane's user avatar
4 votes
1 answer
335 views

LDO in split supply behaving incorrectly when power supply sequence is "wrong"

I'm powering an op-amp (OPA657) in transimpedance configuration. I externally supply ±15V, with LDOs to drop to ±5V; here I omit the feedback loop for simplicity: When I turn on the negative rail (-...
user2022444's user avatar
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3 answers
1k views

The circuit-level "why" of the loudspeaker / amplifier “POPP” sound

in the other question about the "popp" sound I asked if the "popp" is harmful to a loudspeaker. Since I am also interested in the "why" on the circuit level, here is my next question. I put this ...
Justin Time's user avatar
4 votes
2 answers
245 views

Why do ICs need a specific power down sequence?

When powering down a board, for ICs that have multiple supply voltage rails, why do they need a specific power down sequence? Typically in complex motherboards, there is a CPLD doing the job of this ...
Neil Dey's user avatar
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Exceeded absolute maximum voltage of FPGA

I am using cyclone V FPGA. During my testing process, somehow I gave 12V to the IO bank instead of 3.3V. The board is shorted and I found FPGA has gone bad. Now to prevent such accidents in the ...
pavan's user avatar
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Power sequencing with LDO without enable pin

What is the right way to provide a power sequence using LDO (or any other power source) without the enable pin? I'm using DAC7718 from Texas Instruments and it require a quit complex power sequencing:...
Mark's user avatar
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1 answer
158 views

Power up sequence for AD5724

The datasheet says: POWER-UP SEQUENCE Because the DAC output voltage is controlled by the voltage monitor and control block (see Figure 42), it is important to power the DVCC pin before applying any ...
Mark's user avatar
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3 votes
1 answer
1k views

Using Power Good pins for sequencing

I'm trying to figure out a way to use the Power Good outputs of several stages of voltage regulators to sequence and monitor a board powering several FPGAs. I've done this easily before with a ...
Dejvid_no1's user avatar
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3 votes
2 answers
191 views

Power sequence solution with limited board real estate

I am designing a power supply using the LTM4639 part. VIN (3.3. V) needs to be sequenced before the bias input (5 V) in order for soft start to work. However there is no fixed timing relationship ...
JackOTrade's user avatar
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1 answer
146 views

Are RC circuits suitable for use as power sequencers?

Are RC circuits suitable for use as power sequencers with EN pins on LDOs? I know that there may be a problem with reverse sequence on power off, but some devices allow that on power down all power ...
Singee's user avatar
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1 answer
211 views

Power sequencing of simple peripheral ICs for ADC/GPIO with an MCU

Imagine I have the following scenario: Having a +5V rail powering an MCU and several other peripheral ICs, let's assume in this case a voltage reference (for example 4096mV). The output of this ...
fscheidl's user avatar
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3 votes
1 answer
420 views

What's the reason for power-down sequencing in a SOC? Can you damage it in some way?

Power-on sequencing I understand. But why do power-off sequencing? I could understand if you had to do something before power died, or maybe you just wanted to shutdown I/O before core so that no ...
confused's user avatar
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1 vote
2 answers
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Would a reset IC be enough for this many power supplies?

Could you please let me know how many reset ICs I'd need for my board? I'm designing a camera using the IMX225LQR Image Sensor. This sensor requires 3 different input voltages: 1.2v, 1.8v and 3.3v ...
SD11's user avatar
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1 answer
516 views

Power supply sequencing for low power camera module

Could you please suggest a simple method how to make power on/off sequence of three different input voltages? I'm making a board camera using this image sensor. The sensor requires three different ...
SD11's user avatar
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7 votes
1 answer
419 views

Can I ignore the Power up Sequence

I am designing a board where the datasheet suggests a power up sequence. Basically, the VDD_PLL should be turned on first, after 100us, the VAA should be turned on, followed by the internal supply and ...
red car's user avatar
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1 vote
1 answer
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Power sequencing requirement for LCD

I am using LCD with below power interface. But as per below note in LCD datasheet, VCC and VGL need to apply first and then VGH. My query is why such power sequencing is needed ? If I use below ...
Electroholic's user avatar
3 votes
3 answers
676 views

Power supply for FPGA

I have a Spartan 6 FPGA (XC6SLX9-2TQG144) and I'm designing a power supply for it. Let's assume that I will utilize all of its logic (very possible) and I want to clock it as fast as possible (around ...
zupazt3's user avatar
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0 votes
2 answers
114 views

Question about particular powerup seq

I have a particular powerup sequence from a datasheet that require this: At power-up, VDDIO needs to reach 0.6 V before VDDIN reaches 1.0 V. VDDIO voltage needs to be equal to or below (VDDIN ...
Yaro's user avatar
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5 votes
1 answer
295 views

Power sequencing in FPGAs and MCUs

I have a question about power sequencing requested by FPGA/MCU datasheets. I always see in datasheets that a particular power supply input must reach a voltage level before another power supply input (...
Yaro's user avatar
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What is the name of a circuit that delays powering of another circuit?

I'm having trouble figuring out the name of this circuit. It needs to delay turning "on" a 12V circuit and a 120VAC circuit, after a 5V circuit has been turned on. Example: Turn on 1x power switch, ...
rcdriver23's user avatar
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2 answers
208 views

Power up sequence circuitry

I need to power up an IC and I have two or three power supplies. The datasheet says: Vdd1 and Vdd2 are turned on at the same time; make sure Vdd1 becomes stable before Vdd2. My power supplies have ...
Yaroooo's user avatar
3 votes
3 answers
2k views

Any good method for the power down sequence?

In my circuit, +12V would be supplied by an external power source. After two regulators, two more voltage sources (+5V and +3.3V) would be produced and supply power to the AD7682 ADC. Because of the ...
billyzhao's user avatar
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1 vote
3 answers
182 views

Would having no power supply but a large input signal damage the amplifier?

I am now learning about the power sequence of the circuit. And wonder that as every amplifier has its own limited input voltage (for example: ADA4004's input limit is V− < VIN < V+), would the ...
billyzhao's user avatar
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4 votes
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Power up sequence

I am designing hardware where a specific power up sequence is needed. The Vdd_33 should come 10 µs after vdd_18. I have LDOs for these supplies. One option is to control the power distribution with ...
Ktc's user avatar
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