Questions tagged [process]

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51 views

VHDL: How to only update register at rising edge of the clock?

I have a counter called lastelem_reg. At the rising edge of each clock, it should check whether another signal enqueue is HIGH. If it is, then lastelem_reg will be incremented by 1 in the next clock, ...
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1answer
31 views

How to find out which process triggered join_any in verilog

I have three tasks running in parallel and the fork joins when one of them gets completed. I would like to know which one was completed first and caused the fork to join. Is there a way to know it? <...
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2answers
103 views

What's the typical distribution of fabric speed grades in produced dies?

Let's say I produce 1000 FPGAs, what percentage of these 1000 FPGAs are considered super fast, fast, medium, and slow? Does it look like a normal distribution, exponential, linear, etc.? Does anyone ...
2
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4answers
122 views

How do I translate product requirements into components, schematics, and programming?

I graduated with a degree in electrical engineering, but a) I've been doing mostly project management since, b) I didn't get my ADHD diagnosed until after I graduated, and c) I feel like inappropriate ...
0
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1answer
41 views

Learning process automation starting from general engineering background [closed]

I'd like to study process automation by myself, could you suggest a good entry-level book to start with? I have engineering college math level and I remember a bit of Laplace transforms to model ...
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0answers
235 views

How to calculate the number of pages of a process, and the size of the page table(in bytes)?

I just need a second opinion on the result that I got for a question to see if it is right. I am dealing with a computer system using paging, where the address space space of every process has a size ...
1
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1answer
84 views

Xilinx Line <read_line> has not enough elements for target <input_b> for the file with more than one line

I have a file each line of which includes two 9 bits inputs. Here is an example of this file: input_vectors.txt: ...
2
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2answers
5k views

VHDL multiple signal drivers

I am trying to learn good vhdl design methodologies. I was trying to find some advises about multiple signal drivers. Unfortunatelly without success. My question is if it is good idea to have signal ...
0
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0answers
447 views

Power MOSFET versus regular MOSFET Silicon Layers

I am having some difficulties differentiating between a power MOSFET process and a regular MOSFET process. Here is a regular MOSFET silicon layer stackup: The n+ doped region for the source and ...
1
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2answers
846 views

Execution inside a process [VHDL]

I have, for example, this code snippet: ...
0
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1answer
135 views

decapsulating a MOSFET to create a bulk terminal

In my project, I would be using NMOS' and it would be very handy for me to have a bulk terminal. Since my choices of NMOS parts don't have bulk terminal, I was wondering if I could somehow decapsulate ...
1
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1answer
62 views

Why two independent if-loops are always put in different always/process blocks?

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2
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2answers
165 views

Can a flip flop possibly work at over 800MHz? [closed]

As I know, the setup time is at least required time for data to become stable at the input of a FF before the sensitive clock edge. Hold time is the required time for data to remain stable after the ...
1
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1answer
3k views

loop synthesis vhdl

Suppose we have an iterative algorithm like: r(j) := f(r(j-1)) r(0) := value And that vhdl i implemened a process for such algorithms (assuming a bit of ...
2
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1answer
81 views

How can I deposit metallic electrodes on a temperature-sensitive wafer?

How can I deposit metallic contacts on a wafer in a process that won't heat the wafer above 80C? The size of the electrodes should be around 1mm2. The wafer could be glass or silicon, coated with a ...
2
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1answer
200 views

What is the effect of this delayed statement in the following process?

Hi guys in the following process how the delayed assignment should be interpreted? ...
1
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1answer
773 views

Microcontroller and FPGA Manufacturing Process Technology and Size

I'm comparing the power consumption of several microcontrollers, FPGAs and an ASIC I've developed, which all perform the same task. For a fair comparison the current consumption must be scaled due to ...
5
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3answers
1k views

How do integrated circuit design companies create their datasheets?

Especially for something like a microprocessor. I assume the majority of information is "auto-generated" or we'd see a lot more typos and errors. A laughable scenario keeps popping into my head ...
16
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4answers
19k views

Why does a processor get hot?

I would like to understand how the computation process causes the processor to get hot. I understand that the heat is generated by the transistors. How does the transistors generate the heat exactly? ...
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1answer
209 views

Lead-lag process control

What is the locus of the following system, and for what value of \$\alpha\$ is the damping ratio 0.5?
9
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3answers
712 views

How to find out if a microprocessor is powerful enough

Everybody knows its easy to develop a proof of concept for an embedded device on a rasbperry pi or even a PC, although when it comes down to choosing a microprocessor for your product, it is difficult ...
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2answers
10k views

Signal assignment in/out process

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3answers
4k views

what do the nm or µm for a process technology refer to e.g 22nm process technology for device fabrication

There are many "process technologies" that exist to fabricate circuits on silicon. They are mainly differentiated based on size of some feature. Here is the list of them: ...
4
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1answer
4k views

VHDL: when is process sensitivity list triggered?

In VHDL simulation, there is a concept of "delta time," which is loosely interpreted as "group of events triggered by the previous delta time." After a change, once all cascading changes have settled, ...