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Why does a processor get hot?

I would like to understand how the computation process causes the processor to get hot. I understand that the heat is generated by the transistors. How does the transistors generate the heat exactly? ...
syntagma's user avatar
  • 397
9 votes
3 answers
884 views

How to find out if a microprocessor is powerful enough

Everybody knows its easy to develop a proof of concept for an embedded device on a rasbperry pi or even a PC, although when it comes down to choosing a microprocessor for your product, it is difficult ...
Funkyguy's user avatar
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5 votes
3 answers
887 views

DIN Rail Logic Gate

I'm not an expert in electronics and need a bit of guidance. At work, we want to implement an alarm that sound when a process is running (or starting) but the air for cooling is not on. The alarm does ...
Ernie Peters's user avatar
5 votes
3 answers
2k views

How do integrated circuit design companies create their datasheets?

Especially for something like a microprocessor. I assume the majority of information is "auto-generated" or we'd see a lot more typos and errors. A laughable scenario keeps popping into my head ...
Grit's user avatar
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4 votes
3 answers
5k views

what do the nm or µm for a process technology refer to e.g 22nm process technology for device fabrication

There are many "process technologies" that exist to fabricate circuits on silicon. They are mainly differentiated based on size of some feature. Here is the list of them: ...
quantum231's user avatar
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4 votes
1 answer
5k views

VHDL: when is process sensitivity list triggered?

In VHDL simulation, there is a concept of "delta time," which is loosely interpreted as "group of events triggered by the previous delta time." After a change, once all cascading changes have settled, ...
Jon Watte's user avatar
  • 5,750
3 votes
2 answers
602 views

Why is CVD not used in the manufacture of NMOS gate oxides?

I know that chemical vapor deposition (CVD) is a vacuum deposition method used to produce high-quality, high-performance solid materials. The process is often used in the manufacture of semiconductors ...
LUFER's user avatar
  • 469
3 votes
1 answer
818 views

VHDL process, nested if statement execution

I am relearning VHDL and have a question about the code below. This is from a tutorial I have been following. When a button is pressed, an LED gets turned on after the person releases their finger ...
Eric33's user avatar
  • 83
3 votes
2 answers
10k views

VHDL multiple signal drivers

I am trying to learn good vhdl design methodologies. I was trying to find some advises about multiple signal drivers. Unfortunatelly without success. My question is if it is good idea to have signal ...
e2p's user avatar
  • 187
3 votes
0 answers
319 views

What is the shortest possible *channel length* in a currently available commercial CMOS process?

I'm aware that terms like "5 nm", "7 nm" for the latest technology nodes no longer refer to any linear dimension of the transistors, although I have seen some interpretations in ...
Halleff's user avatar
  • 705
2 votes
2 answers
182 views

Can a flip flop possibly work at over 800MHz? [closed]

As I know, the setup time is at least required time for data to become stable at the input of a FF before the sensitive clock edge. Hold time is the required time for data to remain stable after the ...
bural's user avatar
  • 43
2 votes
4 answers
262 views

How do I translate product requirements into components, schematics, and programming?

I graduated with a degree in electrical engineering, but a) I've been doing mostly project management since, b) I didn't get my ADHD diagnosed until after I graduated, and c) I feel like inappropriate ...
John Doe's user avatar
  • 196
2 votes
2 answers
129 views

What's the typical distribution of fabric speed grades in produced dies?

Let's say I produce 1000 FPGAs, what percentage of these 1000 FPGAs are considered super fast, fast, medium, and slow? Does it look like a normal distribution, exponential, linear, etc.? Does anyone ...
Charles Clayton's user avatar
2 votes
1 answer
212 views

What is the effect of this delayed statement in the following process?

Hi guys in the following process how the delayed assignment should be interpreted? ...
user8469759's user avatar
2 votes
1 answer
93 views

How can I deposit metallic electrodes on a temperature-sensitive wafer?

How can I deposit metallic contacts on a wafer in a process that won't heat the wafer above 80C? The size of the electrodes should be around 1mm2. The wafer could be glass or silicon, coated with a ...
Sparkler's user avatar
  • 833
1 vote
1 answer
78 views

Why two independent if-loops are always put in different always/process blocks?

...
tollin jose's user avatar
  • 3,232
1 vote
3 answers
13k views

Signal assignment in/out process

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Anarkie's user avatar
  • 329
1 vote
1 answer
2k views

VHDL: How to only update register at rising edge of the clock?

I have a counter called lastelem_reg. At the rising edge of each clock, it should check whether another signal enqueue is HIGH. If it is, then lastelem_reg will be incremented by 1 in the next clock, ...
Leonhard Euler's user avatar
1 vote
1 answer
5k views

loop synthesis vhdl

Suppose we have an iterative algorithm like: r(j) := f(r(j-1)) r(0) := value And that vhdl i implemened a process for such algorithms (assuming a bit of ...
user8469759's user avatar
1 vote
2 answers
1k views

Execution inside a process [VHDL]

I have, for example, this code snippet: ...
ferdepe's user avatar
  • 575
1 vote
1 answer
1k views

Microcontroller and FPGA Manufacturing Process Technology and Size

I'm comparing the power consumption of several microcontrollers, FPGAs and an ASIC I've developed, which all perform the same task. For a fair comparison the current consumption must be scaled due to ...
Johann Glaser's user avatar
0 votes
1 answer
488 views

How to fix this VHDL error

I am getting an error in my VHDL code. It says "[Synth 8-27] else clause after check for clock not supported". Why is this? Below is the code: ...
David777's user avatar
  • 1,583
0 votes
1 answer
57 views

Learning process automation starting from general engineering background [closed]

I'd like to study process automation by myself, could you suggest a good entry-level book to start with? I have engineering college math level and I remember a bit of Laplace transforms to model ...
Vinlar's user avatar
  • 115
0 votes
1 answer
1k views

VHDL signals with initialized values

This is my code: And this is the testbench: I am a VHDL beginner, and now I am trying to understand how 'Process' works. I know that signals get the value only in the end of the process. At t=0, the ...
idan's user avatar
  • 3
0 votes
1 answer
235 views

decapsulating a MOSFET to create a bulk terminal

In my project, I would be using NMOS' and it would be very handy for me to have a bulk terminal. Since my choices of NMOS parts don't have bulk terminal, I was wondering if I could somehow decapsulate ...
Majin_Boo's user avatar
  • 187
0 votes
1 answer
58 views

How to find out which process triggered join_any in verilog

I have three tasks running in parallel and the fork joins when one of them gets completed. I would like to know which one was completed first and caused the fork to join. Is there a way to know it? <...
Nazar's user avatar
  • 3,212
0 votes
0 answers
111 views

What process (nm) are Microchip SAM D 21 microcontrollers made on?

I'm assuming that the whole family is made on the same process, but specifically I'm looking for ATSAMD21G18A series.
Paul Jurczak's user avatar
0 votes
0 answers
624 views

Power MOSFET versus regular MOSFET Silicon Layers

I am having some difficulties differentiating between a power MOSFET process and a regular MOSFET process. Here is a regular MOSFET silicon layer stackup: The n+ doped region for the source and ...
12Lappie's user avatar
  • 1,407
-1 votes
1 answer
2k views

How to calculate the number of pages of a process, and the size of the page table(in bytes)?

I just need a second opinion on the result that I got for a question to see if it is right. I am dealing with a computer system using paging, where the address space space of every process has a size ...
Othello's user avatar
-1 votes
1 answer
241 views

Xilinx Line <read_line> has not enough elements for target <input_b> for the file with more than one line

I have a file each line of which includes two 9 bits inputs. Here is an example of this file: input_vectors.txt: ...
Arghavan Mohammadhassani's user avatar
-2 votes
1 answer
224 views

Lead-lag process control

What is the locus of the following system, and for what value of \$\alpha\$ is the damping ratio 0.5?
Alireza Ghaffari's user avatar