Questions tagged [processor]

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Problem in executing the memory stage that can perform call, ret, pop, etc

I am trying to implement a Y86 processor for my college assignment. This is my MemoryStage: ...
Chiranjeevi K's user avatar
1 vote
1 answer
39 views

How to ensure a simple power sequence of a processor without a PMIC?

I need to integrate a video processor on a PCBA (part number: AllWinner S3, overview). It requires several power rails, and the power sequence is as follows: Power on: Power off: (page 380/384 of ...
uz3il's user avatar
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Making a model of an Intel 80386

On the internet there are some die shots of the 80386 but I am having a hard time finding one that contains descriptions or interpretations of each of its components. I need to make a model, and for ...
Vren's user avatar
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1 answer
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Is it possible to use a MOS 6502 with a AE29F2008?

I wanted to buy a MOS 6502, but before that, wanted to know if it is possible to interface it with an AE29F2008 memory (recovered from a PC). The problem is that the AE29F2008 has three address pins ...
jack07Code's user avatar
3 votes
3 answers
332 views

Necessary components for diy ATMega328

I am trying to build a barebones avr based circuit, based on designs i found on the internet. My questions are based on this sub-circuit: I don't plan on using a Reset button, thus S1 will be omitted....
user1584421's user avatar
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Is FLOP/s for a GPU constant with varied VRAM utilization?

Meaning is the compute output of a GPU a function of total VRAM being used, or perhaps any other variable?
Riley's user avatar
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-1 votes
2 answers
116 views

Replacement of RaspberryPi [closed]

I'm working with a learning project where I use an IMU sensor unit connected with Raspberry Pi 4B via UART. I receive data on Raspi's serial port and later I use that data to display it on a self made ...
Ashish1313's user avatar
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712 views

Help with Register File Implementation on Logisim

I'm currently working on an assignment that involves implementing a register file with 2 read ports and 1 write port on Logisim. I've made some progress but I'm struggling with a few questions and ...
mrAnonymous's user avatar
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42 views

Need help categorizing keywords and concepts for two different scenarios

I am currently working on a project that involves categorizing certain keywords and concepts into two different scenarios. I am having a bit of trouble determining which scenario each keyword belongs ...
tarek hankir's user avatar
-2 votes
2 answers
736 views

Need help understanding the concept of "power wall"

I am currently studying computer architecture and I am having some trouble understanding the concept of the "power wall". I came across the following statement: The term power wall ...
bittscoterie's user avatar
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0 answers
81 views

Need help understanding Dennard's scaling and multicore processors

I am currently studying computer architecture and came across the following statement: "Around 2006, Dennard’s scaling did not hold anymore. As a consequence, larger processor manufacturers ...
bittscoterie's user avatar
0 votes
1 answer
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Designing instruction emulating swap on a MIPS ISA with only 2 registers

In a typical MIPS ISA, you have only 2 working registers. But you have a large number of ALU units. How to design an instruction to emulate swap?
Nidhi's user avatar
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3 votes
1 answer
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How can memories be implemented efficiently with memory blocks of different sizes?

I am unsure if I am framing the question correctly, but here's what I wanted to ask. Let's say we want to implement a 64 kB memory. We would require a 16-bit address if we have byte-addressable memory....
Vedanta Mohapatra's user avatar
1 vote
0 answers
107 views

Access register values from a PicoBlaze / MicroBlaze soft processor

We are conducting research on the reliability of registers deployed in embedded RISC processors where the focus is to ensure the reliability of their contents during transient faults. To do this we ...
David777's user avatar
  • 1,578
10 votes
7 answers
4k views

How do 16-bit addresses work inside 8-bit data bus processors?

As a project I am building a small 8-bit RISC processor out of discrete ICs. I have 17 instructions and cannot fit all information into instructions that are only one byte, so I have been thinking ...
David777's user avatar
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1 vote
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27 views

Can we calculate leakage power after synthesis at the architectural level power analysis itself?

As I understand it, leakage power depends after implementation and not on the architectural level itself. When I report power after synthesis in Vivado I get even the leakage power. Is this possible ...
Nagendra Prasad's user avatar
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1 answer
212 views

Are FPGA and PC communications possible without a microprocessor i.e. do all FPGA dev boards have processors in? [closed]

I am new to FPGA design. I have worked on a Zedboard, used AXI bus and developed IP. However, I am not clear on some of the basic things. I would like to learn the following questions. My sincerest ...
Tan007's user avatar
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1 vote
1 answer
2k views

Why don't we see an MMU on a high-end MCU?

In the past, microcontrollers were fairly simple and had poor performance, making the idea of running a full OS on them not viable. Today, there are multi-core MCUs running at over 500 MHz (e.g. ...
FourierFlux's user avatar
3 votes
1 answer
130 views

Replacing a keypad on DYMO LetraTag

I'm rebuilding my label printer to become an Internet service using an ESP8266. It's a fun project, never mind the usefulness. The keypad will be removed and instead my MCU emulates keypresses. The ...
mikabytes's user avatar
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0 votes
1 answer
232 views

10gbase-kr autonegociation and ICs

My goal is to propose building a 3U VPX card which connects to a backplane. After some research, the preferred connection between cards is over 10gbase-kr (although SGMII is supported in some ...
alin_gtri's user avatar
3 votes
2 answers
1k views

maximum memory supported by processor - why often stated less than 1TB?

I want to understand technical details of limitations of maximum memory size a system / processor can support. Below what I was able to find via web search to date Wiki: Modern 64-bit processors such ...
Martian2020's user avatar
1 vote
0 answers
39 views

Are coarse-grained reconfigurable architectures a subset of dataflow architecture?

By definition, dataflow architectures consist of large modules in the dataflow path, such as adders and multipliers for integer, floating-point, or fixed-point computation. Hence, are coarse-grained ...
Giovanni's user avatar
-3 votes
2 answers
364 views

Why Intel does not make 5nm chips buying UV machines from ASML? [closed]

I've recently found out (correct me if I'm wrong here), that 5nm lithograthy machines are made by ASML, which is independent and Intel invested in it. I've tried web searches but I still do not ...
Martian2020's user avatar
0 votes
2 answers
60 views

How many instructions can a vector processor issue per cycle? [closed]

I currently have vector processors in class and wondered whether a vector processor only issues one (vector) instruction per cycle (in order processor). Maybe this question is stupid and it depends ...
Rhi's user avatar
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-1 votes
2 answers
443 views

What are the factors that determine the clock speed of a processor?

What are the factors that determine the clock speed of a processor? Since the speed of electricity is the same for all processors then I assume that how fast the binary data is transmitted to ...
Sayaman's user avatar
  • 109
0 votes
4 answers
366 views

Question about PID control loop timing

For my project I am creating a RISC processing architecture on an FPGA that can perform various basic instructions like adding, multiplying, subtracting, storing and fetching from memory etc. To prove ...
David777's user avatar
  • 1,578
4 votes
1 answer
10k views

Help in understanding Store Word (SW) instruction in Risc-V

So this is what I understood from what my professor said, but I don't think it's the right answer. What am I doing wrong? I'm sure It's just some small thing that I'm getting mixed up. Given ...
RhinoECE's user avatar
0 votes
2 answers
75 views

What is throughput as far as processors are concerned?

My teacher showed some algothrims, RR, FCFS and others. In the end he exposed a table with throughput of the algorithms. He explained what thoughput is but he failed miserably. He first said that ...
Diego Alves's user avatar
1 vote
1 answer
1k views

How can I modify single-cycle MIPS processor to implement jal command?

Hello Stack exchange community I was wondering which modification should I have to make in order to enable single-cycle MIPS processor to run a jal(jump and link) command? My most pressing confusion ...
Amir's user avatar
  • 11
0 votes
1 answer
222 views

Number of read and write ports on L2 and L3 cache

I have an Intel Core i9-9900K processor (some specs here) and I'm trying to figure out how many read and write ports each level of cache has, for a personal project. I cannot find this in any online ...
Anthony Krivonos's user avatar
0 votes
2 answers
175 views

How are transistors on processor chips designed to withstand high operating temperatures?

The process for transistors grow smaller every few years, and operating temperatures reach around 100 degree Celsius. This makes one wonder as to how these tiny designs are able to hold up within ...
Nikhil Sadasivan's user avatar
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0 answers
145 views

What processor architecture is in a 230GMULps KPU design?

While AI products are becoming popular recently, when looking at the "Seeed Studio Grove AI HAT for Edge Computing Artificial Intelligence Board" it mentions a RISC-V, a 230GMULps 16-bit KPU ...
minghua's user avatar
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0 votes
1 answer
74 views

confusion understanding a processor?

As shown highlighted in attached photo,In case of 6713 dsp,during each clock cycle, up to eight instructions can be carried out in parallel Does this happen in case of every processor that multiple ...
DSP_CS's user avatar
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0 votes
1 answer
203 views

Single Cycle Data-path Requirements

How having separate instruction and data memories helps in implementing a single cycle data-path for mips instruction set? i want to know why we can only use data-path element once in a cycle for ...
Karan Verma's user avatar
1 vote
3 answers
1k views

Effect of doubling clock frequency on computer performance

If we double the clock frequency of a CPU, does that translate to a doubling of the CPU performance? Assuming that the number of instructions and CPI are constant, we have an inverse relationship ...
Ski Mask's user avatar
  • 143
15 votes
4 answers
9k views

Where are registers and what do they look like?

I racked my brain through my comp-arch class and reread wiki’s article on hardware registers (they’re flip-flops, I get that), but one year later and I still don’t understand what a register ...
JohnnyApplesauce's user avatar
0 votes
0 answers
34 views

Does stage Sy of instruction have to wait till all earlier instructions has executed their corresponding stage

I am trying to understand execution of instruction in RISC pipeline. Can stage Sy of instruction I2 execute before stage Sy of I1? That is, in below example, will it be allowed to run I2's ID in C3 as ...
RajS's user avatar
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1 vote
2 answers
152 views

How do I procure SoCs in small quantities? [closed]

I want to design an SBC but I am having difficulty with buying the SoC. I'm thinking of Snapdragon, Mediatek, Allwinner, Amlogic and Rockchip (These are the ones I know, if you know others I would ...
kadhem alabdulmuhsin's user avatar
1 vote
4 answers
227 views

royalty free embedded processor [closed]

I got into FPGA design last year for a project, and had some success with a Xilinx Spartan 6 dev board using ISE. I could do everything with this low cost board and ISE 14, which is free. I needed an ...
danmcb's user avatar
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0 votes
2 answers
679 views

Data Bus and High Impedance

Let's consider an interface between a simple microprocessor and a certain memory. For instance, let's assume that the microprocessor drives the address bus, a read signal, a write signal, and that the ...
Kinka-Byo's user avatar
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0 votes
2 answers
110 views

Need a processor to be able to turn off its own power

I have a processor that is powered by a mains 5V power from a wall adapter, and has a short term battery backup. I need the processor to turn on automatically and immediately when 5V mains supply is ...
R2D2's user avatar
  • 167
-1 votes
2 answers
70 views

Data transfer from/to memory [closed]

Consider an interface (between a memory and a processor, or between a memory and an ASIC, or similar situations) in which there is a data bus of 8 bit. Suppose I want read a 16 bit data from memory, ...
Kinka-Byo's user avatar
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1 vote
1 answer
2k views

Understanding branch delay slot and branch prediction prefetch in instruction pipelining

Let me define: Branch delay slot: Typically assemblers reorder instructions to move some instructions immediately after branch instruction, such that the moved instruction will always be executed, ...
RajS's user avatar
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1 vote
0 answers
50 views

Finding percentage memory utilization in pipelining architecture

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Consider stage latencies: ...
RajS's user avatar
  • 227
0 votes
1 answer
462 views

Why cant we increase chip area?

According to Moore's law, transistors are getting double every 24 months. But now, we have reached the transistor size limit which results in leakage current. Then why can't we increase chip area size,...
srccode's user avatar
  • 101
3 votes
2 answers
5k views

How many stall cycles resulted by incorrectly predicted branch in instruction pipelining

I have been solving following exercise problem from book Computer Organization by Patterson and Hennessy: The importance of having a good branch predictor depends on how often conditional branches ...
RajS's user avatar
  • 227
0 votes
2 answers
67 views

Have separate instructions for each register or pass register as argument?

I am trying to design a (very) simple processor architecture. I am in the process of creating a basic instruction set for it, however I am not sure of the best ("best" meaning what most people use - ...
Jachdich's user avatar
  • 145
1 vote
1 answer
92 views

Analog Blackfin Processor Silicon Revision issue [closed]

Recently we got a large batch of ADSP-BF5346s that say they are Silicon Rev 3 but internally read as Rev 2. Is there a way for me to determine the Silicon Revision number on the rest of the shipment ...
JFisher's user avatar
  • 13
1 vote
1 answer
2k views

Multi-source in Unit <> on signal <>; this signal is connected to multiple drivers

I'm trying to design a multiprocessor in Verilog. ...
Peter's user avatar
  • 123
5 votes
1 answer
2k views

Inside a CPU, what happens in a single clock cycle?

In grossly simplified terms, a processor calculates 1 instruction in a single clock cycle. But what does that even mean? If a processor is a bunch of transistors, is 1 clock cycle simply 1 state ...
user3629081's user avatar