Questions tagged [processor]
The processor tag has no usage guidance.
103
questions
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57 views
What is throughput as far as processors are concerned?
My teacher showed some algothrims, RR, FCFS and others. In the end he exposed a table with throughput of the algorithms. He explained what thoughput is but he failed miserably. He first said that ...
0
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1answer
87 views
How can I modify single-cycle MIPS processor to implement jal command?
Hello Stack exchange community
I was wondering which modification should I have to make in order to enable single-cycle MIPS processor to run a jal(jump and link) command?
My most pressing confusion ...
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0answers
22 views
Number of read and write ports on L2 and L3 cache
I have an Intel Core i9-9900K processor (some specs here) and I'm trying to figure out how many read and write ports each level of cache has, for a personal project. I cannot find this in any online ...
0
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2answers
65 views
How are transistors on processor chips designed to withstand high operating temperatures?
The process for transistors grow smaller every few years, and operating temperatures reach around 100 degree Celsius. This makes one wonder as to how these tiny designs are able to hold up within ...
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0answers
65 views
What processor architecture is in a 230GMULps KPU design?
While AI products are becoming popular recently, when looking at the "Seeed Studio Grove AI HAT for Edge Computing Artificial Intelligence Board" it mentions a RISC-V, a 230GMULps 16-bit KPU ...
1
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1answer
59 views
confusion understanding a processor?
As shown highlighted in attached photo,In case of 6713 dsp,during each clock cycle, up to eight instructions can be carried out in parallel
Does this happen in case of every processor that multiple ...
0
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1answer
42 views
Single Cycle Data-path Requirements
How having separate instruction and data memories helps in implementing a single cycle data-path for mips instruction set? i want to know why we can only use data-path element once in a cycle for ...
1
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3answers
308 views
Effect of doubling clock frequency on computer performance
If we double the clock frequency of a CPU, does that translate to a doubling of the CPU performance? Assuming that the number of instructions and CPI are constant, we have an inverse relationship ...
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4answers
5k views
Where are registers and what do they look like?
I racked my brain through my comp-arch class and reread wiki’s article on hardware registers (they’re flip-flops, I get that), but one year later and I still don’t understand what a register ...
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34 views
Does stage Sy of instruction have to wait till all earlier instructions has executed their corresponding stage
I am trying to understand execution of instruction in RISC pipeline.
Can stage Sy of instruction I2 execute before stage Sy of I1? That is, in below example, will it be allowed to run I2's ID in C3 as ...
0
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0answers
65 views
Why is 7 nm Process Node called 7 nm?
I found this on wikipedia: "The naming of process nodes by different major manufacturers (TSMC, Intel, Samsung, GlobalFoundries) is partially marketing-driven and not directly related to any ...
0
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2answers
80 views
How do I procure SoCs in small quantities? [closed]
I want to design an SBC but I am having difficulty with buying the SoC. I'm thinking of Snapdragon, Mediatek, Allwinner, Amlogic and Rockchip (These are the ones I know, if you know others I would ...
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4answers
202 views
royalty free embedded processor [closed]
I got into FPGA design last year for a project, and had some success with a Xilinx Spartan 6 dev board using ISE. I could do everything with this low cost board and ISE 14, which is free. I needed an ...
0
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2answers
210 views
Data Bus and High Impedance
Let's consider an interface between a simple microprocessor and a certain memory. For instance, let's assume that the microprocessor drives the address bus, a read signal, a write signal, and that the ...
0
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2answers
98 views
Need a processor to be able to turn off its own power
I have a processor that is powered by a mains 5V power from a wall adapter, and has a short term battery backup.
I need the processor to turn on automatically and immediately when 5V mains supply is ...
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2answers
59 views
Data transfer from/to memory [closed]
Consider an interface (between a memory and a processor, or between a memory and an ASIC, or similar situations) in which there is a data bus of 8 bit. Suppose I want read a 16 bit data from memory, ...
1
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1answer
242 views
Understanding branch delay slot and branch prediction prefetch in instruction pipelining
Let me define:
Branch delay slot: Typically assemblers reorder instructions to move some instructions immediately after branch instruction, such that the moved instruction will always be executed, ...
1
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0answers
24 views
Finding percentage memory utilization in pipelining architecture
I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this:
Consider stage latencies:
...
0
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1answer
247 views
Why cant we increase chip area?
According to Moore's law, transistors are getting double every 24 months. But now, we have reached the transistor size limit which results in leakage current. Then why can't we increase chip area size,...
2
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1answer
2k views
How many stall cycles resulted by incorrectly predicted branch in instruction pipelining
I have been solving following exercise problem from book Computer Organization by Patterson and Hennessy:
The importance of having a good branch predictor depends on how often conditional branches ...
0
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2answers
51 views
Have separate instructions for each register or pass register as argument?
I am trying to design a (very) simple processor architecture. I am in the process of creating a basic instruction set for it, however I am not sure of the best ("best" meaning what most people use - ...
1
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1answer
68 views
Analog Blackfin Processor Silicon Revision issue [closed]
Recently we got a large batch of ADSP-BF5346s that say they are Silicon Rev 3 but internally read as Rev 2. Is there a way for me to determine the Silicon Revision number on the rest of the shipment ...
0
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1answer
1k views
Verilog) Multi-source in Unit <> on signal <>; this signal is connected to multiple drivers
Hi I'm trying to design a multiprocessor in Verilog.
...
4
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1answer
649 views
Inside a CPU, what happens in a single clock cycle?
In grossly simplified terms, a processor calculates 1 instruction in a single clock cycle. But what does that even mean? If a processor is a bunch of transistors, is 1 clock cycle simply 1 state ...
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5answers
3k views
In a CPU, does the speed of a calculation affect the heat generated?
Take as an example a CPU that is capable of changing its clock speed, like a modern computer CPU (Intel, AMD, whatever). When it does a certain calculation at a particular clock speed, does it ...
1
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3answers
350 views
Computer architecture why is MemRead used?
Why is a control signal MemRead needed for the Data Memory element if whenever the output Read Data is not desired it will be multiplexed out via MemtoReg?
Wouldn't having MemRead always enabled ...
0
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1answer
206 views
What is the best way to implement spi using 8085? [closed]
I have to make a compass using 8085. I have to take serial data from magnetometer of mpu9250. Should i prefer bit banging to implement spi or make parallel out and parallel in hardware using shift ...
3
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1answer
139 views
Finding specifications for digital signal processors (DSPs) for given audio application [closed]
I'm finding difficulties choosing an adequate processor solution for my application from my null experience with DSP:
8ch 24-bit @11025Hz I2S TDM Input
Beamforming + ASNR
MSS Multi-source selection
...
0
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1answer
45 views
Lpc 43s50FET256 processor and its connections
ı want to buy a nxp LPC43S50FET256 processor and ı made some research but I dont know whether lpc43s50 has already got bridge connections, ı also dont know for example whether ethernet is already ...
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1answer
226 views
Finding percentage accuracy of instruction pipeline branch predictor
I need help in understanding the solution from solution manual. The question is from the exercise 4.24.4 and 4.24.5 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey ...
1
vote
1answer
300 views
Understanding execution of sequence of pipeline instructions
I need help in understanding the solution from solution manual. The question is from the exercise 4.22.2 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
0
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1answer
123 views
Understanding instruction branching
I need help in understanding the solution from solution manual. The question is from the exercise 4.22.1 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
0
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2answers
132 views
Methods to detect errors in cache
Are there methods apart from ECC, to detect and possibly correct cache errors?
0
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0answers
350 views
Understanding instruction pipelining speedup calculation
I was solving the exercise problem 4.17.6 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th edition):
Percentage occurrences of the instructions are as ...
0
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1answer
408 views
Understanding processor instruction pipeline problem solution
I need help in understanding the solution from solution manual.
The question is from the exercise 4.13.5 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
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1answer
68 views
USB RF Videotransmission, is it possible? [closed]
I am thinking about building my next rc plane complete from scratch. I wanted to do the programming by myself, so I have the problem, that I can't use any 5.8Ghz video transmitter because I can't ...
0
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4answers
1k views
How does VCO in PLL in computer processor work?
In todays personal computers and notebooks, what is usually used as a Voltage-Controlled Oscillator for generating clock signal for processor?
Is that a crystal rather than RC circuit?
Is it tuned by ...
-1
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4answers
320 views
How calculator's processor works in a base manner? [closed]
For example, when we click the "3" number button or "+" button, what it sends to processor ? I want an answer something like = " It come first MAR, then goes to Memory, then comes ALU " in this manner ...
3
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2answers
2k views
Do multi-core processors reduce power consumption?
I have been reading some tutorials about power consumption on parallelized system. I have been following this tutorial.
Tim Mattson (Intel): Introduction to OpenMP: 02 part 1 Module 1, YouTube
At ...
1
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2answers
164 views
Multi-core processor and Real Time [closed]
Is it a good idea to design a real time system on a multicore processor? Task's execution time isn't determinist in these kind of processor because of core management. This makes scheduler's ...
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2answers
565 views
Where can I find the definition of SMI, SCI pins on a CPU?
I am trying to understand the SMI (System Management Interrupt) and SCI (System Control Interrupt) in IA32 architecture.
According to this thread, it seems a CPU should have dedicated pins for SMI ...
2
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2answers
3k views
Are there 8 bit ARM processors?
Is there anything below 32-bits for an ARM processor? I was wondering if there is or ever was an 8-bit ARM processor. I've searched but not seen any and so it seems that ARM processors are either 32 ...
2
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2answers
2k views
Arm mode and Thumb mode makes the PC's bit 0
The ARM and Thumb modes are word-aligned and halfword-aligned. I understand this means that if it's in ARM mode, the start of addresses must be divisible by 32, and if it's in Thumb mode it has to be ...
1
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1answer
323 views
Why is register file latency, during write-back stage, not included in computing for minimum clock cycle time
I was looking at the solution for a homework posted here:
https://cseweb.ucsd.edu/classes/sp13/cse141-a/solutions/assignment4_solutions.pdf
and noticed that for 1.1, it didn't include the Register ...
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1answer
2k views
Micro processor logic gates
Where to get a logic level diagram for a processor , preferably intel 4004.
i have block diagrams but want it to know more at logic level then transistor level.
1
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1answer
368 views
Using a high frequency LPDDR3 RAM with a lower RAM frequency supported Processor
I'm designing a board with Allwinner A64 processor and i'm confused in choosing the proper RAM. the SDRAM controller characteristics of the processor is listed as follows:
Compatible with JEDEC ...
0
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2answers
156 views
Is it 'ok' to use a switched power supply to power a processor core?
I'm currently working on a project which features an Analog Devices Blackfin DSP Digikey link. This DSP requires 1.3V to power the core. I plan on having my project be battery powered, thus I'm ...
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1answer
1k views
What is the exact type of oil used in immersion cooling of electronic devices such as processors?
I am looking for cooling solutions for a data center with low PUE. I can see that there is an immersion cooling option which uses a very specific oil based liquid that is non conductive but can ...
2
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1answer
338 views
Multiple Cores vs Single Core Power Efficiency Equations
I was searching for OpenMP tutorials and I came up a video that showed some simple equations that promotes multiple core hierarchies against single core ones.
The equations used are
Capacitance = ...
1
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1answer
103 views
How much embedded program memory in this NXP (aka freescale) KL03 processor?
Is there a way to find out how much programming memory is in an NXP (aka freescale) KL03 ARM processor? The markings on the chip say "P03T5V" and "PSABA".
There is this NXP package number lookup web ...
