Questions tagged [processor]

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how work with TCD1304 AP ccd line sensor

hello every one for a project i need to work with a line sensor TCD1304 AP . here it's the data sheet link http://www.spectronicdevices.com/pdf/TCD1304AP.pdf i don't know what's the exactly protocol ...
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24 views

Finding percentage memory utilization in pipelining architecture

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Consider stage latencies: ...
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1answer
307 views

Why is register file latency, during write-back stage, not included in computing for minimum clock cycle time

I was looking at the solution for a homework posted here: https://cseweb.ucsd.edu/classes/sp13/cse141-a/solutions/assignment4_solutions.pdf and noticed that for 1.1, it didn't include the Register ...
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Number of read and write ports on L2 and L3 cache

I have an Intel Core i9-9900K processor (some specs here) and I'm trying to figure out how many read and write ports each level of cache has, for a personal project. I cannot find this in any online ...
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What processor architecture is in a 230GMULps KPU design?

While AI products are becoming popular recently, when looking at the "Seeed Studio Grove AI HAT for Edge Computing Artificial Intelligence Board" it mentions a RISC-V, a 230GMULps 16-bit KPU ...
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1answer
34 views

Single Cycle Data-path Requirements

How having separate instruction and data memories helps in implementing a single cycle data-path for mips instruction set? i want to know why we can only use data-path element once in a cycle for ...
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88 views

How to properly implement a crowbar circuit to perform a fault injection / power glitch attack?

I am trying to implement a power glitch attack. This is a hardware attack in which for a very short period of time (order of nanoseconds) I remove the power to a processor, using a transistor, to ...
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34 views

Does stage Sy of instruction have to wait till all earlier instructions has executed their corresponding stage

I am trying to understand execution of instruction in RISC pipeline. Can stage Sy of instruction I2 execute before stage Sy of I1? That is, in below example, will it be allowed to run I2's ID in C3 as ...
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63 views

Why is 7 nm Process Node called 7 nm?

I found this on wikipedia: "The naming of process nodes by different major manufacturers (TSMC, Intel, Samsung, GlobalFoundries) is partially marketing-driven and not directly related to any ...
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319 views

Understanding instruction pipelining speedup calculation

I was solving the exercise problem 4.17.6 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th edition): Percentage occurrences of the instructions are as ...
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319 views

Understanding processor instruction pipeline problem solution

I need help in understanding the solution from solution manual. The question is from the exercise 4.13.5 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...