Questions tagged [processor]

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Finding percentage memory utilization in pipelining architecture

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Consider stage latencies: ...
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340 views

Why is register file latency, during write-back stage, not included in computing for minimum clock cycle time

I was looking at the solution for a homework posted here: https://cseweb.ucsd.edu/classes/sp13/cse141-a/solutions/assignment4_solutions.pdf and noticed that for 1.1, it didn't include the Register ...
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Simulink - STM32 - PIL test communication error

I have a Simulink model that contain an algorithm block. I built the generated c code succesfully to STM32F4-discovery board. (I read that from diagnostic viewer.) I used SIL/PIL Manager App to make ...
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Help in understanding Store Word (SW) instruction in Risc-V

So this is what I understood from what my professor said, but I don't think it's the right answer. What am I doing wrong? I'm sure It's just some small thing that I'm getting mixed up. Given ...
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1answer
179 views

How can I modify single-cycle MIPS processor to implement jal command?

Hello Stack exchange community I was wondering which modification should I have to make in order to enable single-cycle MIPS processor to run a jal(jump and link) command? My most pressing confusion ...
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25 views

Number of read and write ports on L2 and L3 cache

I have an Intel Core i9-9900K processor (some specs here) and I'm trying to figure out how many read and write ports each level of cache has, for a personal project. I cannot find this in any online ...
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72 views

What processor architecture is in a 230GMULps KPU design?

While AI products are becoming popular recently, when looking at the "Seeed Studio Grove AI HAT for Edge Computing Artificial Intelligence Board" it mentions a RISC-V, a 230GMULps 16-bit KPU ...
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46 views

Single Cycle Data-path Requirements

How having separate instruction and data memories helps in implementing a single cycle data-path for mips instruction set? i want to know why we can only use data-path element once in a cycle for ...
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34 views

Does stage Sy of instruction have to wait till all earlier instructions has executed their corresponding stage

I am trying to understand execution of instruction in RISC pipeline. Can stage Sy of instruction I2 execute before stage Sy of I1? That is, in below example, will it be allowed to run I2's ID in C3 as ...
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380 views

Understanding instruction pipelining speedup calculation

I was solving the exercise problem 4.17.6 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th edition): Percentage occurrences of the instructions are as ...
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446 views

Understanding processor instruction pipeline problem solution

I need help in understanding the solution from solution manual. The question is from the exercise 4.13.5 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...