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Questions tagged [programmable-logic]

Programmable digital logic devices include FPGAs, CPLDs, and older devices such as GALs and PALs. Programmable logic enables flexibly implementing complex digital functions in a single chip, from a few gates of glue logic to entire microprocessors or complex signal processing systems.

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181 views

Can an EPROM be “refreshed” without UV erasing?

I have lots of AM27C512 65k x 8b EPROMS (with the UV window) which are quite old (1980's.) Using a Xeltek SuperPro 3000U, most can still be read and verified. A few have failed outright and were ...
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1answer
55 views

Why do ICs need a specific Power Down Sequence?

When powering down a board, for ICs that have multiple supply voltage rails, why do they need a specific Power Down Sequence? Typically in complex motherboards, there is a CPLD doing the job of this ...
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3answers
181 views

True 5V CPLD other than PIC/Altera ATF150*?

Are there any True 5V CPLD's families still in manufacturing other than PIC/Atmel ATF150*? I am talking not just "5V tolerant IO", but rather ones with 5V VCCIO, able to drive 5V loads without ...
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0answers
19 views

Using generic tools to program ATF150X series CPLDs from a JEDEC file (understanding JTAG details)

I have a number of ATF1504 44 pin PLCC CPLD devices. I can design for them without a problem to get a JEDEC file. I want to program them via the JTAG ISP interface which has the same pinout as the ...
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1answer
51 views

Including and extra product term on same chip in a PAL implemntaion

To implement a circuit we have a PAL requirement 4-input,4-output,(2,2,2,2) product terms.We are using a chip with 8 inputs,8 outputs(4 reg, 4non reg)(2,2,2,2,2,2,2,2). But it happened that we made a ...
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1answer
95 views

Verilog - connecting multiple bidirectional buses

I've been designing a retro computer in verilog as an exercise and so far have a simple 8-bit CPU that communicates directly with a single RAM chip via a bidirectional data port. This works great in ...
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1answer
26 views

Can I estimate what CPLD I need?

I'm planning to design a driver for VGA connectors, and for testing purposes I have an evaluation board of one CPLD. Concretely, the board is the Digilent's CoolRunner-II with the Xilinx's XC2C256 ...
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1answer
29 views

register enable line usage in `case` block (verilog synthesis for altera cpld)

I have the following in a verilog design aimed at an altera CPLD (currently targeting EPM240, although the target device isn't set in stone): ...
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2answers
91 views

7 segment display for hexadecimal numbers using PLAs

I'm trying to design 7 segment display for single digit hexadecimal numbers using PLAs but I am getting more than 16 product terms .If I implement using PROM it uses exactly 16 product terms(all min-...
2
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1answer
109 views

How can I program GALs on a shoestring budget?

GALs may be obsolete technology, but they're still readily available, and are dirt cheap. For a hobbyist like myself, they're ideal for small projects that need something a little faster than a low ...
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0answers
64 views

MAX10 .pof file issue, quartus II and usb blaster

After a MAX10 board revision. When programming the MAX10 with .pof, the MAX10 board do not start when power-on or after .pof programming is completed. However, normal operation is achieved when ...
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1answer
64 views

Create a low frequency oscillator with CPLD TTL input and output

I have 2 available pins on a CPLD which is a 5V TTL device (ATF750C-10PU). The inputs are just regular logic not Schmitt trigger. One pin is an output, while the other is an input. I would like to ...
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3answers
107 views

Low risk entry into CPLD/FPGA design? [closed]

I have a possible project coming up that looks like it needs a small amount of digital logic (to generate some synchronous timing/control signals). Speed is not that high, in the low megahertz. My ...
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2answers
50 views

Line remapping using a CPLD

On the product I am designing, I have an input connector of 60 lines and an output connector of 32 lines. The input can be connected to different outside products and then the lines can be mixed, so ...
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1answer
46 views

Interfacing a temperature sensor with PLD without implementing SPI/I2C bus

Are there any temperature sensors which can be interfaced with PLDs without having to implement a SPI/I2C bus at the PLD end. I am looking for something which can be interfaced without having to be ...
0
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1answer
87 views

FPGA and CPLD bootloader [closed]

Coming from the world of MCUs, I create bootloaders so that customers can update the firmware. Specifically, i'm talking about a USB bootloader to narrow down the many different mediums. How is this ...
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0answers
20 views

Understanding fuzzy logic parameters for my control surface

I need to use fuzzy logic to model a control surface that follows the equation: \$ z = 4 \exp[-0.15(x-4)^2 -0.3(y-2.5)^2 ] \$ where x and y are integers in the inclusive interval [0,4]. I want to ...
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6answers
3k views

Discrete logic design

I have been tasked with building a simple alarm device. It just needs to measure a few inputs and the outputs will respond accordingly (to put it very simply!). To me, it seemed that using a few ...
0
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1answer
73 views

Altera Max10 altPLL slack

Regarding a MAX10 board. The whole design inside the MAX10 is clocked from a single clock using verilog's always@(posedge clockin). If connect directly a 80mhz clock to a Max10 input pin and define ...
0
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1answer
67 views

Need help understanding the status output generation of an ALU

I'm currently trying to implement a simple processor using Verilog in a FPGA. I'm using Mic - 1 architecture as a reference model. The thing I can't understand is the ALU is generating a "status" ...
4
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3answers
773 views

CPLD is (sometimes) not incrementing counter

I have this simple program running on the Altera EPM240 that’s sometimes not doing the counter increment. ...
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1answer
170 views

74LS161 in program counter circuit jumps clock cycles

I have recently been working on an 8-bit computer (Ben Eater-YouTube) and I have run into a very significant problem. My program counter seems to not work. When pulsing through a command I see that it ...
2
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2answers
135 views

VHDL: Demultiplexing a signal to one of many outputs while driving unused outputs to '0'

I'm attempting to create synthesisable VHDL that will demultiplex a one-bit continuous signal stream to one of many outputs. The outputs that aren't being sent this stream should be set to '0'. See ...
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1answer
100 views

Can I learn VHDL on a CPLD device?

I need to learn and practice VHDL, so I wouldlike to buy a small FPGA dev board. I've found a board based on a MAX10 circuit with the exact form factor I need, but I've read this chip is a CPLD, not a ...
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3answers
1k views

Can I use C language to program a CPLD/FPGA?

I wanted to know if I can program CPLDs /FPGAs using C language? If so, is it commonly practiced? What are the steps and the required & tools for the same?
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0answers
70 views

Verilog Code Optimisation

I have recently become involved in FPGA design and I am just testing out some new Zync SoC hardware. I have followed a tutorial online to blink some LED's however I have modified it to blink all the ...
0
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0answers
69 views

The cheapest and best way to drive a coin vibrator Motor in only one direction

I am a beginner at power electronics so bear with me. I am planning to drive a lot of coin vibrator motors(around 64) with pwm. here is the datasheet : https://www.parallax.com/sites/default/files/...
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0answers
109 views

How to interface dc motor(3V) with raspberry Pi 3

I am building an accident alert system. I am controlling dc motor speed on the basis of distance measured by the ultrasonic sensors. Til now,I have interfaced the ultrasonic sensor with the Pi, but I ...
0
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1answer
135 views

circuit programming using a SPLD or CPLD as a 16 bit (addressable memory) microcontroller [closed]

SPLD Reference https://www.arrow.com/en/categories/programmable-devices/programmable-logic-devices/splds CPLD Reference https://www.arrow.com/en/categories/programmable-devices/programmable-logic-...
1
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1answer
369 views

What is difference between register and distributed RAM

I'm trying to understand what is purpose of distributed RAM as a concept. As far as I understand it is implemented using LUTs just as registers are. However registers seems to be much more flexible: <...
4
votes
2answers
145 views

Are there FPGA chips that permit to update the programmable logic from the logic itself?

For the research purpose I am interested are there FPGA chips that are capable to update the bytestream (the programmable logic) from the bytestream itself?
3
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1answer
93 views

How much RAM can I get from a MAX V logic element?

I need a CPLD or an FPGA in a hobby project. Since I have no experience of it I am trying to evaluate the different options and brands based on the constraints I already know, so that I can buy an ...
0
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1answer
68 views

Power on configuration for MCU using CPLD and pin multiplexing

simulate this circuit – Schematic created using CircuitLab Suppose we have simple same here. The logic behind this is very simple. During MCU boot it tests pins CONF1 and CONF2 for data on it (...
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1answer
52 views

How to program the P5Z22V10-da?

I got a handful of these chips at my job when they were being thrown away. They are Programmable Logic Devices. I found a datasheet online from 1997 that says that xilinx bought the ip for a similar ...
0
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2answers
295 views

8 to 3 Priority Encoder. Answer Verification

I am trying to design a priority encoder with a given priority table. Input: I0 I1 I2 I3 I4 I5 I6 I7 Priority: 2 7 6 1 5 0 3 4 Image attached!! Are these correct? Or I am failing?
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2answers
175 views

Not understanding why “if” is not triggered in modelsim vhdl sim

I am using a programmable-logic to decode a sequence of long or short impulses into latin letters according to morse code. I am using VHDL to describe our design, to be precise I'm using Quartus Prime ...
2
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3answers
165 views

What is the modern way to do small scale programmable logic?

I am designing a circuit for an electronic coil winder. It has a few binary counters, equality detectors, 7 segment decoders and flip flops. How it is possible to get all of this logic onto 1 ...
0
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1answer
547 views

Using Altera Max II Internal Oscillator

So I'm just getting my feet wet with CPLDs, in fact I programmed a chip successfully for the first time last night (success being programming it with the correct program, not the one recovered from it ...
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0answers
95 views

ABEL vs. VHDL edge detection

how can I detect signals edges in ABEL language? In other words, there is an equivalent of 'event (VHDL) in ABEL? Thanks for your help!
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2answers
312 views

Altera Max10 3.3V interface

Regarding Altera's MAX10 Cpld, I got some questions regarding the interface of this CPLD with 3.3V devices. I have set pins to 3.3V LVCMOS and I got this warning message in quartus: "Warning (169177):...
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1answer
337 views

How do I generate a .JED file for programming an ATF750C using VHDL language?

I know how to program regular PAL/GAL22V10 chips and I am interested in using the enhanced Atmel ATF750C CPLD device because it seems 100% pin- and voltage-compatible with the PAL/GAL22V10 chips. I ...
0
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1answer
50 views

Level converter usage when Vccb not present

I'm looking at incorporating a LSF0108 level shifter into a design to convert bidirectional GPIO signals from a 1.8V CPLD (Vcca) to an off-board device via ribbon cable. The header contains a voltage ...
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votes
1answer
205 views

Spartan 6 Internal Memory [closed]

I am referring to below datasheet of IC XC6SLX45-L1FGG484C-ND. As per Digikey portal, it has Total RAM Bits = 2138112 If I want use internal RAM memory is there any specific pins associated with ...
0
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1answer
85 views

What triggered the need for VLSI chips in modems post 1200 baud?

I was chatting to my boss today and he said: My first job was electrical working in a factory for a modem company. The last model modem we made was the 1200 baud. After that they needed ...
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2answers
289 views

Altera MAX10 CPLD initialization IO state

I'm designing a pcb with an Altera MAX10 (10M02) CPLD used to do, amongst other things, bus arbitration between several memory chips (one /CS per chip). All the memory chip are on same bus so only ...
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0answers
47 views

ABEL-HDL - Default/reset values

I have as a school task to make a clocks & calendar in a HDL. As a source I have 10 MHz oscilator, which I managed to "slow down" to 1 Hz, as I want. I have asynchronous counters for seconds, ...
4
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1answer
594 views

Is this the correct way putting multiple chips into one JTAG chain?

I am thinking about a hobby project that have a microcontroller and a CPLD connected together. Is this the correct way doing it? simulate this circuit – Schematic created using CircuitLab ...
8
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2answers
413 views

MITM on I2C Bus

I've been trying to design a module that will allow me to modify selected slave responses on an I2C bus. Here is the original bus configuration (the pull-ups and power connections are not shown for ...
1
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1answer
339 views

What are the low level programming waveforms for the Atmel ATF16V8B?

I want to program some ATF16V8B chips for a project. Naturally I don't have a programmer. No problem, I'll homebrew it with a Raspberry Pi. It will be fun. I only need one thing - I need the ...
1
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1answer
172 views

CPLD use with 6800 processor

Quick, and potentially silly question. I'm working on an old board design (late 70's) that utilizes a 6800 processor. The current board design left a few address lines from the CPU unused. I'd like ...