Questions tagged [programmable-logic]

Programmable digital logic devices include FPGAs, CPLDs, and older devices such as GALs and PALs. Programmable logic enables flexibly implementing complex digital functions in a single chip, from a few gates of glue logic to entire microprocessors or complex signal processing systems.

Filter by
Sorted by
Tagged with
0
votes
0answers
19 views

Allen Bradley PLC 5555 IO not responding [on hold]

Don't have any idea about plc programming.anyone identify what's the issue with the tree .. the io not responding blinks and warning symbol on I/o configuration folder
0
votes
1answer
53 views

Implementing 4-bit counter on GAL 16V8

I want to use a GAL 16V8 to implement a 4-bit counter using Verilog. I'm using Lattice's ispLEVER software. So far I have had no issues using Verilog to implement combinational logic. However, I ...
0
votes
0answers
13 views

What is BUFG constraint?

In Xilinx ISE I've made a small VHDL-code for a CPLD (XC2C32A) without a constraint file. On "Implement design" I right-clicked and chose "Run", and I got green checkmarks on Synthesize, Translate, ...
0
votes
0answers
9 views

Termination mode for CoolRunner CPLD (XC2C32A)

Fitting properties in Xilinx ISE offers some options for -unused and -terminate: ...
-1
votes
1answer
61 views

In practical, what really is a memory word in PLC?

I came across some plc code (structured text) being used in an industrial company. When I asked the question, I got a blurry answer. However, what I picked up is that it has something to do with the ...
3
votes
1answer
38 views

What does the % symbol mean on plc addresses?

I've seen contacts assigned with a % symbol on ladder diagrams and plc structured text. For example a normally open start button would be %I1.02 and a coil would be %Q5.3 I understand the I and Q is ...
0
votes
0answers
22 views

PLC Ladder Logic using LRXSW

I'm working on a project for a summer internship and was hoping for some assistance with PLC Ladder Logic. I have been trying for the last couple of days to program the PLC to do what I want but have ...
0
votes
1answer
62 views

VHDL: case when using constants constructs

I'm having some trouble with the following statement ...
0
votes
1answer
67 views

Are Verilog always blocks synthesized so that the sensitivity list items are settled by the time the block behavior is carried out?

In other words, if signal goes high and triggers the always block, will the block be synthesized in a way that the behavior in ...
0
votes
4answers
87 views

AC-Coupling on Composite video

Many sources say that composite video input should be AC-coupled. Voltage levels for blank, black and white signal are also specified. How is it possible to detect these voltage levels after AC ...
0
votes
3answers
95 views

On-the-fly routing of digital and analog signals using unbuffered analog crosspoint arrays?

The issue I have is strongly related to a question which was asked over here. Unfortunately I did not find the answer I was looking for. Digging a bit more I've came across a class of IC's named ...
2
votes
2answers
715 views

CPLD based Pierce oscillator

I want to make a clock generator for Altera EPM240T100C5N using the CPLD itself as a Pierce oscillator. This CPLD has Schmitt trigger inputs so I guess this should be possible. What I`m not sure about ...
1
vote
1answer
117 views

Naming of PLA and PAL

I am studying the Programmable Logic Array (PLA) and Programmable Array Logic (PAL). I understood every detail I found about them including the implementation and difference between them. But I have a ...
0
votes
1answer
116 views

PLDs, DSPs, MCUs, MPUs and SoCs Typical Application [closed]

PLDs, DSPs, MCUs, MPUs and SoCs are all embedded devices, they can be programmed / configured to achieve a specific application. I've worked with MCUs and FPGAs in the past and realized that they are ...
0
votes
2answers
56 views

percision timing ratio of multiple lights blinking with different durations and intervals

I'm learning a lot of this as I go, my background is mostly in programming. I'm trying to setup a timing circuit for two sets of lights going into a model, and am trying to determine the best way to ...
3
votes
1answer
83 views

Orientation of switching elements in PLA

In a PLA, the switching elements in the wired-OR array are oriented as shown on the right of the figure (from Fundamentals of Logic Design, Roth/Kinney, 6th Ed, p.264). A logic 1 current appears to ...
0
votes
0answers
557 views

What's the difference between PLA and PAL logic devices? Is there one?

I've seen both PAL (which I understand is Programmable Array Logic) and PLA (I don't know what this one stands for. Programmable Logic Array?) used to refer to certain types of programmable logic ...
0
votes
0answers
44 views

How to get minimum product of expression in Combinational Circuit Design (PLA)

I've been answering an assignment where the problem is design a combinational circuit design using programmable logic array (PLA) Here's the problem: F1 (A, B, C) = π(0,1,2,4) F2 (A, B, C) = π(1,...
0
votes
0answers
20 views

Voltage applying to cpld I/O pin while VCCio isn't connected

I have a pcb based around a coolrunner II cpld . My problem is as follows. An other ic generated at it's output a logic '1' (around 3.5V ) and the signal was driven to an input pin of the cpld while ...
2
votes
1answer
294 views

Logic Design simple door security system with using MUX

I draw the cicuit without using any MUX. But my project says I need to use 4x1 MUXs and I couldn't find where to use 4x1 MUXs. I tried put MUX of each output but this was very pointless, no need to ...
1
vote
1answer
140 views

Are there CPLD / FPGA toolchains and workflows that bypass vendor IDEs? [duplicate]

Custom programming for FPGA boards is a similar and helpful question for any with the same as this, but they are different. In that thread they discuss custom options and building their own. This ...
0
votes
1answer
46 views

Input impedance of input pin from Xilinx CoolRunner II CPLD

Is the effective resistance mentioned in the image the input resistance for the CPLD pins? I am using Vccio at 3.3 V. (Image is from Xilinx CPLD IO guide application note).
1
vote
1answer
54 views

Resistors for xilinx coolrunner ii cpld pcb

I am making a pcb which contains among others a coolrunner ii cpld . I will programm the CPLD through jtag from a digilent cpld development board . I read in a xilinx application note that pull-up ...
0
votes
1answer
129 views

Implementing a simple counter using VHDL

Hi I'm trying to implement a counter with external control. I'm kinda new to VHDL and I keep getting syntax error for the following code. Can someone help me understand why there's an error here? <...
0
votes
1answer
80 views

How to have an in-system check in an FPGA based system that it has been reset?

I have a system based on Altera's MAX10 device that is doing the following tasks: receives the data and stores it on an on-chip flash memory only once. reads all the data from on-chip flash, stores ...
5
votes
3answers
955 views

How do you cast an integer as a time in VHDL?

For the purposes of simplifying a test bench, I would like to set various delays by changing numerical values at the top of the file. I'd like to do something like: ...
3
votes
4answers
543 views

Can an EPROM be “refreshed” without UV erasing?

I have lots of AM27C512 65k x 8b EPROMS (with the UV window) which are quite old (1980's.) Using a Xeltek SuperPro 3000U, most can still be read and verified. A few have failed outright and were ...
3
votes
2answers
114 views

Why do ICs need a specific power down sequence?

When powering down a board, for ICs that have multiple supply voltage rails, why do they need a specific power down sequence? Typically in complex motherboards, there is a CPLD doing the job of this ...
1
vote
3answers
468 views

True 5V CPLD other than PIC/Altera ATF150*?

Are there any True 5V CPLD's families still in manufacturing other than PIC/Atmel ATF150*? I am talking not just "5V tolerant IO", but rather ones with 5V VCCIO, able to drive 5V loads without ...
0
votes
1answer
53 views

Including and extra product term on same chip in a PAL implemntaion

To implement a circuit we have a PAL requirement 4-input,4-output,(2,2,2,2) product terms.We are using a chip with 8 inputs,8 outputs(4 reg, 4non reg)(2,2,2,2,2,2,2,2). But it happened that we made a ...
0
votes
1answer
671 views

Verilog - connecting multiple bidirectional buses

I've been designing a retro computer in verilog as an exercise and so far have a simple 8-bit CPU that communicates directly with a single RAM chip via a bidirectional data port. This works great in ...
1
vote
1answer
37 views

Can I estimate what CPLD I need?

I'm planning to design a driver for VGA connectors, and for testing purposes I have an evaluation board of one CPLD. Concretely, the board is the Digilent's CoolRunner-II with the Xilinx's XC2C256 ...
1
vote
1answer
65 views

register enable line usage in `case` block (verilog synthesis for altera cpld)

I have the following in a verilog design aimed at an altera CPLD (currently targeting EPM240, although the target device isn't set in stone): ...
0
votes
2answers
148 views

7 segment display for hexadecimal numbers using PLAs

I'm trying to design 7 segment display for single digit hexadecimal numbers using PLAs but I am getting more than 16 product terms .If I implement using PROM it uses exactly 16 product terms(all min-...
2
votes
1answer
265 views

How can I program GALs on a shoestring budget?

GALs may be obsolete technology, but they're still readily available, and are dirt cheap. For a hobbyist like myself, they're ideal for small projects that need something a little faster than a low ...
1
vote
1answer
437 views

MAX10 .pof file issue, quartus II and usb blaster

After a MAX10 board revision. When programming the MAX10 with .pof, the MAX10 board do not start when power-on or after .pof programming is completed. However, normal operation is achieved when ...
0
votes
1answer
135 views

Create a low frequency oscillator with CPLD TTL input and output

I have 2 available pins on a CPLD which is a 5V TTL device (ATF750C-10PU). The inputs are just regular logic not Schmitt trigger. One pin is an output, while the other is an input. I would like to ...
0
votes
3answers
137 views

Low risk entry into CPLD/FPGA design? [closed]

I have a possible project coming up that looks like it needs a small amount of digital logic (to generate some synchronous timing/control signals). Speed is not that high, in the low megahertz. My ...
0
votes
2answers
122 views

Line remapping using a CPLD

On the product I am designing, I have an input connector of 60 lines and an output connector of 32 lines. The input can be connected to different outside products and then the lines can be mixed, so ...
0
votes
1answer
58 views

Interfacing a temperature sensor with PLD without implementing SPI/I2C bus

Are there any temperature sensors which can be interfaced with PLDs without having to implement a SPI/I2C bus at the PLD end. I am looking for something which can be interfaced without having to be ...
0
votes
1answer
193 views

FPGA and CPLD bootloader [closed]

Coming from the world of MCUs, I create bootloaders so that customers can update the firmware. Specifically, i'm talking about a USB bootloader to narrow down the many different mediums. How is this ...
11
votes
6answers
3k views

Discrete logic design

I have been tasked with building a simple alarm device. It just needs to measure a few inputs and the outputs will respond accordingly (to put it very simply!). To me, it seemed that using a few ...
0
votes
1answer
238 views

Altera Max10 altPLL slack

Regarding a MAX10 board. The whole design inside the MAX10 is clocked from a single clock using verilog's always@(posedge clockin). If connect directly a 80mhz clock to a Max10 input pin and define ...
0
votes
1answer
120 views

Need help understanding the status output generation of an ALU

I'm currently trying to implement a simple processor using Verilog in a FPGA. I'm using Mic - 1 architecture as a reference model. The thing I can't understand is the ALU is generating a "status" ...
4
votes
3answers
838 views

CPLD is (sometimes) not incrementing counter

I have this simple program running on the Altera EPM240 that’s sometimes not doing the counter increment. ...
1
vote
1answer
386 views

74LS161 in program counter circuit jumps clock cycles

I have recently been working on an 8-bit computer (Ben Eater-YouTube) and I have run into a very significant problem. My program counter seems to not work. When pulsing through a command I see that it ...
2
votes
2answers
288 views

VHDL: Demultiplexing a signal to one of many outputs while driving unused outputs to '0'

I'm attempting to create synthesisable VHDL that will demultiplex a one-bit continuous signal stream to one of many outputs. The outputs that aren't being sent this stream should be set to '0'. See ...
0
votes
1answer
185 views

Can I learn VHDL on a CPLD device?

I need to learn and practice VHDL, so I wouldlike to buy a small FPGA dev board. I've found a board based on a MAX10 circuit with the exact form factor I need, but I've read this chip is a CPLD, not a ...
5
votes
3answers
1k views

Can I use C language to program a CPLD/FPGA?

I wanted to know if I can program CPLDs /FPGAs using C language? If so, is it commonly practiced? What are the steps and the required & tools for the same?
1
vote
0answers
88 views

Verilog Code Optimisation

I have recently become involved in FPGA design and I am just testing out some new Zync SoC hardware. I have followed a tutorial online to blink some LED's however I have modified it to blink all the ...