All Questions
Tagged with programmable-logic verilog
27 questions
1
vote
1
answer
106
views
MAX3000A clock enables
I am digging into the RTL diagram created by the Quartus. I see no registers with ENA input being used. For example:
created by the following code
...
- 241
2
votes
1
answer
113
views
Is it possible to decrease timing for this circuit?
Warning. I named signal w_tristate_decoder for other reason than it being tristate. w_tristate_decoder is just a name for ths ...
- 7,152
1
vote
2
answers
3k
views
Easier way to implement a large look-up table in Verilog?
I am designing the FPGA-based control for a power-electronic AC/DC converter. This converter has five output voltage levels, so it has 8 switching instances. The levels are given by ...
- 4,458
5
votes
2
answers
762
views
How does programming FPGAs and CPLDs differ? [closed]
I am learning to program programmable devices using a XC9572XL CPLD. I would like to know how much knowledge from programming CPLDs (in Verilog, VHDL) will be transferable to programming FPGAs (not ...
- 8,935
0
votes
1
answer
557
views
Are Verilog always blocks synthesized so that the sensitivity list items are settled by the time the block behavior is carried out?
In other words, if signal goes high and triggers the always block, will the block be synthesized in a way that the behavior in ...
- 178k
0
votes
1
answer
177
views
How to have an in-system check in an FPGA based system that it has been reset?
I have a system based on Altera's MAX10 device that is doing the following tasks:
receives the data and stores it on an on-chip flash memory only once.
reads all the data from on-chip flash, stores ...
- 1,077
3
votes
1
answer
3k
views
Verilog - connecting multiple bidirectional buses
I've been designing a retro computer in verilog as an exercise and so far have a simple 8-bit CPU that communicates directly with a single RAM chip via a bidirectional data port. This works great in ...
- 14.6k
1
vote
1
answer
121
views
register enable line usage in `case` block (verilog synthesis for altera cpld)
I have the following in a verilog design aimed at an altera CPLD (currently targeting EPM240, although the target device isn't set in stone):
...
CommunityBot
- 1
0
votes
1
answer
753
views
Altera Max10 altPLL slack
Regarding a MAX10 board. The whole design inside the MAX10 is clocked from a single clock using verilog's always@(posedge clockin).
If connect directly a 80mhz clock to a Max10 input pin and define ...
- 67
4
votes
3
answers
2k
views
CPLD is (sometimes) not incrementing counter
I have this simple program running on the Altera EPM240 that’s sometimes not doing the counter increment.
...
- 1,693
0
votes
1
answer
347
views
Need help understanding the status output generation of an ALU
I'm currently trying to implement a simple processor using Verilog in a FPGA. I'm using Mic - 1 architecture as a reference model.
The thing I can't understand is the ALU is generating a "status" ...
- 3,774
2
votes
0
answers
266
views
Verilog Code Optimisation
I have recently become involved in FPGA design and I am just testing out some new Zync SoC hardware. I have followed a tutorial online to blink some LED's however I have modified it to blink all the ...
- 115
1
vote
1
answer
2k
views
Active low vs active High reset in CPLD
I am using Xilinx's CoolRunner-II series CPLD, and programming programmable logic for the first time.
I have to use few of flip-flops with asynchronous reset.
I wonder what is the difference between ...
- 8,935
0
votes
1
answer
2k
views
Verilog Ring Oscillator problem
I am trying to make a ring oscillator inside of a Xilinx's CoolRunner-II CPLD and trying to measure how many ring-oscillator cycle fits inside a low half of external 10MHz clock. Below is simple code ...
- 70.7k
13
votes
5
answers
8k
views
What would make me choose Verilog or VHDL over schematic design on CPLDs or FPGAs?
I have absolutely no background in programmable logic, I use mostly microcontrollers in my projects but recently I needed to work with video and the microcontroller is just too slow for what I needed ...
- 1,010
0
votes
1
answer
313
views
How is the signal assigned to a pin by default
Here's the simple verilog code that contains WR_n signal. This signal (net) is not explicitly assigned to a LOC (pin) in the .ucf file. The design implements without any errors. I would assume that ...
- 96
6
votes
2
answers
1k
views
Trouble with VGA Controller on CPLD
What I am attempting to do is create a VGA controller from a Lattice MachXO CPLD in Verilog.
The Problem
I am attempting to display the color red with a resolution of 640x480 @ 60Hz using a 25.175 ...
- 3,977
3
votes
2
answers
1k
views
Arduino to CPLD to toggle an LEDs using I2C
I have a a CPLD (Lattice MachXO2) that echos a signal from an Arduino to turn on an LED.
Arduino:
...
- 3,977
1
vote
1
answer
196
views
4 port 12 bit mux is consuming 48 macrocells!
I'm programming on the coolrunner II cpld. It is running out of resources so I decided to implement my own 4 port, 12 bit mux. After implementation I find that it's using over 40 macrocells. Any way ...
- 10.1k
-2
votes
1
answer
43
views
What's the order of the array generated by Verilog? Syntax
What is the correct interpretation between these two lines:
wire[2:0] w = SW[17:15] = {SW[17], SW[16], SW[15]}
wire[2:0] w = SW[17:15] = {SW[15], SW[16], SW[17]}
When I call w[0] will I get SW[15] ...
- 178k
1
vote
0
answers
541
views
problem with CPLD and 24C16 EEPROM interface
Can any one say if it is possible to implement this code in ATMEL 24C16 EEPROM device for write the data. While I am implementing this with CPLD xc9572 I/O Pin declared as sda, scl there won't have ...
- 1,379
6
votes
1
answer
6k
views
Free linting tool for Verilog
Is there an opensource linting tool for Verilog. I've seen HDL companion and other but they all come with a price tag.
- 343
3
votes
2
answers
10k
views
Parameterized net width in Verilog
Is something like this possible ?
parameter width;
wire[width-1] a_net = (width)'b0;
I basically need a variable to control the width of the right hand side. I ...
- 3,042
-3
votes
2
answers
2k
views
Learn CPLD from zero [closed]
a) Should I learn VHDL or Verilog? Is one excel in some area while the other better fit another area?
For simple "glue logic", says, 5 to 30 TTL chips equivalant, which is better?
b) First ...
CommunityBot
- 1
8
votes
2
answers
2k
views
Why does this Verilog hog down 30 macrocells and hundreds of product terms?
I have a project that's consuming 34 of a Xilinx Coolrunner II's macrocells. I noticed I had an error and tracked it down to this:
...
- 946
1
vote
1
answer
177
views
Why does changing an 'add' to a logical or devour 7 CPLD macrocells?
I have a design that's synthesizing to about 50 macrocells.
I have this section of code:
...
- 55.5k
4
votes
1
answer
397
views
Verilog - A line stays high, I need it to go low after a while
I'm working on a circuit in Verilog to be implemented on a CPLD. The output of the circuit will drive a stepper motor. The input is a stream of pulses from a machine.
I generate a stepper pulse ...
- 946