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Trying to minimize product terms for GAL16V8

I am building an accessory for a 6502-based computer, and am trying to stick with (reasonably) period-era components. To this end I am using a GAL16v8 (specifically an ATF16V8C) to handle register ...
reekanmantell's user avatar
3 votes
1 answer
430 views

Why do PALs have higher speed than PLAs?

When considering speed I have learned that PLAs are much slower than PALs. As each signal has to propagate through same sequence of gates (in series) why there is a speed difference?
sandun herath's user avatar
0 votes
1 answer
68 views

Defining arbitrary length bit-string literals for constant std_ulogic_vector in VHDL

I want to be able to define a simple constant for DEFAULT_BUS as all Z, or some other std_ulogic value, but its length should depend upon another generic value as per instantiation and it'd be nice to ...
David H Parry's user avatar
0 votes
1 answer
212 views

How to combine two, separate 4 bit words into a 6 bit one?

How to combine two, 4-bit words into one 6-bit word. What I want to achieve: Using a matrix keyboard, I would like to control six addresses (A0-A5) of a parallel EEPROM memory in the range from 000000 ...
Jerzy Przezdziecki's user avatar
0 votes
0 answers
94 views

What logic function performs this IEEE Standard 91-1984 symbol?

I'm thinking about copying network interface card for an old HP9000/300 series computer. These cards are insanely expensive on ebay these days (around 200USD), and i think that i could make one for ...
woytekm's user avatar
  • 101
13 votes
4 answers
3k views

Accurate quadrature decoding without external clocking

An Incremental Encoder is a linear or rotary electromechanical device that has two output signals, A and B, which issue pulses ...
Pavel Stepanek's user avatar
0 votes
1 answer
563 views

What is the maximum number of inputs to a logic gate that is being used in computing hardware these days?

I was referring to this question, but I had a confusion due to the concept of programmable logic devices. Image from UW page 7. Here the OR section can have up to 8 inputs to it. I'm confused about ...
lousycoder's user avatar
2 votes
1 answer
73 views

200 Input Smart Multimeter Project

First off, thanks for taking the time to read this and help out. Here's a quick overview of what I am trying to design. I have a break out box that has 200 female probe inputs. Each input is numbered, ...
bmilesyo's user avatar
-1 votes
1 answer
114 views

What is the relation of memory and PLD to (synchronous) sequential circuits?

In Mona's Digital Design book, Chapter 5 outlines the formal procedures for analyzing and designing clocked (syn- chronous) sequential circuits. The gate structure of several types of flip‐flops ...
Tim's user avatar
  • 359
1 vote
3 answers
423 views

How much current can a MAX II I/O pin safely sink? 16 or 55mA?

This question is quite similar to this one. As far as I understood, an I/O pin configured as LVTTL output can be programmed to source/sink up to 16mA. This is what the MAX II handbook says in Table 2....
ris8_allo_zen0's user avatar
0 votes
1 answer
327 views

Checking the color of the pixel in VHDL

I'm trying to switch the colors of a 4-bitmap image using VHDL . In a 4 bit-image . Which means we have these types of colors . ...
James's user avatar
  • 15
0 votes
1 answer
221 views

Question On Logic Gates

In a small railway station, there are three platforms, #1, #2, #3. Up and down trains can enter in platform number #2 and #3, but platform #1 is only devoted to up trains. Design a logic circuit using ...
user255006's user avatar
0 votes
3 answers
586 views

On-the-fly routing of digital and analog signals using unbuffered analog crosspoint arrays?

The issue I have is strongly related to a question which was asked over here. Unfortunately I did not find the answer I was looking for. Digging a bit more I've came across a class of IC's named ...
Paun Alin's user avatar
0 votes
2 answers
74 views

percision timing ratio of multiple lights blinking with different durations and intervals

I'm learning a lot of this as I go, my background is mostly in programming. I'm trying to setup a timing circuit for two sets of lights going into a model, and am trying to determine the best way to ...
CyF's user avatar
  • 51
0 votes
0 answers
926 views

What's the difference between PLA and PAL logic devices? Is there one?

I've seen both PAL (which I understand is Programmable Array Logic) and PLA (I don't know what this one stands for. Programmable Logic Array?) used to refer to certain types of programmable logic ...
Hearth's user avatar
  • 38.5k
2 votes
1 answer
2k views

Logic Design simple door security system with using MUX

I draw the cicuit without using any MUX. But my project says I need to use 4x1 MUXs and I couldn't find where to use 4x1 MUXs. I tried put MUX of each output but this was very pointless, no need to ...
Proton956185's user avatar
0 votes
1 answer
77 views

Including and extra product term on same chip in a PAL implemntaion

To implement a circuit we have a PAL requirement 4-input,4-output,(2,2,2,2) product terms.We are using a chip with 8 inputs,8 outputs(4 reg, 4non reg)(2,2,2,2,2,2,2,2). But it happened that we made a ...
Siddharth's user avatar
0 votes
2 answers
1k views

7 segment display for hexadecimal numbers using PLAs

I'm trying to design 7 segment display for single digit hexadecimal numbers using PLAs but I am getting more than 16 product terms .If I implement using PROM it uses exactly 16 product terms(all min-...
Siddharth's user avatar
0 votes
1 answer
394 views

Create a low frequency oscillator with CPLD TTL input and output

I have 2 available pins on a CPLD which is a 5V TTL device (ATF750C-10PU). The inputs are just regular logic not Schmitt trigger. One pin is an output, while the other is an input. I would like to ...
Robotbugs's user avatar
  • 415
1 vote
1 answer
892 views

74LS161 in program counter circuit jumps clock cycles

I have recently been working on an 8-bit computer (Ben Eater-YouTube) and I have run into a very significant problem. My program counter seems to not work. When pulsing through a command I see that it ...
techsupport's user avatar
1 vote
2 answers
1k views

8 to 3 Priority Encoder. Answer Verification [closed]

I am trying to design a priority encoder with a given priority table. Input: I0 I1 I2 I3 I4 I5 I6 I7 Priority: 2 7 6 1 5 0 3 4 Image attached!! Are these correct? Or I am failing?
Gabriel Valedon's user avatar
4 votes
4 answers
1k views

What is the modern way to do small scale programmable logic?

I am designing a circuit for an electronic coil winder. It has a few binary counters, equality detectors, 7 segment decoders and flip flops. How it is possible to get all of this logic onto 1 ...
John Spence's user avatar
-2 votes
1 answer
162 views

XC9536XL CPLD socket [closed]

I'm planning on using this CPLD: XC9536XL-5VQG44C. I only have one question when I used the chip in the lab the chip was mounted on top of some type of socket or base and that socket was connect to ...
MrAbdul's user avatar
0 votes
4 answers
528 views

How to check if sync signal is inverted?

in input of a CPLD, I have a syncronization video signal that can be like this (positive polarity): or like this (negative polarity): I want to recognize the type of the sync signal and invert the ...
Alessio's user avatar
1 vote
3 answers
1k views

What exactly does a 10-transistor XOR gate look like?

I need a schematic for a 10-transistor xor gate, I have searched everywhere and I see 8, 12, 6, but I can't see 10. What does it look like in a transistor like picture?
user124627's user avatar
3 votes
2 answers
10k views

Parameterized net width in Verilog

Is something like this possible ? parameter width; wire[width-1] a_net = (width)'b0; I basically need a variable to control the width of the right hand side. I ...
Blackadder's user avatar
0 votes
1 answer
110 views

what are the things to keep in mind when interfacing two digital devices?

what are the things to keep in mind when interfacing two digital devices, e.g FPGA with a dual shock controller or CPLD with a PS/2 Mouse, Microcontroller with an FPGA, FPGA with an external RAM. One ...
quantum231's user avatar
  • 12.2k
5 votes
3 answers
4k views

Is this a good use of a CPLD?

I am trying to generate some waveforms which are phase shifted from an input signal. The input signal is around 4.4 MHz and is a square wave at 50% duty. I need a 0 degree and 90 degree phase shift ...
Thomas O's user avatar
  • 32.2k
9 votes
4 answers
53k views

What is the difference between PLA and ROM?

I'm finding it hard to understand. What is the difference between PLA and ROM? Can somebody please provide a link or explanation?
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