Questions tagged [programmable-logic]
Programmable digital logic devices include FPGAs, CPLDs, and older devices such as GALs and PALs. Programmable logic enables flexibly implementing complex digital functions in a single chip, from a few gates of glue logic to entire microprocessors or complex signal processing systems.
244 questions
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5V input tolerance on ATF16LV8
The features clause in the datasheet (https://www.microchip.com/en-us/product/atf16lv8c) specifically mentions "Inputs are 5V Tolerant",
but the DC characteristics specify VIH to be MAX Vcc+...
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Trying to minimize product terms for GAL16V8
I am building an accessory for a 6502-based computer, and am trying to stick with (reasonably) period-era components. To this end I am using a GAL16v8 (specifically an ATF16V8C) to handle register ...
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Why do PALs have higher speed than PLAs?
When considering speed I have learned that PLAs are much slower than PALs. As each signal has to propagate through same sequence of gates (in series) why there is a speed difference?
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How to fix erased On-Board Usb-Blaster FPGA (MAX II EPM240T100C3 on board Terasic DE10-Lite)
I have Terasic DE10-Lite board (with Altera MAX10 fpga), which use Altera Max II EPM240T100C3N (and usb-b + ftdi chip) for on-board usb-blaster logic. After explore 8 pins jtag holes on the board, i ...
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How to flash Altera EPM7256E?
I am working on legacy bit of hardware. I see that EPM7256S can be flashed as usual, via JTAG using standard (modern) tools, so this is quite clear.
But how to flash EPM7256E? Are the any inexpensive ...
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Defining arbitrary length bit-string literals for constant std_ulogic_vector in VHDL
I want to be able to define a simple constant for DEFAULT_BUS as all Z, or some other std_ulogic value, but its length should depend upon another generic value as per instantiation and it'd be nice to ...
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Having a Counter issue on a PLD, programmed from NI MultiSim
In a PLD build:
I have built a counter that counts 0-9 combined to a second counter that counts to 8, to create a counter that counts up to 80. It has a reset and hold (@80) function as well. I have ...
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What is the algorithm to read fusemap from PAL IC?
I am aware that it's not always possible due to security fuse, but I would like to at least try to read the fusemap from a certain PAL16R6 chip. I would like to do it using MCU like Arduino, not a ...
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How to combine two, separate 4 bit words into a 6 bit one?
How to combine two, 4-bit words into one 6-bit word.
What I want to achieve: Using a matrix keyboard, I would like to control six addresses (A0-A5) of a parallel EEPROM memory in the range from 000000 ...
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Composite video with 8-bit DAC
recently my eyes got caught by this YouTube video
It shows how ESP32 can draw analog composite video using I2S -> DMA -> DAC.
I considered using this concept in my project but it has a little ...
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How to estimate GreenPAK speed limits?
I am considering using a SLG46826 GreenPAK PLD for a simple digital design running at 40 MHz. Basically output a 40 MHz external clock and generate a properly synchronized pulse now and then. In the ...
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What logic function performs this IEEE Standard 91-1984 symbol?
I'm thinking about copying network interface card for an old HP9000/300 series computer. These cards are insanely expensive on ebay these days (around 200USD), and i think that i could make one for ...
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How can I improve my ladder logic diagram of a vending machine?
I am trying to create a coffee and tea machine using a ladder logic diagram. There are small, medium, and large sizes. This is where I am now:
Can you give me any ideas or corrections on how to ...
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Lowering VCE(sat) for analog transistor switch
I've been wanting to build a primitive programmable logic device using mainly bipolar transistors.
One of the defining characteristics of a PLD is the ability to select what inputs get passed through ...
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Atmel Micro-controller on a Xilinx CPLD board
This question is related to the CoolRunner-II Starter Board that was used to be offered from Digilent. See here for schematic. See here for the reference manual. Here is the block diagram for the CPLD ...
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What is this chip? Is it re-programmable? [duplicate]
I found this chip inside my kid's walker. Seems like it stores the pre-installed audios of children's rhymes. It's connected to several LEDs, a mono speaker and two button pcbs. I wanna replace the ...
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Understanding OLD PEEL173 code
I have some code for a PEEL173 form the early 90's. I would like to understand the logic of this code, but I don't recognize this syntax.
Question 1: Do you recognize the syntax of this language? What ...
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MAX3000A clock enables
I am digging into the RTL diagram created by the Quartus. I see no registers with ENA input being used. For example:
created by the following code
...
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Is it possible to decrease timing for this circuit?
Warning. I named signal w_tristate_decoder for other reason than it being tristate. w_tristate_decoder is just a name for ths ...
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Pros and cons connecting R2R directly to FPGA/CPLD
I am designing the R2R-based DAC circuit (5 bits per channel) for the video output @ 25.17 MHz. Looking for advice to ensure I didn't overlook something very important.
Initial design was CPLD -> ...
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Can I use PICkit 3 to program an ATF16V8CZ?
Is possible to program an ATF16V8CZ chip using a PICkit 3 programmer?
In the pin description of the datasheet I can't find the conections to the programmer or the MCLR pin.
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Can a digital system be considered an ASIC regardless its physical implementation?
From my knowledge from classical books of computational and digital systems, an ASIC is a category of full-customized or semi-customized integrated circuit (IC) tailored to a specific application.
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Use cases for RAM-less microcontrollers
In a different question around a specific microcontroller (ATtiny12 - datasheet) I came to ask myself: What are the intended use cases for such devices?
Does it target the segment: Too "complex&...
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Problem in programming ALTERA MAX 7000S CPLD with homemade Byte Blaster
I am trying to read back an ALTERA MAX 7000S CPLD (EPM7064SLC84-10) mounted on a board (a part of the board's schematic is shown below) and copy it on another CPLD.
In the schematic, X4 is a male 10 ...
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Can I/O pins on a PLD (e.g. ATF16V8B) be configured to act as an open-drain output that is usable in a wired-OR circuit?
I designed a peripheral card for an 8-bit home computer which uses an ATF16V8B for address decoding and glue logic.
I want this card to be able to generate interrupt requests by driving the system's /...
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Accurate quadrature decoding without external clocking
An Incremental Encoder is a linear or rotary electromechanical device that has two output signals, A and B, which issue pulses ...
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Top-level HDL File with Libero SOC
I'm using Libero SOC for the first time. I've used Quartus and Vivado before. I notice in the tutorials ways to use the graphical "Smart Design" file type as a top level module. But I can't ...
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Do any FPGAs that set undefined values in registers after power up exist?
There is some discussions how to set default values or start an initial sequence in FPGAs design after programming/power-up.
The most reliable method is using a supervisor IC which guaranteed send ...
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JTagging an Atmel ATF1500 CPLD
Intentions
I'm learning how to use CPLDs and I thought a good one to start with is the Atmel ATF1500AL-TQFP44.
Whats the deal
The datasheet provides no information about programming the CPLD; also, ...
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CPLD Programming via Microcontroller
I am new to CPLD's and I have a CPLD connected to the microcontroller via JTAG. Xilinx has an application note (XAPP058) about programming but I could not understand very well. Steps that I understand:...
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Is this two-tone oscillator a smart design?
I am fiddling a bit with building some kind of programmable sound generator using simple components. I got something more or less working now as a proof of concept:
Here, the 555 is wired as an ...
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How can I implement selectable VCC and ground
I want to make a retro computer around a 6809E and a CPLD. It occurs to me that the physical layout/design of this board would be nearly identical for all the 40 pin, 8 bit CPUs except for power and ...
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What is the maximum number of inputs to a logic gate that is being used in computing hardware these days?
I was referring to this question, but I had a confusion due to the concept of programmable logic devices. Image from UW page 7. Here the OR section can have up to 8 inputs to it. I'm confused about ...
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PLC programming
In the figure below it says if the contact used is NC, then program it in the PLC as NO. Why?
Also, the diagram on the left for example the stop pushbutton which is connected to IN 1, is a NC switch ...
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Writing an assembler for Lattice GAL devices
I am writing a compiler for the Lattice GAL10V8 and GAL16V8 PLDs. (And, yes I know that these chips are now obsolete.)
I have completed the compiler as far as parsing the logic equations and pin ...
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Working on a legacy system that requires a full DMA controller (external DRQ/DACK mechanism) CPLD or FPGA vs Microcontroller
I'm working on a system that involves a legacy ASIC that requires a DMA controller. My current implementation is based on the STM32, but as you might know, the STM32 doesn't provide external DRQ/DACK ...
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Can I programming a CPLD in low-level?
Maybe it's a silly question, but I want to use a microcontroller with a CPLD.
My idea is for the microcontroller to reprogram the CPLD as many times as the user wants.
The problem is that I don't want ...
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GAL 16v8 tri-state independent pin control
I would like to use GAL chips for a project.
16V8, 22V10, 26V12.
I have read that the tri-state status of a pin maybe controlled individually.
I do not understand how write the equations to ...
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New design with XC9500XL CPLDs, is it already obsolete?
I am in the middle of a new design for which a relatively small amount of logic is needed. This is a change to a previous version in which discrete 3.3V logic parts were used. We decided to go a CPLD ...
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200 Input Smart Multimeter Project
First off, thanks for taking the time to read this and help out.
Here's a quick overview of what I am trying to design. I have a break out box that has 200 female probe inputs. Each input is numbered, ...
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Should I get a response when beeping two GND pins on a CPLD?
I have an Altera CPLD, 5M570ZT100I5N (100 pins, Quad-Flat-Package) mounted in a socket adapter to get access to the pins. I try to beep two GND pins on the same edge of the package, but get no ...
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Altera Quartus detects 2 CPLD devices instead of 1
I try to program a design I made using 5M40ZE64C5N CPLD. The software side was successful and I got a .pof file without any critical warnings or errors. The problem occurs when I try to upload the ...
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16V8 PLD alternatives for fast clock-to-data turnaround time
Context: I'm prototyping an MIPI I3C Basic slave device implemented on a PSOC5LP. (I3C is similar to I2C, but is spec'd to run at up to 12.9 MHz.) Due to a speed limitation of the PSOC, I'm ...
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Easier way to implement a large look-up table in Verilog?
I am designing the FPGA-based control for a power-electronic AC/DC converter. This converter has five output voltage levels, so it has 8 switching instances. The levels are given by ...
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3 digit BCD Counter in VHDL and Quartus II
I'm trying to make a 3 digits BCD counter in VHDL for Cyclone V FPGA from intel. I have an module-k counter design and I instantiate four counters in top level module (structural design):
One counter ...
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Have I burnt my MAX II by excessive soldering?
I soldered my first TQFP 100 package, an Altera MAX II EPM570 CPLD, on a PCB.
But I only found the "correct" way to solder (put flux on the pads and on the pins, melt some tin on a thin iron ...
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What is the relation of memory and PLD to (synchronous) sequential circuits?
In Mona's Digital Design book,
Chapter 5 outlines the formal procedures for analyzing and designing clocked (syn-
chronous) sequential circuits. The gate structure of several types of flip‐flops ...
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What is the difference between these two ladder logic diagrams?
First ladder logic diagram:
Second ladder logic diagram:
I am trying to implement a toggle switch. On the rising edge of "Change", it should toggle "ToggleThis".
I thought the ...
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Which pins belong in a "I/O region" on a MAX II CPLD?
I want to use an Altera/Intel MAX II device (EPM570) to drive 20 LEDs. They all have 20mA forward voltage, for a worst-case current draw of 400mA.
The application note AN 286 explains how an Altera/...
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How much current can a MAX II I/O pin safely sink? 16 or 55mA?
This question is quite similar to this one.
As far as I understood, an I/O pin configured as LVTTL output can be programmed to source/sink up to 16mA. This is what the MAX II handbook says in Table 2....
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