Questions tagged [programmable-logic]
Programmable digital logic devices include FPGAs, CPLDs, and older devices such as GALs and PALs. Programmable logic enables flexibly implementing complex digital functions in a single chip, from a few gates of glue logic to entire microprocessors or complex signal processing systems.
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JTagging an Atmel ATF1500 CPLD
Intentions
I'm learning how to use CPLDs and I thought a good one to start with is the Atmel ATF1500AL-TQFP44.
Whats the deal
The datasheet provides no information about programming the CPLD; also, ...
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200 Input Smart Multimeter Project
First off, thanks for taking the time to read this and help out.
Here's a quick overview of what I am trying to design. I have a break out box that has 200 female probe inputs. Each input is numbered, ...
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Macrocell and Function Block optimization ISE XILINX
I get the following result when I compile my code in ISE. It says the CPLD is full, but I can't help but notice that the optimizer should be able to move elements from different function blocks to ...
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Having a Counter issue on a PLD, programmed from NI MultiSim
In a PLD build:
I have built a counter that counts 0-9 combined to a second counter that counts to 8, to create a counter that counts up to 80. It has a reset and hold (@80) function as well. I have ...
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Lowering VCE(sat) for analog transistor switch
I've been wanting to build a primitive programmable logic device using mainly bipolar transistors.
One of the defining characteristics of a PLD is the ability to select what inputs get passed through ...
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5-V CPLD family in-circuit programmability
I have a need for a relatively small amount of 5V-logic (active at power-up) that would perfectly fit a package like that of the ATF750CL CPLD from Atmel/Microchip, the DigiKey page for these devices ...
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How do I feed a digital value to the PIC CLC system?
I'm playing with a nice new PIC16F15356, and investigating the Configurable Logic Cell (CLC) capabilities - basically a 4-cell mini-PLD on the chip that can take inputs from any of a list of 40 ...
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Verilog Code Optimisation
I have recently become involved in FPGA design and I am just testing out some new Zync SoC hardware. I have followed a tutorial online to blink some LED's however I have modified it to blink all the ...
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CPLD ispmach 4256ze starter pin connention configuration
I am an undergraduate student that working on a project which need to use an ispMACH 4256ZE CPLD to implement some data transfer function in my circuit.
Need someone whoever have worked with CPLD to ...
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problem with CPLD and 24C16 EEPROM interface
Can any one say if it is possible to implement this code in ATMEL 24C16 EEPROM device for write the data. While I am implementing this with CPLD xc9572 I/O Pin declared as sda, scl there won't have ...
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Defining arbitrary length bit-string literals for constant std_ulogic_vector in VHDL
I want to be able to define a simple constant for DEFAULT_BUS as all Z, or some other std_ulogic value, but its length should depend upon another generic value as per instantiation and it'd be nice to ...
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How to estimate GreenPAK speed limits?
I am considering using a SLG46826 GreenPAK PLD for a simple digital design running at 40 MHz. Basically output a 40 MHz external clock and generate a properly synchronized pulse now and then. In the ...
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What logic function performs this IEEE Standard 91-1984 symbol?
I'm thinking about copying network interface card for an old HP9000/300 series computer. These cards are insanely expensive on ebay these days (around 200USD), and i think that i could make one for ...
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How can I improve my ladder logic diagram of a vending machine?
I am trying to create a coffee and tea machine using a ladder logic diagram. There are small, medium, and large sizes. This is where I am now:
Can you give me any ideas or corrections on how to ...
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Understanding OLD PEEL173 code
I have some code for a PEEL173 form the early 90's. I would like to understand the logic of this code, but I don't recognize this syntax.
Question 1: Do you recognize the syntax of this language? What ...
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Pros and cons connecting R2R directly to FPGA/CPLD
I am designing the R2R-based DAC circuit (5 bits per channel) for the video output @ 25.17 MHz. Looking for advice to ensure I didn't overlook something very important.
Initial design was CPLD -> ...
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Can I use PICkit 3 to program an ATF16V8CZ?
Is possible to program an ATF16V8CZ chip using a PICkit 3 programmer?
In the pin description of the datasheet I can't find the conections to the programmer or the MCLR pin.
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Do any FPGAs that set undefined values in registers after power up exist?
There is some discussions how to set default values or start an initial sequence in FPGAs design after programming/power-up.
The most reliable method is using a supervisor IC which guaranteed send ...
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Writing an assembler for Lattice GAL devices
I am writing a compiler for the Lattice GAL10V8 and GAL16V8 PLDs. (And, yes I know that these chips are now obsolete.)
I have completed the compiler as far as parsing the logic equations and pin ...
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Working on a legacy system that requires a full DMA controller (external DRQ/DACK mechanism) CPLD or FPGA vs Microcontroller
I'm working on a system that involves a legacy ASIC that requires a DMA controller. My current implementation is based on the STM32, but as you might know, the STM32 doesn't provide external DRQ/DACK ...
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Which pins belong in a "I/O region" on a MAX II CPLD?
I want to use an Altera/Intel MAX II device (EPM570) to drive 20 LEDs. They all have 20mA forward voltage, for a worst-case current draw of 400mA.
The application note AN 286 explains how an Altera/...
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Programmable delay line IC
I'm currently redesigning a delay line circuit. It is implemented on a Xilinx CPLD IC. Minimum delay is about 200 ns and maximum 600 µs, which is enough range for my project. What I want to do is ...
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Why a CPLD input pin behaves almost like an output pin?
I want my CPLD (a MAX II CPLD, EPM240, see datasheet) to accept an S/PDIF input using an optical receiver with TTL-compatible output.
I tested the receiver alone: when giving proper power and optical ...
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What's the difference between PLA and PAL logic devices? Is there one?
I've seen both PAL (which I understand is Programmable Array Logic) and PLA (I don't know what this one stands for. Programmable Logic Array?) used to refer to certain types of programmable logic ...
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How do I generate a .JED file for programming an ATF750C using VHDL language?
I know how to program regular PAL/GAL22V10 chips and I am interested in using the enhanced Atmel ATF750C CPLD device because it seems 100% pin- and voltage-compatible with the PAL/GAL22V10 chips. I ...
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