Questions tagged [programmable-logic]

Programmable digital logic devices include FPGAs, CPLDs, and older devices such as GALs and PALs. Programmable logic enables flexibly implementing complex digital functions in a single chip, from a few gates of glue logic to entire microprocessors or complex signal processing systems.

Filter by
Sorted by
Tagged with
0 votes
1 answer
63 views

CPLD Programming via Microcontroller

I am new to CPLD's and I have a CPLD connected to the microcontroller via JTAG. Xilinx has an application note (XAPP058) about programming but I could not understand very well. Steps that I understand:...
user avatar
1 vote
0 answers
54 views

How do I make my MAX II CPLD stable after disconnecting it from USB ByteBlaster and PC?

I just designed and programmed firmware into my CPLD which has a state machine for a project. It works fine when connected to the USB ByteBlaster and PC. However, when I disconnect the ByteBlaster, ...
user avatar
  • 11
0 votes
3 answers
85 views

Is this two-tone oscillator a smart design?

I am fiddling a bit with building some kind of programmable sound generator using simple components. I got something more or less working now as a proof of concept: Here, the 555 is wired as an ...
user avatar
0 votes
0 answers
13 views

ICE5LP4K-SG48ITR Flash programming Issue

I am using the Lattice CPLD: ICE5LP4K-SG48ITR in my module.For that I have an SPI flash (W25Q256JVEIQ) for device programming.I can able to program SPI Flash and CPLD externally using HW-USBN-2B.But ...
user avatar
0 votes
3 answers
77 views

How can I implement selectable VCC and ground

I want to make a retro computer around a 6809E and a CPLD. It occurs to me that the physical layout/design of this board would be nearly identical for all the 40 pin, 8 bit CPUs except for power and ...
user avatar
0 votes
1 answer
105 views

What is the maximum number of inputs to a logic gate that is being used in computing hardware these days?

I was referring to this question, but I had a confusion due to the concept of programmable logic devices. Image from UW page 7. Here the OR section can have up to 8 inputs to it. I'm confused about ...
user avatar
0 votes
2 answers
88 views

PLC programming

In the figure below it says if the contact used is NC, then program it in the PLC as NO. Why? Also, the diagram on the left for example the stop pushbutton which is connected to IN 1, is a NC switch ...
user avatar
  • 817
0 votes
0 answers
25 views

How to connect a system on module to my customized carrier board

I want to use MYC-Y7Z010/20 CPU Module from MYIR company (http://www.myirtech.com/download/Zynq7000/MYC-Y7Z010_20.pdf), the carrier board for this module consists of interfaces I don't need, including ...
user avatar
  • 89
0 votes
0 answers
76 views

Writing an assembler for Lattice GAL devices

I am writing a compiler for the Lattice GAL10V8 and GAL16V8 PLDs. (And, yes I know that these chips are now obsolete.) I have completed the compiler as far as parsing the logic equations and pin ...
user avatar
0 votes
0 answers
58 views

Working on a legacy system that requires a full DMA controller (external DRQ/DACK mechanism) CPLD or FPGA vs Microcontroller

I'm working on a system that involves a legacy ASIC that requires a DMA controller. My current implementation is based on the STM32, but as you might know, the STM32 doesn't provide external DRQ/DACK ...
user avatar
1 vote
1 answer
106 views

Can I programming a CPLD in low-level?

Maybe it's a silly question, but I want to use a microcontroller with a CPLD. My idea is for the microcontroller to reprogram the CPLD as many times as the user wants. The problem is that I don't want ...
user avatar
1 vote
2 answers
254 views

GAL 16v8 tri-state independent pin control

I would like to use GAL chips for a project. 16V8, 22V10, 26V12. I have read that the tri-state status of a pin maybe controlled individually. I do not understand how write the equations to ...
user avatar
2 votes
1 answer
519 views

New design with XC9500XL CPLDs, is it already obsolete?

I am in the middle of a new design for which a relatively small amount of logic is needed. This is a change to a previous version in which discrete 3.3V logic parts were used. We decided to go a CPLD ...
user avatar
  • 8,165
2 votes
0 answers
49 views

200 Input Smart Multimeter Project

First off, thanks for taking the time to read this and help out. Here's a quick overview of what I am trying to design. I have a break out box that has 200 female probe inputs. Each input is numbered, ...
user avatar
0 votes
0 answers
153 views

Arithmetic - Absolute value

I constructed a circuit that calculates the absolute value of a signed 4-bit number in two's complement Then the second question of the exercise was to show the correctness of my circuit using the ...
user avatar
  • 227
0 votes
2 answers
61 views

Should I get a response when beeping two GND pins on a CPLD?

I have an Altera CPLD, 5M570ZT100I5N (100 pins, Quad-Flat-Package) mounted in a socket adapter to get access to the pins. I try to beep two GND pins on the same edge of the package, but get no ...
user avatar
  • 125
1 vote
2 answers
258 views

Altera Quartus detects 2 CPLD devices instead of 1

I try to program a design I made using 5M40ZE64C5N CPLD. The software side was successful and I got a .pof file without any critical warnings or errors. The problem occurs when I try to upload the ...
user avatar
0 votes
1 answer
106 views

16V8 PLD alternatives for fast clock-to-data turnaround time

Context: I'm prototyping an MIPI I3C Basic slave device implemented on a PSOC5LP. (I3C is similar to I2C, but is spec'd to run at up to 12.9 MHz.) Due to a speed limitation of the PSOC, I'm ...
user avatar
0 votes
0 answers
176 views

How to write a linear interpolator in VHDL?

I have to create a linear interpolator in VHDL.My interpolator has to take 2 known values and using a factory level of 2 in interpolation return the interpolated value.Our signal is campionated with a ...
user avatar
1 vote
2 answers
924 views

Easier way to implement a large look-up table in Verilog?

I am designing the FPGA-based control for a power-electronic AC/DC converter. This converter has five output voltage levels, so it has 8 switching instances. The levels are given by ...
user avatar
2 votes
1 answer
1k views

3 digit BCD Counter in VHDL and Quartus II

I'm trying to make a 3 digits BCD counter in VHDL for Cyclone V FPGA from intel. I have an module-k counter design and I instantiate four counters in top level module (structural design): One counter ...
user avatar
0 votes
2 answers
168 views

Have I burnt my MAX II by excessive soldering?

I soldered my first TQFP 100 package, an Altera MAX II EPM570 CPLD, on a PCB. But I only found the "correct" way to solder (put flux on the pads and on the pins, melt some tin on a thin iron ...
user avatar
-1 votes
1 answer
86 views

What is the relation of memory and PLD to (synchronous) sequential circuits?

In Mona's Digital Design book, Chapter 5 outlines the formal procedures for analyzing and designing clocked (syn- chronous) sequential circuits. The gate structure of several types of flip‐flops ...
user avatar
  • 349
1 vote
1 answer
97 views

What is the difference between these two ladder logic diagrams?

First ladder logic diagram: Second ladder logic diagram: I am trying to implement a toggle switch. On the rising edge of "Change", it should toggle "ToggleThis". I thought the ...
user avatar
0 votes
1 answer
54 views

Which pins belong in a "I/O region" on a MAX II CPLD?

I want to use an Altera/Intel MAX II device (EPM570) to drive 20 LEDs. They all have 20mA forward voltage, for a worst-case current draw of 400mA. The application note AN 286 explains how an Altera/...
user avatar
1 vote
3 answers
185 views

How much current can a MAX II I/O pin safely sink? 16 or 55mA?

This question is quite similar to this one. As far as I understood, an I/O pin configured as LVTTL output can be programmed to source/sink up to 16mA. This is what the MAX II handbook says in Table 2....
user avatar
1 vote
2 answers
111 views

Is fractional PLL the key functionality that defines whether a microcontroller is able to generate an analog TV signal?

I've been researching microcontrollers with the goal of outputting NTSC and/or PAL video signals. And when I look at the microcontroller specifications, it appears to me that the single most important ...
user avatar
2 votes
1 answer
337 views

Analog video chrominance decoding - PAL/NTSC

I'm implementing an analog video decoder on FPGA. I find some difficulties during chrominance decoding. I appreciate if you can help me. These are the steps as I'm doing: I generate an NTSC ColorBar ...
user avatar
  • 21
4 votes
2 answers
549 views

What does an NMOS transistor with the gate connected to the drain do?

I'm studying about PLAs and I came across this simple PLA design. What is the purpose of the highlighted transistors?
user avatar
0 votes
0 answers
126 views

Programmable delay line IC

I'm currently redesigning a delay line circuit. It is implemented on a Xilinx CPLD IC. Minimum delay is about 200 ns and maximum 600 µs, which is enough range for my project. What I want to do is ...
user avatar
  • 11
0 votes
1 answer
169 views

Checking the color of the pixel in VHDL

I'm trying to switch the colors of a 4-bitmap image using VHDL . In a 4 bit-image . Which means we have these types of colors . ...
user avatar
  • 15
0 votes
1 answer
103 views

Question On Logic Gates

In a small railway station, there are three platforms, #1, #2, #3. Up and down trains can enter in platform number #2 and #3, but platform #1 is only devoted to up trains. Design a logic circuit using ...
user avatar
1 vote
0 answers
29 views

5-V CPLD family in-circuit programmability

I have a need for a relatively small amount of 5V-logic (active at power-up) that would perfectly fit a package like that of the ATF750CL CPLD from Atmel/Microchip, the DigiKey page for these devices ...
user avatar
  • 8,165
2 votes
1 answer
306 views

How do you select pin functions on an EPM7128 CPLD?

I have some old Altera MAX EPM7128SLC84-15N CPLDs kicking around that I want to use to interface with 5v TTL logic. If you look at the pinout, some of the pins have more than one function (eg. Pin 2 ...
user avatar
0 votes
1 answer
35 views

Why a CPLD input pin behaves almost like an output pin?

I want my CPLD (a MAX II CPLD, EPM240, see datasheet) to accept an S/PDIF input using an optical receiver with TTL-compatible output. I tested the receiver alone: when giving proper power and optical ...
user avatar
1 vote
1 answer
68 views

Oscillator slows down when my hand hovers over it

I'm teaching myself VHDL using this MAX II CPLD board. I designed a frequency divider and 4-bit counter in VHDL using the onboard 50MHz oscillator. It seemed to work as the onboard LEDs are flashing ...
user avatar
1 vote
1 answer
324 views

How to use global clock in VHDL

I'm teaching myself CPLD programming using a development board with an Altera MAX II EPM240. After learning how to make a 4-bit digital counter in VHDL using clock/reset inputs, I'd like to use the ...
user avatar
0 votes
1 answer
83 views

CPLD High-Z pin - safe to drive over the high logic level voltage?

I have a CPLD connected to a BUS and an EEPROM. The bus has 3v logic and is 5v tolerant. The CPLD is 3v only. If I configure the CPLD pin to be in the high-z state and the eeprom drives that pin to ...
user avatar
  • 115
1 vote
0 answers
85 views

How do I feed a digital value to the PIC CLC system?

I'm playing with a nice new PIC16F15356, and investigating the Configurable Logic Cell (CLC) capabilities - basically a 4-cell mini-PLD on the chip that can take inputs from any of a list of 40 ...
user avatar
  • 936
0 votes
1 answer
66 views

Is there a relay package which can be triggered by a numeric coded pulse?

I would like to design a simple relay which is triggered by a series of pulses rather than just a high signal. e.g. the relay would have a serial data input. The relay would need to be "preset" with ...
user avatar
  • 165
0 votes
1 answer
101 views

Do I have match impedance while routing PAL video tracks?

I am designing a PCB with PAL video output. PCB contains 50ohm and 100 ohm traces. The connection between RF coax connector is very close. So 75 ohm traces are 80 micron for my stack-up. I am confused ...
user avatar
5 votes
2 answers
498 views

How does programming FPGAs and CPLDs differ? [closed]

I am learning to program programmable devices using a XC9572XL CPLD. I would like to know how much knowledge from programming CPLDs (in Verilog, VHDL) will be transferable to programming FPGAs (not ...
user avatar
  • 151
0 votes
1 answer
144 views

Programmable polarity switch for DC circuit

My question concerns a future research project in electrocoagulation (water treatment) I am planning right now. I will have a lab power supply connected to two (or more) plates in water. The ...
user avatar
0 votes
1 answer
108 views

First design with EEPROM

I want to get an idea of how to use a chip, code it and burn it. So an and gate could be a good choice. I've thought about using AT27C01024-70PU or AT89LP4052-20PU. Got this burner in mind: https://...
user avatar
0 votes
1 answer
588 views

Implementing 4-bit counter on GAL 16V8

I want to use a GAL 16V8 to implement a 4-bit counter using Verilog. I'm using Lattice's ispLEVER software. So far I have had no issues using Verilog to implement combinational logic. However, I ...
user avatar
-1 votes
1 answer
2k views

In practical, what really is a memory word in PLC?

I came across some plc code (structured text) being used in an industrial company. When I asked the question, I got a blurry answer. However, what I picked up is that it has something to do with the ...
user avatar
  • 317
3 votes
1 answer
245 views

What does the % symbol mean on plc addresses?

I've seen contacts assigned with a % symbol on ladder diagrams and plc structured text. For example a normally open start button would be %I1.02 and a coil would be %Q5.3 I understand the I and Q is ...
user avatar
  • 317
0 votes
1 answer
146 views

VHDL: case when using constants constructs

I'm having some trouble with the following statement ...
user avatar
  • 765
0 votes
1 answer
340 views

Are Verilog always blocks synthesized so that the sensitivity list items are settled by the time the block behavior is carried out?

In other words, if signal goes high and triggers the always block, will the block be synthesized in a way that the behavior in ...
user avatar
  • 1,084
1 vote
4 answers
868 views

AC-Coupling on Composite video

Many sources say that composite video input should be AC-coupled. Voltage levels for blank, black and white signal are also specified. How is it possible to detect these voltage levels after AC ...
user avatar

1
2 3 4 5