Questions tagged [programmable-logic]

Programmable digital logic devices include FPGAs, CPLDs, and older devices such as GALs and PALs. Programmable logic enables flexibly implementing complex digital functions in a single chip, from a few gates of glue logic to entire microprocessors or complex signal processing systems.

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200 Input Smart Multimeter Project

First off, thanks for taking the time to read this and help out. Here's a quick overview of what I am trying to design. I have a break out box that has 200 female probe inputs. Each input is numbered, ...
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Arithmetic - Absolute value

I constructed a circuit that calculates the absolute value of a signed 4-bit number in two's complement Then the second question of the exercise was to show the correctness of my circuit using the ...
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14 views

Should the Quartus programmer find the CPLD wired as shown via JTAG and USB Blaster?

I apologize beforehand for the elaborate description that follows: The accompying figure shows an Altera CPLD TQFP chip mounted in a socket-adapter for pin access. The chip is brand new (i.e. never ...
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58 views

Should I get a response when beeping two GND pins on a CPLD?

I have an Altera CPLD, 5M570ZT100I5N (100 pins, Quad-Flat-Package) mounted in a socket adapter to get access to the pins. I try to beep two GND pins on the same edge of the package, but get no ...
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Altera Quartus detects 2 CPLD devices instead of 1

I try to program a design I made using 5M40ZE64C5N CPLD. The software side was successful and I got a .pof file without any critical warnings or errors. The problem occurs when I try to upload the ...
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54 views

16V8 PLD alternatives for fast clock-to-data turnaround time

Context: I'm prototyping an MIPI I3C Basic slave device implemented on a PSOC5LP. (I3C is similar to I2C, but is spec'd to run at up to 12.9 MHz.) Due to a speed limitation of the PSOC, I'm ...
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49 views

How to write a linear interpolator in VHDL?

I have to create a linear interpolator in VHDL.My interpolator has to take 2 known values and using a factory level of 2 in interpolation return the interpolated value.Our signal is campionated with a ...
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141 views

Easier way to implement a large look-up table in Verilog?

I am designing the FPGA-based control for a power-electronic AC/DC converter. This converter has five output voltage levels, so it has 8 switching instances. The levels are given by ...
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367 views

3 digit BCD Counter in VHDL and Quartus II

I'm trying to make a 3 digits BCD counter in VHDL for Cyclone V FPGA from intel. I have an module-k counter design and I instantiate four counters in top level module (structural design): One counter ...
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Have I burnt my MAX II by excessive soldering?

I soldered my first TQFP 100 package, an Altera MAX II EPM570 CPLD, on a PCB. But I only found the "correct" way to solder (put flux on the pads and on the pins, melt some tin on a thin iron ...
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52 views

What is the relation of memory and PLD to (synchronous) sequential circuits?

In Mona's Digital Design book, Chapter 5 outlines the formal procedures for analyzing and designing clocked (syn- chronous) sequential circuits. The gate structure of several types of flip‐flops ...
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What is the difference between these two ladder logic diagrams?

First ladder logic diagram: Second ladder logic diagram: I am trying to implement a toggle switch. On the rising edge of "Change", it should toggle "ToggleThis". I thought the ...
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Which pins belong in a “I/O region” on a MAX II CPLD?

I want to use an Altera/Intel MAX II device (EPM570) to drive 20 LEDs. They all have 20mA forward voltage, for a worst-case current draw of 400mA. The application note AN 286 explains how an Altera/...
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98 views

How much current can a MAX II I/O pin safely sink? 16 or 55mA?

This question is quite similar to this one. As far as I understood, an I/O pin configured as LVTTL output can be programmed to source/sink up to 16mA. This is what the MAX II handbook says in Table 2....
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77 views

Is fractional PLL the key functionality that defines whether a microcontroller is able to generate an analog TV signal?

I've been researching microcontrollers with the goal of outputting NTSC and/or PAL video signals. And when I look at the microcontroller specifications, it appears to me that the single most important ...
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1answer
133 views

Analog video chrominance decoding - PAL/NTSC

I'm implementing an analog video decoder on FPGA. I find some difficulties during chrominance decoding. I appreciate if you can help me. These are the steps as I'm doing: I generate an NTSC ColorBar ...
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352 views

What does an NMOS transistor with the gate connected to the drain do?

I'm studying about PLAs and I came across this simple PLA design. What is the purpose of the highlighted transistors?
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Programmable delay line IC

I'm currently redesigning a delay line circuit. It is implemented on a Xilinx CPLD IC. Minimum delay is about 200 ns and maximum 600 µs, which is enough range for my project. What I want to do is ...
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94 views

Checking the color of the pixel in VHDL

I'm trying to switch the colors of a 4-bitmap image using VHDL . In a 4 bit-image . Which means we have these types of colors . ...
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59 views

Question On Logic Gates

In a small railway station, there are three platforms, #1, #2, #3. Up and down trains can enter in platform number #2 and #3, but platform #1 is only devoted to up trains. Design a logic circuit using ...
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5-V CPLD family in-circuit programmability

I have a need for a relatively small amount of 5V-logic (active at power-up) that would perfectly fit a package like that of the ATF750CL CPLD from Atmel/Microchip, the DigiKey page for these devices ...
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1answer
100 views

How do you select pin functions on an EPM7128 CPLD?

I have some old Altera MAX EPM7128SLC84-15N CPLDs kicking around that I want to use to interface with 5v TTL logic. If you look at the pinout, some of the pins have more than one function (eg. Pin 2 ...
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17 views

Why a CPLD input pin behaves almost like an output pin?

I want my CPLD (a MAX II CPLD, EPM240, see datasheet) to accept an S/PDIF input using an optical receiver with TTL-compatible output. I tested the receiver alone: when giving proper power and optical ...
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1answer
61 views

Oscillator slows down when my hand hovers over it

I'm teaching myself VHDL using this MAX II CPLD board. I designed a frequency divider and 4-bit counter in VHDL using the onboard 50MHz oscillator. It seemed to work as the onboard LEDs are flashing ...
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1answer
113 views

How to use global clock in VHDL

I'm teaching myself CPLD programming using a development board with an Altera MAX II EPM240. After learning how to make a 4-bit digital counter in VHDL using clock/reset inputs, I'd like to use the ...
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33 views

CPLD High-Z pin - safe to drive over the high logic level voltage?

I have a CPLD connected to a BUS and an EEPROM. The bus has 3v logic and is 5v tolerant. The CPLD is 3v only. If I configure the CPLD pin to be in the high-z state and the eeprom drives that pin to ...
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55 views

How do I feed a digital value to the PIC CLC system?

I'm playing with a nice new PIC16F15356, and investigating the Configurable Logic Cell (CLC) capabilities - basically a 4-cell mini-PLD on the chip that can take inputs from any of a list of 40 ...
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64 views

Is there a relay package which can be triggered by a numeric coded pulse?

I would like to design a simple relay which is triggered by a series of pulses rather than just a high signal. e.g. the relay would have a serial data input. The relay would need to be "preset" with ...
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52 views

Do I have match impedance while routing PAL video tracks?

I am designing a PCB with PAL video output. PCB contains 50ohm and 100 ohm traces. The connection between RF coax connector is very close. So 75 ohm traces are 80 micron for my stack-up. I am confused ...
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308 views

How does programming FPGAs and CPLDs differ? [closed]

I am learning to program programmable devices using a XC9572XL CPLD. I would like to know how much knowledge from programming CPLDs (in Verilog, VHDL) will be transferable to programming FPGAs (not ...
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49 views

Programmable polarity switch for DC circuit

My question concerns a future research project in electrocoagulation (water treatment) I am planning right now. I will have a lab power supply connected to two (or more) plates in water. The ...
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1answer
80 views

First design with EEPROM

I want to get an idea of how to use a chip, code it and burn it. So an and gate could be a good choice. I've thought about using AT27C01024-70PU or AT89LP4052-20PU. Got this burner in mind: https://...
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351 views

Implementing 4-bit counter on GAL 16V8

I want to use a GAL 16V8 to implement a 4-bit counter using Verilog. I'm using Lattice's ispLEVER software. So far I have had no issues using Verilog to implement combinational logic. However, I ...
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987 views

In practical, what really is a memory word in PLC?

I came across some plc code (structured text) being used in an industrial company. When I asked the question, I got a blurry answer. However, what I picked up is that it has something to do with the ...
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1answer
103 views

What does the % symbol mean on plc addresses?

I've seen contacts assigned with a % symbol on ladder diagrams and plc structured text. For example a normally open start button would be %I1.02 and a coil would be %Q5.3 I understand the I and Q is ...
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79 views

VHDL: case when using constants constructs

I'm having some trouble with the following statement ...
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1answer
225 views

Are Verilog always blocks synthesized so that the sensitivity list items are settled by the time the block behavior is carried out?

In other words, if signal goes high and triggers the always block, will the block be synthesized in a way that the behavior in ...
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4answers
495 views

AC-Coupling on Composite video

Many sources say that composite video input should be AC-coupled. Voltage levels for blank, black and white signal are also specified. How is it possible to detect these voltage levels after AC ...
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3answers
245 views

On-the-fly routing of digital and analog signals using unbuffered analog crosspoint arrays?

The issue I have is strongly related to a question which was asked over here. Unfortunately I did not find the answer I was looking for. Digging a bit more I've came across a class of IC's named ...
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2answers
818 views

CPLD based Pierce oscillator

I want to make a clock generator for Altera EPM240T100C5N using the CPLD itself as a Pierce oscillator. This CPLD has Schmitt trigger inputs so I guess this should be possible. What I`m not sure about ...
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268 views

Naming of PLA and PAL

I am studying the Programmable Logic Array (PLA) and Programmable Array Logic (PAL). I understood every detail I found about them including the implementation and difference between them. But I have a ...
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1answer
264 views

PLDs, DSPs, MCUs, MPUs and SoCs Typical Application [closed]

PLDs, DSPs, MCUs, MPUs and SoCs are all embedded devices, they can be programmed / configured to achieve a specific application. I've worked with MCUs and FPGAs in the past and realized that they are ...
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59 views

percision timing ratio of multiple lights blinking with different durations and intervals

I'm learning a lot of this as I go, my background is mostly in programming. I'm trying to setup a timing circuit for two sets of lights going into a model, and am trying to determine the best way to ...
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1answer
159 views

Orientation of switching elements in PLA

In a PLA, the switching elements in the wired-OR array are oriented as shown on the right of the figure (from Fundamentals of Logic Design, Roth/Kinney, 6th Ed, p.264). A logic 1 current appears to ...
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804 views

What's the difference between PLA and PAL logic devices? Is there one?

I've seen both PAL (which I understand is Programmable Array Logic) and PLA (I don't know what this one stands for. Programmable Logic Array?) used to refer to certain types of programmable logic ...
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1answer
807 views

Logic Design simple door security system with using MUX

I draw the cicuit without using any MUX. But my project says I need to use 4x1 MUXs and I couldn't find where to use 4x1 MUXs. I tried put MUX of each output but this was very pointless, no need to ...
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392 views

Are there CPLD / FPGA toolchains and workflows that bypass vendor IDEs? [duplicate]

Custom programming for FPGA boards is a similar and helpful question for any with the same as this, but they are different. In that thread they discuss custom options and building their own. This ...
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1answer
77 views

Input impedance of input pin from Xilinx CoolRunner II CPLD

Is the effective resistance mentioned in the image the input resistance for the CPLD pins? I am using Vccio at 3.3 V. (Image is from Xilinx CPLD IO guide application note).
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1answer
69 views

Resistors for xilinx coolrunner ii cpld pcb

I am making a pcb which contains among others a coolrunner ii cpld . I will programm the CPLD through jtag from a digilent cpld development board . I read in a xilinx application note that pull-up ...
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1answer
238 views

Implementing a simple counter using VHDL

Hi I'm trying to implement a counter with external control. I'm kinda new to VHDL and I keep getting syntax error for the following code. Can someone help me understand why there's an error here? <...

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