Questions tagged [programmable-logic]

Programmable digital logic devices include FPGAs, CPLDs, and older devices such as GALs and PALs. Programmable logic enables flexibly implementing complex digital functions in a single chip, from a few gates of glue logic to entire microprocessors or complex signal processing systems.

13 questions with no upvoted or accepted answers
Filter by
Sorted by
Tagged with
2
votes
0answers
159 views

Macrocell and Function Block optimization ISE XILINX

I get the following result when I compile my code in ISE. It says the CPLD is full, but I can't help but notice that the optimizer should be able to move elements from different function blocks to ...
1
vote
0answers
96 views

Verilog Code Optimisation

I have recently become involved in FPGA design and I am just testing out some new Zync SoC hardware. I have followed a tutorial online to blink some LED's however I have modified it to blink all the ...
1
vote
1answer
46 views

CPLD ispmach 4256ze starter pin connention configuration

I am an undergraduate student that working on a project which need to use an ispMACH 4256ZE CPLD to implement some data transfer function in my circuit. Need someone whoever have worked with CPLD to ...
1
vote
0answers
473 views

problem with CPLD and 24C16 EEPROM interface

Can any one say if it is possible to implement this code in ATMEL 24C16 EEPROM device for write the data. While I am implementing this with CPLD xc9572 I/O Pin declared as sda, scl there won't have ...
0
votes
0answers
27 views

How do I feed a digital value to the PIC CLC system?

I'm playing with a nice new PIC16F15356, and investigating the Configurable Logic Cell (CLC) capabilities - basically a 4-cell mini-PLD on the chip that can take inputs from any of a list of 40 ...
0
votes
0answers
80 views

What is BUFG constraint?

In Xilinx ISE I've made a small VHDL-code for a CPLD (XC2C32A) without a constraint file. On "Implement design" I right-clicked and chose "Run", and I got green checkmarks on Synthesize, Translate, ...
0
votes
0answers
23 views

Termination mode for CoolRunner CPLD (XC2C32A)

Fitting properties in Xilinx ISE offers some options for -unused and -terminate: ...
0
votes
0answers
30 views

PLC Ladder Logic using LRXSW

I'm working on a project for a summer internship and was hoping for some assistance with PLC Ladder Logic. I have been trying for the last couple of days to program the PLC to do what I want but have ...
0
votes
0answers
721 views

What's the difference between PLA and PAL logic devices? Is there one?

I've seen both PAL (which I understand is Programmable Array Logic) and PLA (I don't know what this one stands for. Programmable Logic Array?) used to refer to certain types of programmable logic ...
0
votes
2answers
779 views

8 to 3 Priority Encoder. Answer Verification

I am trying to design a priority encoder with a given priority table. Input: I0 I1 I2 I3 I4 I5 I6 I7 Priority: 2 7 6 1 5 0 3 4 Image attached!! Are these correct? Or I am failing?
0
votes
0answers
127 views

ABEL vs. VHDL edge detection

how can I detect signals edges in ABEL language? In other words, there is an equivalent of 'event (VHDL) in ABEL? Thanks for your help!
0
votes
0answers
65 views

ABEL-HDL - Default/reset values

I have as a school task to make a clocks & calendar in a HDL. As a source I have 10 MHz oscilator, which I managed to "slow down" to 1 Hz, as I want. I have asynchronous counters for seconds, ...
-1
votes
1answer
631 views

How do I generate a .JED file for programming an ATF750C using VHDL language?

I know how to program regular PAL/GAL22V10 chips and I am interested in using the enhanced Atmel ATF750C CPLD device because it seems 100% pin- and voltage-compatible with the PAL/GAL22V10 chips. I ...