Questions tagged [programmable-logic]

Programmable digital logic devices include FPGAs, CPLDs, and older devices such as GALs and PALs. Programmable logic enables flexibly implementing complex digital functions in a single chip, from a few gates of glue logic to entire microprocessors or complex signal processing systems.

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Can I use C language to program a CPLD/FPGA?

I wanted to know if I can program CPLDs /FPGAs using C language? If so, is it commonly practiced? What are the steps and the required & tools for the same?
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Verilog Code Optimisation

I have recently become involved in FPGA design and I am just testing out some new Zync SoC hardware. I have followed a tutorial online to blink some LED's however I have modified it to blink all the ...
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263 views

circuit programming using a SPLD or CPLD as a 16 bit (addressable memory) microcontroller [closed]

SPLD Reference https://www.arrow.com/en/categories/programmable-devices/programmable-logic-devices/splds CPLD Reference https://www.arrow.com/en/categories/programmable-devices/programmable-logic-...
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1answer
931 views

What is difference between register and distributed RAM

I'm trying to understand what is purpose of distributed RAM as a concept. As far as I understand it is implemented using LUTs just as registers are. However registers seems to be much more flexible: <...
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2answers
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Are there FPGA chips that permit to update the programmable logic from the logic itself?

For the research purpose I am interested are there FPGA chips that are capable to update the bytestream (the programmable logic) from the bytestream itself?
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1answer
224 views

How much RAM can I get from a MAX V logic element?

I need a CPLD or an FPGA in a hobby project. Since I have no experience of it I am trying to evaluate the different options and brands based on the constraints I already know, so that I can buy an ...
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1answer
106 views

Power on configuration for MCU using CPLD and pin multiplexing

simulate this circuit – Schematic created using CircuitLab Suppose we have simple same here. The logic behind this is very simple. During MCU boot it tests pins CONF1 and CONF2 for data on it (...
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1answer
58 views

How to program the P5Z22V10-da?

I got a handful of these chips at my job when they were being thrown away. They are Programmable Logic Devices. I found a datasheet online from 1997 that says that xilinx bought the ip for a similar ...
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780 views

8 to 3 Priority Encoder. Answer Verification

I am trying to design a priority encoder with a given priority table. Input: I0 I1 I2 I3 I4 I5 I6 I7 Priority: 2 7 6 1 5 0 3 4 Image attached!! Are these correct? Or I am failing?
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217 views

Not understanding why “if” is not triggered in modelsim vhdl sim

I am using a programmable-logic to decode a sequence of long or short impulses into latin letters according to morse code. I am using VHDL to describe our design, to be precise I'm using Quartus Prime ...
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3answers
252 views

What is the modern way to do small scale programmable logic?

I am designing a circuit for an electronic coil winder. It has a few binary counters, equality detectors, 7 segment decoders and flip flops. How it is possible to get all of this logic onto 1 ...
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1answer
868 views

Using Altera Max II Internal Oscillator

So I'm just getting my feet wet with CPLDs, in fact I programmed a chip successfully for the first time last night (success being programming it with the correct program, not the one recovered from it ...
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127 views

ABEL vs. VHDL edge detection

how can I detect signals edges in ABEL language? In other words, there is an equivalent of 'event (VHDL) in ABEL? Thanks for your help!
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2answers
946 views

Altera Max10 3.3V interface

Regarding Altera's MAX10 Cpld, I got some questions regarding the interface of this CPLD with 3.3V devices. I have set pins to 3.3V LVCMOS and I got this warning message in quartus: "Warning (169177):...
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1answer
632 views

How do I generate a .JED file for programming an ATF750C using VHDL language?

I know how to program regular PAL/GAL22V10 chips and I am interested in using the enhanced Atmel ATF750C CPLD device because it seems 100% pin- and voltage-compatible with the PAL/GAL22V10 chips. I ...
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1answer
64 views

Level converter usage when Vccb not present

I'm looking at incorporating a LSF0108 level shifter into a design to convert bidirectional GPIO signals from a 1.8V CPLD (Vcca) to an off-board device via ribbon cable. The header contains a voltage ...
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1answer
368 views

Spartan 6 Internal Memory [closed]

I am referring to below datasheet of IC XC6SLX45-L1FGG484C-ND. As per Digikey portal, it has Total RAM Bits = 2138112 If I want use internal RAM memory is there any specific pins associated with ...
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1answer
93 views

What triggered the need for VLSI chips in modems post 1200 baud?

I was chatting to my boss today and he said: My first job was electrical working in a factory for a modem company. The last model modem we made was the 1200 baud. After that they needed ...
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622 views

Altera MAX10 CPLD initialization IO state

I'm designing a pcb with an Altera MAX10 (10M02) CPLD used to do, amongst other things, bus arbitration between several memory chips (one /CS per chip). All the memory chip are on same bus so only ...
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ABEL-HDL - Default/reset values

I have as a school task to make a clocks & calendar in a HDL. As a source I have 10 MHz oscilator, which I managed to "slow down" to 1 Hz, as I want. I have asynchronous counters for seconds, ...
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1answer
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Is this the correct way putting multiple chips into one JTAG chain?

I am thinking about a hobby project that have a microcontroller and a CPLD connected together. Is this the correct way doing it? simulate this circuit – Schematic created using CircuitLab ...
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2answers
590 views

MITM on I2C Bus

I've been trying to design a module that will allow me to modify selected slave responses on an I2C bus. Here is the original bus configuration (the pull-ups and power connections are not shown for ...
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1answer
636 views

What are the low level programming waveforms for the Atmel ATF16V8B?

I want to program some ATF16V8B chips for a project. Naturally I don't have a programmer. No problem, I'll homebrew it with a Raspberry Pi. It will be fun. I only need one thing - I need the ...
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1answer
191 views

CPLD use with 6800 processor

Quick, and potentially silly question. I'm working on an old board design (late 70's) that utilizes a 6800 processor. The current board design left a few address lines from the CPU unused. I'd like ...
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2answers
615 views

External pull-down resistors on Xilinx XC95144XL

I need your help on the input termination of the Xilinx XC9500XL series. I have a Xilinx CPLD XC95144XL that performs as a LED matrix controller as well as a parallel-in serial-out shift register. A ...
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1answer
198 views

Feasibility Question - graphic acceleration on CPLD / FPGA …DSP?

I am a programmer new to electronics. I wanted to get a perspective on wether Programmable logic is feasible in allowing a basic math algorithm to be accelerated. Wanting to solve a ray-intersection ...
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2answers
309 views

Building a 20x20 matrix with vibrator motor coins

I am currently doing a project that requires a 20x20 matrix with coin type vibrator motors. I am not sure how to pull this off. What is the best way of driving all the motors all together? Provided ...
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1answer
934 views

Active low vs active High reset in CPLD

I am using Xilinx's CoolRunner-II series CPLD, and programming programmable logic for the first time. I have to use few of flip-flops with asynchronous reset. I wonder what is the difference between ...
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1answer
46 views

CPLD ispmach 4256ze starter pin connention configuration

I am an undergraduate student that working on a project which need to use an ispMACH 4256ZE CPLD to implement some data transfer function in my circuit. Need someone whoever have worked with CPLD to ...
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1answer
368 views

How do I reverse a binary counter after it counts to 1111? [closed]

I have 1 74LS191 4-bit synchronous up/down counter hooked to 2 74LS138 1-of-8 decoder/de-multiplexers and to 2 LED bars counting from 0000 to 1111. Now I have to reverse the count from 1111 to 0000, ...
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2answers
126 views

Trick VHDL Synthesizer to synthesize despite no input signals

I have a circuit I'm trying to debug and I'd like to eliminate the PLD from the root cause investigation. As such, I'd like to hardwire the outputs of the PLD to a 0...
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1answer
981 views

Verilog Ring Oscillator problem

I am trying to make a ring oscillator inside of a Xilinx's CoolRunner-II CPLD and trying to measure how many ring-oscillator cycle fits inside a low half of external 10MHz clock. Below is simple code ...
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VHDL - displaying 4 digits on 7-segment display

I wrote a vhdl code, that would display 4 digits on cpld 7-segment displays. I used a state machine to select the display, and with ... select instruction to select a set of bits given to the current ...
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1answer
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PAL data with ADC?

Is it possible to receive PAL video data from ADC of STM32 for example ? I made a program which convert analog data to digital data (tested with analog accelerometer). It is the same for PAL video ...
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3answers
564 views

Is it possible to replicate the ENIAC using logic gates

Can one rebuild a small scaled model of the original ENIAC computer using only logic gates?
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2answers
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Dividing numbers on an FPGA

I wrote a program for a Cyclone II FPGA that divides 2 64 bit numbers and returns if the remainder is 0 using the modulus (%) operation. When I compiled the program with 64 bit numbers for the ...
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Counter for 20 GHz clock

I am designing time critical application where I need time resolution in order of 100 picoseconds. I am considering to make an ring oscillator of 20 GHz and clock from ring oscillator. Is there IC'...
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1answer
638 views

Simulating LPM_counter on Modelsim gives 'z' (high impedance) output

I'm trying to implement a simple 9-bit frequency divider using the LPM_counter Module. Hardware and Software being used: ALtera Max V-CPLD Quartus II 64 bit Web Edition 15.0 ModelSim Altera Starter ...
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2answers
322 views

Access NEON coprocessor from programmable logic in Zynq

For the past few days I've been thinking about the neon coprocessor in the Zynq SoC and I have a question, is it possible to send instructions to the neon from the PL side of the SoC? Imagine I have ...
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2answers
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Pin Assignment in ispLEVER Classic

I have an ispGAL22LV10C that I'm trying to program. I wrote and synthesized the VHDL in ispLEVER Classic, but I cannot seem to figure out how to create pin assignments. Documentation on this is kind ...
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1answer
342 views

What is the purpose of a “BUF” in Xilinx ISE schematic?

I'm working on a schematic for a Xilinx CPLD using ISE. The schematic has a triangle symbol labeled "BUF" before every output, and also between some other nets. I can't really tell why some ...
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2answers
360 views

PLD, FPGA or microcontroller for PWM decode?

I need to handle PWM output from a single channel of an R/C receiver. I want to count the width of the pulse roughly in 4ms increments, and based on different widths take action by switching LEDs (20-...
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Please explain this price difference

When I paid a visit to my component supplier I spotted a few GAL22V10 available there. Asked the price - CNY24 (about US$4) a pop, NOS. Then I asked about ...
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1answer
559 views

Using a PAL for a seven segment display

I know next to nothing about PAL. I was wondering how one goes about programming a PAL (an old TIBPAL 16L8-25CN in my case) to drive a seven segment display, sort of like a HEF4511B. Right now I just ...
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1answer
117 views

Using the UCF constraints to assign one of two output ports

I've got a CPLD design which has one spare (Debug) pin. I'm trying to find out if it's possible to use the UCF file to select which output port (NET) that pin becomes. The problem is however, that I'...
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2answers
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Is it possible to generate a functional EEPROM (with persistence) inside an FPGA/CPLD

I'm looking to implement a small persistent 'configuration space' parallel EEPROM within a design. However, given the volatile nature of FPGAs, this doesn't seem possible without some very clever ...
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1answer
149 views

XC9536XL CPLD socket [closed]

I'm planning on using this CPLD: XC9536XL-5VQG44C. I only have one question when I used the chip in the lab the chip was mounted on top of some type of socket or base and that socket was connect to ...
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3answers
181 views

Linear Feedback Shift Registers on FPGA's

I want to put 256 linear feedback shift registers on a FPGA and each LFSR will have just two tap positions for the XNOR feedback and each register is 63 cells . I don't care if the LFSR'S are not ...
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1answer
349 views

Do CPLD devices lose non-volatile memory over long periods of time?

I have devices that use Xilinx XC9572XL CPLDs. They haven't been used (as in: not powered at all) for almost seven years, and symptoms would point to the CPLDs being at fault. I couldn't find much on ...
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1answer
320 views

How do I use the on board oscillator?

I have the MAX II EPM240 CPLD Minimal Development Board which has an on-board 50 MHz oscillator. According to the "EPM240MAINBOARD Schematic Diagram" file, the output of the oscillator goes to PIN 63, ...