Questions tagged [programmable-logic]

Programmable digital logic devices include FPGAs, CPLDs, and older devices such as GALs and PALs. Programmable logic enables flexibly implementing complex digital functions in a single chip, from a few gates of glue logic to entire microprocessors or complex signal processing systems.

Filter by
Sorted by
Tagged with
1
vote
1answer
221 views

Feasibility Question - graphic acceleration on CPLD / FPGA …DSP?

I am a programmer new to electronics. I wanted to get a perspective on wether Programmable logic is feasible in allowing a basic math algorithm to be accelerated. Wanting to solve a ray-intersection ...
1
vote
2answers
365 views

Building a 20x20 matrix with vibrator motor coins

I am currently doing a project that requires a 20x20 matrix with coin type vibrator motors. I am not sure how to pull this off. What is the best way of driving all the motors all together? Provided ...
1
vote
1answer
1k views

Active low vs active High reset in CPLD

I am using Xilinx's CoolRunner-II series CPLD, and programming programmable logic for the first time. I have to use few of flip-flops with asynchronous reset. I wonder what is the difference between ...
1
vote
1answer
47 views

CPLD ispmach 4256ze starter pin connention configuration

I am an undergraduate student that working on a project which need to use an ispMACH 4256ZE CPLD to implement some data transfer function in my circuit. Need someone whoever have worked with CPLD to ...
-1
votes
1answer
463 views

How do I reverse a binary counter after it counts to 1111? [closed]

I have 1 74LS191 4-bit synchronous up/down counter hooked to 2 74LS138 1-of-8 decoder/de-multiplexers and to 2 LED bars counting from 0000 to 1111. Now I have to reverse the count from 1111 to 0000, ...
0
votes
2answers
130 views

Trick VHDL Synthesizer to synthesize despite no input signals

I have a circuit I'm trying to debug and I'd like to eliminate the PLD from the root cause investigation. As such, I'd like to hardwire the outputs of the PLD to a 0...
0
votes
1answer
1k views

Verilog Ring Oscillator problem

I am trying to make a ring oscillator inside of a Xilinx's CoolRunner-II CPLD and trying to measure how many ring-oscillator cycle fits inside a low half of external 10MHz clock. Below is simple code ...
0
votes
2answers
8k views

VHDL - displaying 4 digits on 7-segment display

I wrote a vhdl code, that would display 4 digits on cpld 7-segment displays. I used a state machine to select the display, and with ... select instruction to select a set of bits given to the current ...
1
vote
1answer
3k views

PAL data with ADC?

Is it possible to receive PAL video data from ADC of STM32 for example ? I made a program which convert analog data to digital data (tested with analog accelerometer). It is the same for PAL video ...
1
vote
3answers
811 views

Is it possible to replicate the ENIAC using logic gates

Can one rebuild a small scaled model of the original ENIAC computer using only logic gates?
3
votes
2answers
2k views

Dividing numbers on an FPGA

I wrote a program for a Cyclone II FPGA that divides 2 64 bit numbers and returns if the remainder is 0 using the modulus (%) operation. When I compiled the program with 64 bit numbers for the ...
7
votes
5answers
6k views

Counter for 20 GHz clock

I am designing time critical application where I need time resolution in order of 100 picoseconds. I am considering to make an ring oscillator of 20 GHz and clock from ring oscillator. Is there IC'...
0
votes
1answer
795 views

Simulating LPM_counter on Modelsim gives 'z' (high impedance) output

I'm trying to implement a simple 9-bit frequency divider using the LPM_counter Module. Hardware and Software being used: ALtera Max V-CPLD Quartus II 64 bit Web Edition 15.0 ModelSim Altera Starter ...
1
vote
2answers
325 views

Access NEON coprocessor from programmable logic in Zynq

For the past few days I've been thinking about the neon coprocessor in the Zynq SoC and I have a question, is it possible to send instructions to the neon from the PL side of the SoC? Imagine I have ...
1
vote
2answers
2k views

Pin Assignment in ispLEVER Classic

I have an ispGAL22LV10C that I'm trying to program. I wrote and synthesized the VHDL in ispLEVER Classic, but I cannot seem to figure out how to create pin assignments. Documentation on this is kind ...
2
votes
1answer
375 views

What is the purpose of a “BUF” in Xilinx ISE schematic?

I'm working on a schematic for a Xilinx CPLD using ISE. The schematic has a triangle symbol labeled "BUF" before every output, and also between some other nets. I can't really tell why some ...
2
votes
2answers
375 views

PLD, FPGA or microcontroller for PWM decode?

I need to handle PWM output from a single channel of an R/C receiver. I want to count the width of the pulse roughly in 4ms increments, and based on different widths take action by switching LEDs (20-...
5
votes
2answers
438 views

Please explain this price difference

When I paid a visit to my component supplier I spotted a few GAL22V10 available there. Asked the price - CNY24 (about US$4) a pop, NOS. Then I asked about ...
1
vote
1answer
645 views

Using a PAL for a seven segment display

I know next to nothing about PAL. I was wondering how one goes about programming a PAL (an old TIBPAL 16L8-25CN in my case) to drive a seven segment display, sort of like a HEF4511B. Right now I just ...
2
votes
1answer
123 views

Using the UCF constraints to assign one of two output ports

I've got a CPLD design which has one spare (Debug) pin. I'm trying to find out if it's possible to use the UCF file to select which output port (NET) that pin becomes. The problem is however, that I'...
0
votes
2answers
2k views

Is it possible to generate a functional EEPROM (with persistence) inside an FPGA/CPLD

I'm looking to implement a small persistent 'configuration space' parallel EEPROM within a design. However, given the volatile nature of FPGAs, this doesn't seem possible without some very clever ...
-2
votes
1answer
151 views

XC9536XL CPLD socket [closed]

I'm planning on using this CPLD: XC9536XL-5VQG44C. I only have one question when I used the chip in the lab the chip was mounted on top of some type of socket or base and that socket was connect to ...
0
votes
3answers
205 views

Linear Feedback Shift Registers on FPGA's

I want to put 256 linear feedback shift registers on a FPGA and each LFSR will have just two tap positions for the XNOR feedback and each register is 63 cells . I don't care if the LFSR'S are not ...
1
vote
1answer
389 views

Do CPLD devices lose non-volatile memory over long periods of time?

I have devices that use Xilinx XC9572XL CPLDs. They haven't been used (as in: not powered at all) for almost seven years, and symptoms would point to the CPLDs being at fault. I couldn't find much on ...
1
vote
1answer
411 views

How do I use the on board oscillator?

I have the MAX II EPM240 CPLD Minimal Development Board which has an on-board 50 MHz oscillator. According to the "EPM240MAINBOARD Schematic Diagram" file, the output of the oscillator goes to PIN 63, ...
0
votes
1answer
191 views

How is the signal assigned to a pin by default

Here's the simple verilog code that contains WR_n signal. This signal (net) is not explicitly assigned to a LOC (pin) in the .ucf file. The design implements without any errors. I would assume that ...
0
votes
1answer
1k views

Charging Indicator for any battery (Charge Monitor)

We see in all today electronic devices like mobile a Visual battery charging indicator,that a graphical Container composed of bars that increases one by one when the battery is charged for long, and ...
3
votes
1answer
734 views

Is it possible to multiplex SIM cards using a CPLD?

I am building a hobby project using a GSM module and would like to be able to switch between multiple SIM cards, in case one stops working or I have poor reception on one provider (the project will be ...
0
votes
1answer
213 views

Coolrunner2 GSR Global Set/Reset

So the Coolrunner2 CPLDs have a feature called GSR or "Global Set/Reset". In the documentations I found lots of references to it but no chapter that tells me how the GSR exactly works and more ...
0
votes
1answer
248 views

Change PL clock

I'm designing my project in Vivado and I had a WNS (Worst negative Slack) of -2.67 ns (my PL clock was 200Mhz). I had some problems when running my design since the results where good sometimes and ...
10
votes
2answers
6k views

What's the difference between CPLD and an FPGA? [closed]

What's the difference between a CPLD and an FPGA?
0
votes
4answers
358 views

How to check if sync signal is inverted?

in input of a CPLD, I have a syncronization video signal that can be like this (positive polarity): or like this (negative polarity): I want to recognize the type of the sync signal and invert the ...
3
votes
2answers
858 views

what to do with JTAG pins when idle?

So I have this design here where I talk via JTAG from a microprocessor to a CPLD. The JTAG protocol is done via bit-banging of four GPIO pins. This connection is just very infrequently. It's just ...
1
vote
1answer
125 views

Is there an easy way to physically implement a simple digital circuit?

I designed a digital circuit which, in total, has about 27-30 gates. Building that circuit in real life using a 74 series IC would mean using a lot of through hole/SMD chips, which wouldn't be ...
1
vote
2answers
744 views

SBUF/SCON 8085 Serial Communication

While using 8085 especially at a different baud-rate , DTE being the micro-controller, DCE being any modem/or a Display device coupled with RS232 db9 or db25 port. I can understand SBUF can Store ...
-1
votes
1answer
183 views

Can a microprocessor ( specifically the ALU) be considered as an FPGA that is re-programmed by the Instruction Decoder

So, I have been reading about FPGAs. As I understand, they work by providing logic blocks for the programmer to link together to solve a particular task. Many such tasks may run in parallel; so an ...
2
votes
0answers
172 views

Macrocell and Function Block optimization ISE XILINX

I get the following result when I compile my code in ISE. It says the CPLD is full, but I can't help but notice that the optimizer should be able to move elements from different function blocks to ...
1
vote
1answer
186 views

4 port 12 bit mux is consuming 48 macrocells!

I'm programming on the coolrunner II cpld. It is running out of resources so I decided to implement my own 4 port, 12 bit mux. After implementation I find that it's using over 40 macrocells. Any way ...
3
votes
1answer
198 views

VHDL - address comparison yields wrong result

I am developing TS-CAN1 emulator on Atmel's ATF1508AS. One part of an application is an address decoder implemented as follows (only interesting parts are left): ...
-2
votes
1answer
37 views

What's the order of the array generated by Verilog? Syntax

What is the correct interpretation between these two lines: wire[2:0] w = SW[17:15] = {SW[17], SW[16], SW[15]} wire[2:0] w = SW[17:15] = {SW[15], SW[16], SW[17]} When I call w[0] will I get SW[15] ...
1
vote
1answer
820 views

Implementing a counter in VHLD with edge triggered clear

I'm still giving my first steps learning VHDL and after a couple of days I could not yet find a solution for this problem. What I'm trying to do is to implement an LCD controller on an Altera MAX II ...
13
votes
5answers
6k views

What would make me choose Verilog or VHDL over schematic design on CPLDs or FPGAs?

I have absolutely no background in programmable logic, I use mostly microcontrollers in my projects but recently I needed to work with video and the microcontroller is just too slow for what I needed ...
1
vote
2answers
184 views

PLC unit power issues

I am creating my own PLC, just for practice with PLCs (as I am an electrical apprentice). I have bought a power supply which changes 240V AC to 24V DC. When it is connected to my PLC unit, and I read ...
1
vote
3answers
846 views

What exactly does a 10-transistor XOR gate look like?

I need a schematic for a 10-transistor xor gate, I have searched everywhere and I see 8, 12, 6, but I can't see 10. What does it look like in a transistor like picture?
2
votes
2answers
732 views

Create delay shorter than a clock period in CPLD

I have several peripherals that connect to CPLD. They all have different propagation delays, and to compensate that I wish to introduce about 10-15ns delay into the CPLD logic. In detail, clkOUT ...
3
votes
1answer
143 views

IO voltage properties in CPLD

I am using CoolRunnerII CPLD and wish to know what is the I/O Voltage Standard setting in the fitting properties: I know that Vcc must be 1.8V. I also know that I define the IO bank voltage by ...
0
votes
2answers
294 views

Crystal <--> CPLD interface

Could someone advise me on what would be a good practice to interface the CoolRunnerXC2C256 with an external clock? I wish to use KC5032A20 crystal and have it to drive global clock GCK2 (pin 38). ...
6
votes
1answer
611 views

Can a CPLD be reprogrammed just like a Microcontroller?

Given that microcontrollers can be reprogrammed multiple times, does this apply to CPLDs as well? In particular, I am interested in Xilinx's CoolRunner-II. Until now, I was positive about the re-...
0
votes
1answer
3k views

The IDCODE read from the device does not match the IDCODE in the BSDL file

I checked many different posts with the same problem, but none of the advises were helpful thus far. So, I am using ISE 14.7, DLC9G USB Cable, and trying to program the XPLA3 256 CPLD. After ...
1
vote
1answer
699 views

Proper oscillator for CPLD

I plan to use KC5032A40 as a clock source for CoolRunnerXPLA3 256. I power it with 3.3V and interface it as suggested: I perform the measurement at the Test Point and do not add any CL capacitance, ...