Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Intel FPGA (formerly Altera).

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33 views

How to open pin planner in Xilinx Vivado?

I am an Intel Quartus user getting to know Xilinx Vivado. I am using Xilinx Vivado for the first time. I am using Digilent ARTY S-7 FPGA board for learning purpose. I am have created a blinking LED ...
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68 views

Build on-chip ROM in HDL

I wrote the next code in quartus 15.0, where I show what I want to do for a specific project. I can write it both in VHDL and Verilog HDL, but verilog is notoriously shorter. ...
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46 views

JTAG Communication Failure in ARRIA 10 FPGA

Has anyone bricked an ARRIA 10 FGPA (or any FPGA) and successfully unbricked it? I have an ARRIA 10 that uses an EPCQ-L256 external memory to configure the FPGA. When I uploaded some code, I think I ...
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84 views

7-segment display communication

I have attempted to solve this problem making kmaps for the binary counter, mux and decoder however I'm getting stuck on the making them all talk to each other bit, I am using a ATmega32L and a ...
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74 views

What does 1'h1 mean in the RTL viewer diagram

Just new to Quartus, from my understanding 1'b1 basically means 1 as input, but why it shows 1'h1 on the diagram instead of 1'b1 or just 1?
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80 views

Why is my code output always showing 0?

This is a 4 bit counter code written using Verilog HDL on Quartus. Can somebody explain why is my output o always showing 0? Code in Text : ...
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69 views

What does symbol width and "beat" mean for Avalon-ST interface?

This is the GUI for the Avalon-ST Source BFM found in Quartus Platform Designer. I am trying to understand, what is the meaning of Symbol width and "beat" for streaming interface? The ...
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30 views

How to see the conections in a decoder Quartus II web edition

I have a decoder whos 16 bit output is conecting to a one bit input. Acording to my knowldge of the design it would make sense. How can i know which output port of the decoder is conecting to that ...
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189 views

Quartus cannot place PLL

I am using Intel/Altera Cyclone V 5CSEMA4U23C6 on DE0-nano-SoC board. My design is using one PLL that I added a while ago in Platform Designer. Though it isn't explicitly calling Fractional PLL based ...
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31 views

Why doesn't Qsys let me connect two conduits together by complaining that they do not have associated resets?

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16 views

Automatic launch of a tcl script at start of Quartus PlatformDesigner

Intel Quartus supports tcl scripts automation - specifically three specific options where user may define variables in the project file to automatically invoke custom tcl scripts at given points of ...
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146 views

Constraining simple design

I am stydying the Quartus II + TimeQuest Analyzer. The documentation is abreast, the examples are not that of, and explanations for beginners are scarce. Here's the simple code: ...
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67 views

How to use command-line to cause Qsys to generate only synthesis or only simulation files?

In my project there are several Qsys files. Some of them are for synthesis but most are for testbench. When changes are made to source code, I usually just run generate Qsys system from the GUI and ...
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72 views

How to make Quartus generated programming files for two different but pin compatible FPGAs?

On most porotype boards there is a smaller FPGA which does fit the design but cannot fit a lot of signal tap tap to aid in debugging. Thus, I got a few boards modified with the largest pin compatible ...
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28 views

Manually override Quartus Fitter/Pin Assignment constraints

I have a design that I want to synthesize for / upload to a Max 10 FPGA. One of the inputs goes to a PLL. Quartus now claims, that the neighbouring IO pin is too close to the PLL input pin and won't ...
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81 views

Unexpected change when reading input signals in a VHDL Finite State Machine

I implemented a FSM in vhdl using two processes; A sync process for state transition ...
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194 views

How can I correct these Verilog syntax and declaration errors?

I am currently working on an Arduino to NIOS II Compiler that I am using on GitHub. I have provided a link to the compiler here: https://github.com/dimag0g/nios_duino. The issue I am having is that I ...
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177 views

How to form a 8-Bit bidirectional shift register using two 4-bit bidirectional shift registers?

I really had some trouble with one design question in my homework (the deadline has passed). We were asked to design a 4-bit bidirectional shift register using D-Flip flops and after that to create a ...
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60 views

TeraTerm can't detect the correct port, FPGA Project

I'm a beginner at FPGA design and have been actively trying to complete new projects to get more hands on experience. The project I'm currently working on is a tutorial from nandland. This video ...
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410 views

How do I correct this SystemVerilog syntax error?

I am working to reuse some Arduino code on my Cyclone V GX FPGA using a compiler I have found on GitHub. https://github.com/dimag0g/nios_duino I was also able to generate the HDL code for both the ...
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77 views

How to ignore simulation only ports when mapping to FPGA pins?

A design has a number of simulation ports that should not be tied to FPGA pins. A VHDL example is shown in the source below, where the sim_only_* ports are for simulation only, thus should not be ...
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120 views

Reusing Quartus block schematic symbol file in another project

I am working on a Quartus project, requiring the usage of some designs previously created as block schematic design files in some other Quartus projects. I generated symbol files from the top design ...
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31 views

Avoiding node removal during optimization for preliminary estimation

I'm doing a preliminary FPGA design where I want to establish whether I will be able to implement the pinout and clock routing -- basically I'm placing all the hard IP blocks and wiring up the clocks, ...
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145 views

How does Quartus pin planner know about voltage in each I/O bank?

It is possible to specify a range of I/O standard options in Quartus pin planner. I am trying to understand a few things: How does Quartus know what voltage is supplied to each bank? Why does Quartus ...
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161 views

Quartus II - State Machine Viewer does't show all arrows/conditions?

As can be seen in the red circle, only arrows with condition a are shown, there is no !a condition at all. To replicate this ...
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26 views

I am getting the opposite result from simulation from Quartus in two cases, while the others are correct

I have created a Quartus schematics according to the following K-map; However, I am getting a wrong result; the output should be 1 when the input is 7 and 0 when 14, but it is going the opposite. The ...
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752 views

Quartus Prime Lite: Error (209053): Unexpected error in JTAG server -- error code 35 and Error 202940 Can't access JTAG chain with SSH

Today I received a Terasic USB Blaster and I want to program an Altera 10M04SCE144C8G FPGA. I am using the Intel Quartus Prime 20.1.1 Lite Edition installed in Ubuntu 20.04. This FPGA has already been ...
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34 views

Multiple Avalon Data Master in Nios II Custom Instruction Crashes CPU

I am attempting to make a Nios II Custom Instruction which performs the function of summing a floating point array, given the array pointer and length. The custom instruction component has an Avalon ...
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2answers
144 views

Registered signal and Fmax in Timing Analyzer from Quartus II

I have the following module that is a simple register: ...
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498 views

How to view the internal signals of module in ModelSim using the testbench?

I have looked over this tutorial (Tutorial - Using Modelsim for Simulation, for Beginners. ) how to add waves and write test benches for VHDL module I looked over some answers as well like this one to ...
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26 views

Why I cannot edit waveform in ModelSim Intel?

I would like to create my own testbench for the code vhdl. I tried to use the edit function from ModelSim but it does show blank as you see on the picture. what could I have missed?
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27 views

typing error showing on quartus prime lite?

I am trying for few hours to understand why Quartus Prime Lite keep showing an error when I compile this basic VHDL code, I kept it like this to understand why it is showing an error just by typing!!!....
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33 views

How to implement a comparator logic gate in Quartus software? [closed]

Been trying for hours...How do I properly implement the following expressions: F0 = A0'A1'B0 + A0'B0B1 + A0B0'B1' + A1'B0B1 F1 = A1'B1 + A0'A1B1' + A0A1'B0' + A0B0'B1 + A1B0B1' I'm using NAND & ...
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113 views

Does Quartus support UVM in files with .sv extension?

I want to learn UVM later (i am starting with verilog first, systemverilog is next) but i have this doubt in my head, i have seem examples in the web but they use Modelsim, so my doubt is, if i make ...
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63 views

What is the proper method to become able to connect conduit signals inside Qsys?

Qsys (now known as Platform designer) identifies Avalon MM, Avalon ST, Clock, Reset and some other type of interfaces and makes it trivial to be able to connect them between different blocks. However, ...
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163 views

Help me debug these VHDL errors please

There are just 6 errors now Can't trace errors in this VHDL ...
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387 views

How to make a very large lookup table in Verilog?

I have a requirement to make a verilog module that takes a Gray code integer i and returns the Gray coded integer i-1 using combinatorial logic only. When I look up examples of Gray decoding, for ...
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83 views

Unable to generate device simulation libraries from Quartus Prime

I am using Quartus 18.1. I am trying to generate device simulation libraries as per the procedure here: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/...
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113 views

What does "database" do in Quartus?

Quartus has settings to export/import database under the project drop-down box. The project directory contains two folders named db and incremental_db. What is this "database" and what does ...
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270 views

Output waveform of TCS3200

I am trying to use TCS3200 color sensor for my project with De0 nano FPGA board. The output of TCS3200 is a square waveform and i am confused how to use that waveform for a particular task. I searched ...
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42 views

why the D-FF does not use the clock assigned by me Quartus schematic

The schematic given above is a simplified version of a design. But this is enough to explain my problem. As you can see from the schematic, clock signal of second dff is connected to (Q0' & clk). ...
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2answers
261 views

UART receiving random values

I tried to transmit "S" using De0 nano FPGA board and UART over USB module . The problem is i am not receiving "s" constantly . I am using the software Called Hterm to see ...
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44 views

How to let Quartus generate VHDL out of Qsys automatically

I was wondering how I can get Quartus to automatically generate VHDL IP from Qsys files, instead of the default Verilog. I know I can change this in the command line or Platform Designer GUI for each ...
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180 views

problem in adding IP to platform designer

I'm new to platform designer and I want to add an ALT PLL intel FPGA IP to a platfrom designer project but after opening Mega wizard plugin manager and setting up the requirements, IP does not add to ...
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38 views

Pin Assignments for DE5-Net

I am porting a working sequential circuit from a DE0-Nano to a DE5-Net. The circuit is driven by one global 50 MHz clock signal. The circuit only has one input and one output port for serial ...
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241 views

Possible to use Segger J-Link with Intel Quartus to flash FPGA?

Does anybody know if it's possible to use a Segger J-Link with Intel Quartus to flash an FPGA?
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143 views

Long enumeration in VHDL to recognize a state machine

In order that Quartus II recognizes a state machine in a case / when statement the case must be applied on an enumerated type. In my code I am using a case on integer number going from 0 to 230. And ...
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924 views

3 digit BCD Counter in VHDL and Quartus II

I'm trying to make a 3 digits BCD counter in VHDL for Cyclone V FPGA from intel. I have an module-k counter design and I instantiate four counters in top level module (structural design): One counter ...
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67 views

How can Quartus Prime System Console be used to read/write a whole file?

I want to find a way to read/write whole file from/to my Intel FPGA design. The file being written provides data to be processed and the file being read shall contain the results of the processing ...

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