Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Altera.

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Why is my seconds counter in verilog jumping values behaviour?

I am implementing a seconds counter on the Altera DE-1 Educational Board powered by the old Cyclone 2 FPGA. My plan is to make a 'down-clocker' that takes the on-board 50 MHz clock and produces a 1 Hz ...
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32 views

I2C on Altera DE1-SOC

I have been doing a project on the Altera FPGA De1 Soc and the main goal is to "talk" to a extern proximity sensor using I2C. Afrer a research I found that the LTC connector has the I2C interface but ...
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21 views

How to use tcl script to generate Qsys system inside Quartus?

When I change .vhd files I need to regenerate Qsys and then compile the design. How can I use tcl commands inside Quartus to regenerate the Qsys and then compile the project as well?​ Is there a way ...
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28 views

How can Qsys component configuration be accessed in software?

I'm designing a Qsys component which I want to be user-configurable. It has config parameters which are defined in the TCL file. For example, for a GPIO bank component I would write: ...
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1answer
67 views

Error (10536): VHDL Loop Statement error at InstructionMemory.vhd(31): loop must terminate within 10,000 iterations

Can someone help me solve this problem? Its my code below: ...
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1answer
80 views

PLL with input depend output CLK

Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed. In ...
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1answer
67 views

altera FPGA acting like OR gate when programed as AND gate

I'm new to altera fpga , I've bought development board based on EP4CE6E22 cyclon IV and tryed to program it with basic program in quartus environment ...
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44 views

Can't achieve requested … bandwidth type?

I have two cascaded PLLs in the design, and read here that it is the best to set first PLL into low bandwidth, and second PLL into high bandwidth in order to decrease jitter accumulation. I had "Auto" ...
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1answer
102 views

Why doesn't my verilog state machine toggle state?

I have written a state machine in Verilog. However, when I try to simulate it with my testbench, it does not advance from the STATUS_IDLE state to the STATUS_READY state. Why isn't the state machine ...
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126 views

Inherent Pseudo-Randomness in modern FPGA design tools

Do Place & Route algorithms of modern FPGA design tools ( Qaurtus / Vivado / etc... ) have inbuilt randomness in them ? I.E: Would it be possible to get 2 different results when compiling the ...
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29 views

regarding bidirectional accessing of array in verilog

Accessing ram logic in Verilog with an initial block gives an error "cannot synthesize initialized RAM logic <name> " A part of the code will be as follows (...
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1answer
46 views

For a Quartus project what files must be added to a git repository?

A Quartus project generates huge number of files as we proceed with design compilation and debug automatically. Provided that I wish to add my Quartus project to a Git repository and not just the hdl ...
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105 views

FPGA too slow for my ripple carry adder?

I wanted to make simple LED counter on my FPGA board (Cyclone IV EP4CE). I've made (from scratch - from NANDs) 4bit counter and 26 bit one. I have 26bit signal that is wired (port map) into 26 bit ...
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19 views

In Intel Quartus Static Timing Analyzer should -ve setup slack on a path in Slow_900mV_0C model also show up in Slow_900mV_100C model?

I am trying to understand why the paths with -ve slack in Slow_900mV_0C model do not show up in Slow_900mV_100C model. I am using Arria 10 GX. I would think the process part of the model is likely ...
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82 views

What's the actual cause of unbalanced combinational logic?

So far when I find timing issues, I try to pipeline combinational logic. It always works. Today, my Quartus Compilation Report show up -ve slack values. I double check it with TimeQuest Timing ...
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52 views

How can I edit my quartus project to work with relative paths?

I have a project in quartus with many files containing full-path-links to other files. I found a way to make it work on my machine with a different location, but that is the cheat way. I would like to ...
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1answer
157 views

Bug in my SPI implementation (VHDL)

I'm new to VHDL/FPGA programming and I experienced some weird behavior in my SPI-Slave implementation. What I did: SPI-Master: I'm using an Arduino (ATMega328p MCU) as the SPI-Master. For debugging, ...
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27 views

Why does functional simulation generate Zs?

I have a very simple project, I share the files in this github repo If I run a functional simulation (Waveform.vwf in the repository) I get some 'Z' in the value of an internal register, see the ...
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55 views

Quartus Prime: Block synthesized away - why?

Doing my very first steps with FPGA. I successfully built an SPI slave (code found somewhere in the web) that receives something and turns an LED (via output SPI_DONE) on my Altera Max10 evaluation ...
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17 views

Is there a way for Quartus System Console to get base addresses of memory mapped peripherals from the sopc file?

The Quartus System Console is a powerful tool when it comes to design verification. We can use tcl script to read/write memory mapped slaves. I have noticed that in the examples I have seen so far, ...
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20 views

Why doesn't Qsys force all peripherals (and masters) to use fixed data width of say 32 or 64 bits?

In Qsys, the address space is byte addressable. However, the datawidth of the master shall most likely be more than a byte. This could create a situation where sometimes a peripheral has wider data ...
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1answer
233 views

How do I know if not using FPGA dedicated clock input for a PLL pin is bad for my design?

PLLs are hard blocks in silicon. They are connected to specific pins for their clock input and drive specific pins for clock output. It is possible that we choose a "non-dedicated" pin for clock input/...
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1answer
26 views

Can specific pipeline latency arithmatic block be inferred when using * or / operator in VHDL?

When using the * or / in VHDL, the synthesis tool shall infer the appropriate IP block to carry out that operation. If we open the actual GUI for that IP block we can find a lot of options e.g select ...
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1answer
108 views

What is the proper methodology to create portable FPGA designs?

FPGA designs may contain RTL along with IP blocks. These IP blocks most likely shall be from the vendor of the FPGA. Examples of such IP blocks are instantiating dual clock FIFOs, floating point and ...
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74 views

Get more AS-attached flash chip information from ALTASMI

I am playing with the attaching various configuration flash devices to the Altera Cyclone 3. In particular, I want to replace EPCS16 (2MB) with W25Q128 (16MB) - for both size and cost reasons. Is ...
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1answer
67 views

74193 stops working after compilation on another PC (QUARTUS)

I got a Quartus project with a mod 22 counter using 74193 from a friend. It works just fine when I run a simulation before a compilation on my PC, but after I compile it on my PC, it stops working ...
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229 views

Error (10028): Can't resolve multiple constant drivers for net “rf[7][XX]” at registerfile8x32.v

Hello Im making a register file 8x32 in verilog, the sim looks good but when I compile on quartus it makes Error (10028): Can't resolve multiple constant drivers for net "rf[7][31]" at ...
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1answer
50 views

SDC constraints for reusable component

I have a simple register based clock divider component I can drop in when I don't have a spare PLL: ...
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1answer
300 views

Altera Cyclone II Quartus II JTAG Programming Error

I'm trying to program a Cyclone II I bought here using Quartus II 13.0sp1 on Arch Linux. I'm trying to program it with a very simple Verilog program with three inputs and two outputs and a few simple ...
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1answer
448 views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
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296 views

Altera-Modelsim simulation wont start when I add a module instance in my main testbench module

Edit: it is something with the simulate_camera_output module that Modelsim doesn't like. Tried with a simple test module and it works fine. Looking for a way to ...
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1answer
66 views

1 Byte Register broken into 2 Nibble outputs not working VHDL/ModelSim

I have made a 1 byte instruction register in VHDL. Instead of having a 1 byte output, I have created an upper nibble output and a lower nibble output. The lower nibble output is special because it ...
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1answer
128 views

Negative Edge Trigger and Asynchronous Clear not working in ModelSim

I have created a 4 bit counter with the following inputs and outputs clockN: active low clock clearN: active low clear cP: When high, the counter counts. When low, the counter stays the same. eP: ...
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186 views
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411 views

Error (suppressible): (vsim-3601) Iteration limit Quartus

I have created a Simulation of a 4 bit register in quartus. Each of the four D flip flops test fine by themselves, but when I test 4 of them connected together into a register, I get the "Error (...
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1answer
449 views

Set input low or high in Quartus

I have created a 4 bit register in VHDL, within Quartus. Normally, I connect each of my inputs to one of the dip switch pins or push button pins in the "pin planner" for my particular development ...
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1answer
141 views

Error (10327): VHDL error at clkdivider.vhd(27): can't determine definition of operator “”not“” — found 0 possible definitions

I am still a beginner and I keep getting this error, can anyone help pls? ...
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2answers
76 views

how to trigger another clk in mainclk (verilog)

I wrote somekind of prescaler in verilog to make sclk_adc signal from clk_i. by now my code looks like: always @(posedge clk_i) begin //generation of sclk_adc end ...
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1answer
293 views

VHDL Error 10481 : no primary unit

I'm designing a circuit using Simulink to VHDL generator to be burned into a FPGA. Simulink model works fine on Simulink, however, when I try to compile the VHDL code using Quartus II I get the ...
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198 views

VHDL to RTL/schematic, not what I expect to see

I'm teaching myself VHDL (using Altera Quartus Prime Web Edition) so we can incoroprate a CPLD into a design. I've only been doing it a few days but so far the VHDL itself seems reasonably ...
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1answer
56 views

register enable line usage in `case` block (verilog synthesis for altera cpld)

I have the following in a verilog design aimed at an altera CPLD (currently targeting EPM240, although the target device isn't set in stone): ...
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1answer
313 views

VHDL - Subtype or type has null range

What is the meaning of the following warning (raised by Quartus)? ...
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1answer
333 views

MAX10 .pof file issue, quartus II and usb blaster

After a MAX10 board revision. When programming the MAX10 with .pof, the MAX10 board do not start when power-on or after .pof programming is completed. However, normal operation is achieved when ...
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1answer
465 views

Is it possible to change the size and look of blocks/symbols in Quartus Schematic Editor

I want to change shapes of and resize blocks/symbols to make the schematic tidier. For example, I want to make my multiplexers the shape of a trapezoid (like commonly drawn on paper) and make them ...
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200 views

Weird quartus waveform diagram from JK flip flop schematic diagram

I tried building a JK flip flop from logic gates. This is my schematic design: However, my waveform for the case J=1, K=1 does not have the Q toggled. Instead, Qnot just copied completely CLK in that ...
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1answer
32 views

How to implement Quartus IP cores using ALMs?

This is a follow-up question on this, where I had asked about how one can implement multiplications without using any DSPs of the FPGA. Now, I would like to know whether one can implement Quartus IP ...
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1answer
238 views

Why is the CPU not able to proceed to the next instruction?

I am using Quartus II 14.0 to perform this activity. I have been trying to interface my CPU with an instruction memory module but I am not getting the correct response. The second instruction is not ...
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268 views

Can I connect all my components in my top level entity

I have finished writing a project with separate VHDL files. Most of the components have connections directly to the FPGA ( which I have instantiated and connected in the top level file) but a few do ...
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15 views

Rom.txt in quartus prime [duplicate]

What is rom.txt in quartus prime? What does it do? How do you change it and implement?I’m building a 8 bit alu. Thanks
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1answer
283 views

Avoid using DSPs in Quartus Prime

I like to implement a simple module without using any DSPs on the FPGA. In other words, I like the whole design to be implemented using logic. Is there an option in Quartus Prime that allows me to ...