Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Intel FPGA (formerly Altera).

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How do you select pin functions on an EPM7128 CPLD?

I have some old Altera MAX EPM7128SLC84-15N CPLDs kicking around that I want to use to interface with 5v TTL logic. If you look at the pinout, some of the pins have more than one function (eg. Pin 2 ...
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Interface VGA monitor with DE2-115 board and NIOSII processor

Currently, I'm working on a VGA part of my project. It's pretty simple, I want to interface with single pixels on the screen. I found a pdf, I will leave a link below, where it is explained step by ...
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28 views

How to use global clock in VHDL

I'm teaching myself CPLD programming using a development board with an Altera MAX II EPM240. After learning how to make a 4-bit digital counter in VHDL using clock/reset inputs, I'd like to use the ...
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Error while building project in Quartus with Eclipse tool

I'm pretty new to the forum so if something is wrong with the question, sorry in advance. Currently, I'm working on a free project for school. My teammates and I decided to make a 'drawing glove'. ...
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Interface mpu6050 with de2-115 board i2c

I'm currently working on a project for school. My teammates and I want to make a magic glove, that can draw on a VGA monitor with data from an accelerometer and gyrosensor. Therefore we are using a ...
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31 views

Connecting a signal to a pin in Quartus

I want to connect a signal in a .v file to a top level pin assigned in the pin planner but I've no idea where to start. I've looked at several guides but as a C programmer this is all quite alien to ...
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What is the easiest way to simulate and experiment with FPGA using simulated external DDR3?

For a computer architecture school project I have to implement an algorithm in verilog, such design have to input and output a VERY large ammount of data that wouldn't fit in on-chip memory, hence I ...
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What are <device_name>@<device_index> to quartus_pgm?

I am trying to download the firmware of a MAX 10 FPGA with the "examine" operation. The help for the command line interface quartus_pgm to Quartus Prime says ...
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56 views

How to prevent Quartus RTL Viewer from optimizing my Verilog code?

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Quartus synthesises memory in logic despite verilog synthesis attribute

I have the following read-only memory module: ...
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Verilog: Can't resolve multiple constant drivers for net

I am writing a code sung Quartus IDE: The following is my code: ...
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Multiplexer Simulation failed in Quartus II Web Edition 15.0

I'm currently working on some assignment for digital electronics. Before this, as in , before I reformat my laptop, everything works just fine. After that, After i reinstall Quartus II, the same ...
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Quartus produces different synthesis for same design

I synthesized my design in Quartus for Arria 10 in a remote server. In my memory instantiation, it is saying that it is unable to infer a Block RAM due to asynchronous reads. I tried to synthesize ...
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How to force arbitrary vector in Quartus II schematic editor?

So let's say I have a block in my schematic diagram which requires multi-bit input, and I want to drive it with arbitrary vector, say 0b0001 or 0b0000. For a single bit input, I would simply use VCC ...
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Is there a Quartus Signal Tap II equivalent for the Microsemi Libero SoC?

Quartus Signal Tap is extremely beneficial in debugging complex problems. However, there is no such toolset in the Microsemi Libero SmartDebug toolset. I would expect that Microsemi does provide ...
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Quartus II: USB Blaster not found, even after installing the driver

I've purchased this USB blaster: https://www.amazon.com/dp/B07F5H5LPZ/ Because I have this Ep2c5/ep2c8 dev board, I've been following this video to begin my work with FPGAs: https://www.youtube.com/...
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Why can't dual port RAM be read out using the Quartus In-System Memory Content Editor?

Here are the screen shots from Quartus; When I want to instantiate the single port RAM, I get option to assign an instance ID and thus read it using the ISMCE (In-System Memory Content Editor). ...
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62 views

How do I get started with my Cyclone IV EP4CE FPGA development board? (Assignment file) [closed]

I have bought a Cyclone IV FPGA development board on AliExpress. I have installed Quartus II 14.01 and I have a sample VHDL file but I do not know how to do the pin assignment without an assignment ...
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Pin assignments do not appear to be assigning in bdf - Quartus 17.1

Following the pin assignment diagram in the device manual for my Max 10 DE10-Lite, I assigned all the correct pins to their associated inputs and outputs as seen below: However, when I go back to my ...
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How can i export synthesized netlist from Quartus 2?

I need to get a netlist that creates by synthesis and optimization from different hdl languages in Quartus 2. I need a netlist in basic logic. Rtl viewer shows me something similar, but i need it in ...
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Quartus Prime Syntax Check Only

I have a variable in my code where I can change "modes". Some (timer and counter) values are reduced and I can run in Modelsim and enjoy the fast error checking. Currently, I need Signal Tap for real ...
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Cyclone IV FPGA: How to use nCSO pin (101) as normal I/O pin?

(I'm new to this -- so sorry if this is a dumb question). I've got a RZ-EasyFPGA dev board with a built in VGA port. I want mess around with generating a simple VGA signal. Dev board pin-out: I ...
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PIN Placement Errors In Quartus

So I am writing a simple blinking LED Verilog code that will be run on a Cyclone10 LP (Device is called 10CL025YU256I7G) and will be tested on a Cyclone 10 Evaluation Kit (6XX-44504R-0D) All code is ...
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45 views

Setting Pin Assignments For Quartus

So I have written a simple Verilog module which works well in the ModelSim emulator. I would like to now program my Cyclone 10 Dev board to perform this simple task, but I need to set up the pin ...
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52 views

Input CLK Keeps Showing As Hi-Z on ModelSim

I am writing some basic verilog code that blinks an LED at some frequency. The code for the design file is the following: ...
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65 views

I am not getting output I want in ModelSim - Altera (perhaps something related to timing requirements not being met?)

I am writing some basic verilog code that blinks an LED at some frequency. The code is the following: ...
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Quartus Prime design input/output array

I'm designing a decoder 3:8 and I would like to make an input/output array of it. How can I do it with the right sequence of ports?
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Problems with Memory Initialization in Quartus

I have the following code snippet in my VHDL code to initialize a ROM block: ...
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216 views

How I can resolve the problem of conversion (to_integer(unsigned(variable))

I want to solve a problem in VHDL with Quartus II. I made a model of VGA protocol 640/480. When I made the part of displaying I made one two signal in integer. Error (10621): VHDL Use Clause ...
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I want to find out how many Nios processors are on the board that I am linked with using JTAG, how to do this?

I just want to test how many Nios II exist inside the Qsys system and if they are in reset or executing code. Can this be done via the Nios II terminal?
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947 views

FPGA starts working after irrelevant changes, why?

I have written a UART module in Verilog. By using that module I get data from PC via UART and then send that data back again via this UART module. I uploaded it to FPGA for testing. It works flawless ...
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How to initialize/load Intel HBM memory in simulation

I am trying to simulate the Intel HBM example design using ModelSim. Is there a way to initialize/load the HBM memory with some data before the simulation? If so, how can we do it?
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What is purpose of the “assignments” in the Qsys custom component editor signals and interfaces tab?

Here is the image showing what I am talking about, For Avalon Memory Mapped Slave port I can see that there are 4 options already there and they are already assigned custom values. I just want to ...
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154 views

Why are VHDL “external names” that are used to create alias to signal at another level of hierarchy, not synthesizeable?

I am using Quartus 18.0 and have set the settings for VHDL-2008. However, when I try to compile a trivial project where one "external name" signal exists, I get this error: Error (10500): VHDL syntax ...
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Measuring the external memory power consumption in FPGAs?

I am trying to get a power/energy breakdown of DDR3 and core logic. I used Quartus power analyzer tool to get the power estimates, but I am not sure whether it includes the power consumption of ...
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787 views

How do D flip-flops (dff) start up in Quartus?

If I connect Q0 of one dff to its D0, its Q0 stays 0. But if I take another dff and connect its Q1 with Q0 of the first dff through OR to his D1, its Q1 stays 1. I understood that all registers are ...
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120 views

Is it possible to add an existing IP variant to a Platform Designer/Qsys system through TCL?

I have a .ip file that contains a parameterized component which I'd like to use in my Qsys system. I can add the component via the GUI but I would like to be able to add it via TCL or another ...
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237 views

How to assign different pins in Pin Planner in Quartus?

I am trying to make the 7 segment display of my FPGA work. I found some working code, but I got issues with the pin planner. The FPGA is this, a knockoff Altera Cyclone IV E EP4CE6E22C8. The code : <...
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210 views

Why is this VHDL pseudo random number generator not working as expected?

I'll start off by saying I have about 2 days experience in VHDL so there's a strong chance my code is horrible. I would appreciate any tips on better VHDL practice. I am busy trying to simulate a ...
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68 views

VHDL: case when using constants constructs

I'm having some trouble with the following statement ...
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Quartus Prime Lite: Generate a 25.18 MHz clock and Constrain to clock input in HDL

I am trying to use a generated clock in .sdc to drive my logic in my DE1-SoC Cyclone V chip. When I load the design onto the chip currently, nothing happens. My counter led does not even blink to show ...
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385 views

Error in simulating bdf with Waveform.vwf.vht, but bdf compiles successfully

I am trying to design an instruction register and controller for an ALU that I designed previously. I made the register with 2 muxes and 2 D flip-flops, and I made the controller with a T flip-flop ...
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162 views

Why is my seconds counter in verilog jumping values behaviour?

I am implementing a seconds counter on the Altera DE-1 Educational Board powered by the old Cyclone 2 FPGA. My plan is to make a 'down-clocker' that takes the on-board 50 MHz clock and produces a 1 Hz ...
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377 views

How to use tcl script to generate Qsys system inside Quartus?

When I change .vhd files I need to regenerate Qsys and then compile the design. How can I use tcl commands inside Quartus to regenerate the Qsys and then compile the project as well?​ Is there a way ...
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53 views

How can Qsys component configuration be accessed in software?

I'm designing a Qsys component which I want to be user-configurable. It has config parameters which are defined in the TCL file. For example, for a GPIO bank component I would write: ...
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132 views

Error (10536): VHDL Loop Statement error at InstructionMemory.vhd(31): loop must terminate within 10,000 iterations

Can someone help me solve this problem? Its my code below: ...
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108 views

PLL with input depend output CLK

Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed. In ...
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85 views

altera FPGA acting like OR gate when programed as AND gate

I'm new to altera fpga , I've bought development board based on EP4CE6E22 cyclon IV and tryed to program it with basic program in quartus environment ...
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Can't achieve requested … bandwidth type?

I have two cascaded PLLs in the design, and read here that it is the best to set first PLL into low bandwidth, and second PLL into high bandwidth in order to decrease jitter accumulation. I had "Auto" ...

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