Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Intel FPGA (formerly Altera).

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Reusing Quartus block schematic symbol file in another project

I am working on a Quartus project, requiring the usage of some designs previously created as block schematic design files in some other Quartus projects. I generated symbol files from the top design ...
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29 views

Avoiding node removal during optimization for preliminary estimation

I'm doing a preliminary FPGA design where I want to establish whether I will be able to implement the pinout and clock routing -- basically I'm placing all the hard IP blocks and wiring up the clocks, ...
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How does Quartus pin planner know about voltage in each I/O bank?

It is possible to specify a range of I/O standard options in Quartus pin planner. I am trying to understand a few things: How does Quartus know what voltage is supplied to each bank? Why does Quartus ...
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34 views

Quartus II - State Machine Viewer does't show all arrows/conditions?

As can be seen in the red circle, only arrows with condition a are shown, there is no !a condition at all. To replicate this ...
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23 views

I am getting the opposite result from simulation from Quartus in two cases, while the others are correct

I have created a Quartus schematics according to the following K-map; However, I am getting a wrong result; the output should be 1 when the input is 7 and 0 when 14, but it is going the opposite. The ...
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96 views

Quartus Prime Lite: Error (209053): Unexpected error in JTAG server — error code 35 and Error 202940 Can't access JTAG chain with SSH

Today I received a Terasic USB Blaster and I want to program an Altera 10M04SCE144C8G FPGA. I am using the Intel Quartus Prime 20.1.1 Lite Edition installed in Ubuntu 20.04. This FPGA has already been ...
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20 views

Multiple Avalon Data Master in Nios II Custom Instruction Crashes CPU

I am attempting to make a Nios II Custom Instruction which performs the function of summing a floating point array, given the array pointer and length. The custom instruction component has an Avalon ...
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30 views

Registered signal and Fmax in Timing Analyzer from Quartus II

I have the following module that is a simple register: ...
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85 views

How to view the internal signals of module in ModelSim using the testbench?

I have looked over this tutorial (Tutorial - Using Modelsim for Simulation, for Beginners. ) how to add waves and write test benches for VHDL module I looked over some answers as well like this one to ...
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23 views

Why I cannot edit waveform in ModelSim Intel?

I would like to create my own testbench for the code vhdl. I tried to use the edit function from ModelSim but it does show blank as you see on the picture. what could I have missed?
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24 views

typing error showing on quartus prime lite?

I am trying for few hours to understand why Quartus Prime Lite keep showing an error when I compile this basic VHDL code, I kept it like this to understand why it is showing an error just by typing!!!....
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How to implement a comparator logic gate in Quartus software? [closed]

Been trying for hours...How do I properly implement the following expressions: F0 = A0'A1'B0 + A0'B0B1 + A0B0'B1' + A1'B0B1 F1 = A1'B1 + A0'A1B1' + A0A1'B0' + A0B0'B1 + A1B0B1' I'm using NAND & ...
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35 views

Does Quartus support UVM in files with .sv extension?

I want to learn UVM later (i am starting with verilog first, systemverilog is next) but i have this doubt in my head, i have seem examples in the web but they use Modelsim, so my doubt is, if i make ...
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17 views

What is the proper method to become able to connect conduit signals inside Qsys?

Qsys (now known as Platform designer) identifies Avalon MM, Avalon ST, Clock, Reset and some other type of interfaces and makes it trivial to be able to connect them between different blocks. However, ...
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96 views

Help me debug these VHDL errors please

There are just 6 errors now Can't trace errors in this VHDL ...
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1answer
141 views

How to make a very large lookup table in Verilog?

I have a requirement to make a verilog module that takes a Gray code integer i and returns the Gray coded integer i-1 using combinatorial logic only. When I look up examples of Gray decoding, for ...
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37 views

Unable to generate device simulation libraries from Quartus Prime

I am using Quartus 18.1. I am trying to generate device simulation libraries as per the procedure here: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/...
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Quartus Minimum Propagation Delay Report doesn't show up

Does anyone have any idea why minimum propagation delay report doesn't show up after compilation? It doesn't happen in every project, sometimes it's included in compilation report sometimes not. This ...
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29 views

What does “database” do in Quartus?

Quartus has settings to export/import database under the project drop-down box. The project directory contains two folders named db and incremental_db. What is this "database" and what does ...
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112 views

Output waveform of TCS3200

I am trying to use TCS3200 color sensor for my project with De0 nano FPGA board. The output of TCS3200 is a square waveform and i am confused how to use that waveform for a particular task. I searched ...
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39 views

why the D-FF does not use the clock assigned by me Quartus schematic

The schematic given above is a simplified version of a design. But this is enough to explain my problem. As you can see from the schematic, clock signal of second dff is connected to (Q0' & clk). ...
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2answers
143 views

UART receiving random values

I tried to transmit "S" using De0 nano FPGA board and UART over USB module . The problem is i am not receiving "s" constantly . I am using the software Called Hterm to see ...
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10 views

Can Quartus help the user find out power saving if one uses clock control block to disable clock?

The clock control block can be used to disable clock to a section of the design thereby achieving clock gating. Can Quartus help the user find out how much saving such a measure will help achieve in ...
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23 views

How to let Quartus generate VHDL out of Qsys automatically

I was wondering how I can get Quartus to automatically generate VHDL IP from Qsys files, instead of the default Verilog. I know I can change this in the command line or Platform Designer GUI for each ...
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89 views

problem in adding IP to platform designer

I'm new to platform designer and I want to add an ALT PLL intel FPGA IP to a platfrom designer project but after opening Mega wizard plugin manager and setting up the requirements, IP does not add to ...
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35 views

Pin Assignments for DE5-Net

I am porting a working sequential circuit from a DE0-Nano to a DE5-Net. The circuit is driven by one global 50 MHz clock signal. The circuit only has one input and one output port for serial ...
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89 views

Possible to use Segger J-Link with Intel Quartus to flash FPGA?

Does anybody know if it's possible to use a Segger J-Link with Intel Quartus to flash an FPGA?
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122 views

Long enumeration in VHDL to recognize a state machine

In order that Quartus II recognizes a state machine in a case / when statement the case must be applied on an enumerated type. In my code I am using a case on integer number going from 0 to 230. And ...
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1answer
417 views

3 digit BCD Counter in VHDL and Quartus II

I'm trying to make a 3 digits BCD counter in VHDL for Cyclone V FPGA from intel. I have an module-k counter design and I instantiate four counters in top level module (structural design): One counter ...
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37 views

How can Quartus Prime System Console be used to read/write a whole file?

I want to find a way to read/write whole file from/to my Intel FPGA design. The file being written provides data to be processed and the file being read shall contain the results of the processing ...
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96 views

VHDL Integer Range Output Bus Width

I'm currently working on writing a simple counter in VHDL, trying to genericize it as much as possible. Ideally I end up with a counter that can pause, count up/down, and take just two integer (min, ...
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79 views

Difference in SystemVerilog-2005 HDL simulation behavior between Quartus Prime Lite (20.1) and ModelSim-Intel Starter Edition(2020.1)

A SystemVerilog module using an always@ block with a gated trigger does not compile in Quartus Prime Lite (20.1). Quartus Prime reports the following compiler error message: Error (10170): Verilog ...
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92 views

I'm getting this error over and over and I don't know how to fix it . Error (12002): Port “S[0]” does not exist in macrofunction “inst8”

I'm working in Quartus 2, trying to use a busmux to select the what to do, but when I click compile I just get this error:
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1answer
80 views

My RTL viewer replaces NAND gates with AND gates with the inversion bubbles

I want it to show this MUX only with 3 NAND gates and an Inverter. so, I specified NAND gate in the verilog HDL code, but it keeps replacing it with AND gates with inversion bubbles without having a ...
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4answers
2k views

Is using floor plan tool during FPGA design ever actually useful or required?

I have used Intel Quartus and Microsemi Libero. Both of these tools contain a method whereby we are able to view the floorplan of the FPGA, hover the mouse around to see what parts of netlist have ...
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Why do FPGA projects always take the same amount of time to compile?

With software, when we compile the project for first time it may take a while but afterwards, it does not take so long anymore. If we change a single file in the project, everything does not need to ...
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18 views

Testbench for RTL and GLS simulation

I want to do the GLS simulation after the RTL simulation. I was asked to add uut : entity work.eq3(structure) instead of the one specified below used for RTL <...
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2answers
120 views

Interface to numpad in VHDL. Numlock button support

I need to implement interface to numpad in keyboard. I am totally newbie in Quartus and VHDL language. I only know that the decoder should return the appropriate key depending on the entered row and ...
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8 views

How exactly does the AvalonMM interconnect work using all the pieces that it has?

When looking into the "memory-mapped interconnect" in Qsys for my system, I can see many components that are inserted by Qsys when the system is generated. These are all part of the Qsys ...
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12 views

Is it possible to limit the address space accessed by a master using the Avalon-Memory Mapped bus?

Provided that a slave is shared by multiple masters which connect to the same slave's Avalon-MM slave port in Qsys, is there a way to control the read/write access to certain address locations inside ...
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33 views

Is there a standard way to extract the base addresses in Qsys SOPC info file into a VHDL file?

For an FGPA fabric AvalonMM master, it is very important that the base addresses be correctly defined in a HDL source file so it can make use of them. The base addresses can change easily as we make ...
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1answer
104 views

How do you select pin functions on an EPM7128 CPLD?

I have some old Altera MAX EPM7128SLC84-15N CPLDs kicking around that I want to use to interface with 5v TTL logic. If you look at the pinout, some of the pins have more than one function (eg. Pin 2 ...
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1answer
129 views

How to use global clock in VHDL

I'm teaching myself CPLD programming using a development board with an Altera MAX II EPM240. After learning how to make a 4-bit digital counter in VHDL using clock/reset inputs, I'd like to use the ...
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1answer
38 views

Connecting a signal to a pin in Quartus

I want to connect a signal in a .v file to a top level pin assigned in the pin planner but I've no idea where to start. I've looked at several guides but as a C programmer this is all quite alien to ...
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1answer
135 views

How to prevent Quartus RTL Viewer from optimizing my Verilog code?

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1answer
51 views

Quartus synthesises memory in logic despite verilog synthesis attribute

I have the following read-only memory module: ...
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181 views

Verilog: Can't resolve multiple constant drivers for net

I am writing a code sung Quartus IDE: The following is my code: ...
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57 views

Quartus produces different synthesis for same design

I synthesized my design in Quartus for Arria 10 in a remote server. In my memory instantiation, it is saying that it is unable to infer a Block RAM due to asynchronous reads. I tried to synthesize ...
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65 views

Is there a Quartus Signal Tap II equivalent for the Microsemi Libero SoC?

Quartus Signal Tap is extremely beneficial in debugging complex problems. However, there is no such toolset in the Microsemi Libero SmartDebug toolset. I would expect that Microsemi does provide ...
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2answers
2k views

Quartus II: USB Blaster not found, even after installing the driver

I've purchased this USB blaster: https://www.amazon.com/dp/B07F5H5LPZ/ Because I have this Ep2c5/ep2c8 dev board, I've been following this video to begin my work with FPGAs: https://www.youtube.com/...

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