Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Intel FPGA (formerly Altera).

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42 views

problem in adding IP to platform designer

I'm new to platform designer and I want to add an ALT PLL intel FPGA IP to a platfrom designer project but after opening Mega wizard plugin manager and setting up the requirements, IP does not add to ...
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Why the output return UUUU when i assign subtraction operation to inputs? How to solve it?

My professor want my class to make a project that could find greates common divisor using a few entities, one of them is the code below. But, it could not return output that is xout <= x - y or ...
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30 views

Pin Assignments for DE5-Net

I am porting a working sequential circuit from a DE0-Nano to a DE5-Net. The circuit is driven by one global 50 MHz clock signal. The circuit only has one input and one output port for serial ...
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Possible to use Segger J-Link with Intel Quartus to flash FPGA?

Does anybody know if it's possible to use a Segger J-Link with Intel Quartus to flash an FPGA?
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1answer
103 views

Long enumeration in VHDL to recognize a state machine

In order that Quartus II recognizes a state machine in a case / when statement the case must be applied on an enumerated type. In my code I am using a case on integer number going from 0 to 230. And ...
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1answer
76 views

3 digit BCD Counter in VHDL and Quartus II

I'm trying to make a 3 digits BCD counter in VHDL for Cyclone V FPGA from intel. I have an module-k counter design and I instantiate four counters in top level module (structural design): One counter ...
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17 views

How can Quartus Prime System Console be used to read/write a whole file?

I want to find a way to read/write whole file from/to my Intel FPGA design. The file being written provides data to be processed and the file being read shall contain the results of the processing ...
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33 views

VHDL Integer Range Output Bus Width

I'm currently working on writing a simple counter in VHDL, trying to genericize it as much as possible. Ideally I end up with a counter that can pause, count up/down, and take just two integer (min, ...
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Difference in SystemVerilog-2005 HDL simulation behavior between Quartus Prime Lite (20.1) and ModelSim-Intel Starter Edition(2020.1)

A SystemVerilog module using an always@ block with a gated trigger does not compile in Quartus Prime Lite (20.1). Quartus Prime reports the following compiler error message: Error (10170): Verilog ...
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41 views

I'm getting this error over and over and I don't know how to fix it . Error (12002): Port “S[0]” does not exist in macrofunction “inst8”

I'm working in Quartus 2, trying to use a busmux to select the what to do, but when I click compile I just get this error:
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Is using floor plan tool during FPGA design ever actually useful or required?

I have used Intel Quartus and Microsemi Libero. Both of these tools contain a method whereby we are able to view the floorplan of the FPGA, hover the mouse around to see what parts of netlist have ...
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Why do FPGA projects always take the same amount of time to compile?

With software, when we compile the project for first time it may take a while but afterwards, it does not take so long anymore. If we change a single file in the project, everything does not need to ...
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Testbench for RTL and GLS simulation

I want to do the GLS simulation after the RTL simulation. I was asked to add uut : entity work.eq3(structure) instead of the one specified below used for RTL <...
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Interface to numpad in VHDL. Numlock button support

I need to implement interface to numpad in keyboard. I am totally newbie in Quartus and VHDL language. I only know that the decoder should return the appropriate key depending on the entered row and ...
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How exactly does the AvalonMM interconnect work using all the pieces that it has?

When looking into the "memory-mapped interconnect" in Qsys for my system, I can see many components that are inserted by Qsys when the system is generated. These are all part of the Qsys ...
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Is it possible to limit the address space accessed by a master using the Avalon-Memory Mapped bus?

Provided that a slave is shared by multiple masters which connect to the same slave's Avalon-MM slave port in Qsys, is there a way to control the read/write access to certain address locations inside ...
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Is there a standard way to extract the base addresses in Qsys SOPC info file into a VHDL file?

For an FGPA fabric AvalonMM master, it is very important that the base addresses be correctly defined in a HDL source file so it can make use of them. The base addresses can change easily as we make ...
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1answer
64 views

How do you select pin functions on an EPM7128 CPLD?

I have some old Altera MAX EPM7128SLC84-15N CPLDs kicking around that I want to use to interface with 5v TTL logic. If you look at the pinout, some of the pins have more than one function (eg. Pin 2 ...
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51 views

How to use global clock in VHDL

I'm teaching myself CPLD programming using a development board with an Altera MAX II EPM240. After learning how to make a 4-bit digital counter in VHDL using clock/reset inputs, I'd like to use the ...
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Error while building project in Quartus with Eclipse tool

I'm pretty new to the forum so if something is wrong with the question, sorry in advance. Currently, I'm working on a free project for school. My teammates and I decided to make a 'drawing glove'. ...
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Interface mpu6050 with de2-115 board i2c

I'm currently working on a project for school. My teammates and I want to make a magic glove, that can draw on a VGA monitor with data from an accelerometer and gyrosensor. Therefore we are using a ...
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35 views

Connecting a signal to a pin in Quartus

I want to connect a signal in a .v file to a top level pin assigned in the pin planner but I've no idea where to start. I've looked at several guides but as a C programmer this is all quite alien to ...
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What is the easiest way to simulate and experiment with FPGA using simulated external DDR3?

For a computer architecture school project I have to implement an algorithm in verilog, such design have to input and output a VERY large ammount of data that wouldn't fit in on-chip memory, hence I ...
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68 views

What are <device_name>@<device_index> to quartus_pgm?

I am trying to download the firmware of a MAX 10 FPGA with the "examine" operation. The help for the command line interface quartus_pgm to Quartus Prime says ...
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99 views

How to prevent Quartus RTL Viewer from optimizing my Verilog code?

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1answer
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Quartus synthesises memory in logic despite verilog synthesis attribute

I have the following read-only memory module: ...
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Verilog: Can't resolve multiple constant drivers for net

I am writing a code sung Quartus IDE: The following is my code: ...
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Multiplexer Simulation failed in Quartus II Web Edition 15.0

I'm currently working on some assignment for digital electronics. Before this, as in , before I reformat my laptop, everything works just fine. After that, After i reinstall Quartus II, the same ...
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Quartus produces different synthesis for same design

I synthesized my design in Quartus for Arria 10 in a remote server. In my memory instantiation, it is saying that it is unable to infer a Block RAM due to asynchronous reads. I tried to synthesize ...
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How to force arbitrary vector in Quartus II schematic editor?

So let's say I have a block in my schematic diagram which requires multi-bit input, and I want to drive it with arbitrary vector, say 0b0001 or 0b0000. For a single bit input, I would simply use VCC ...
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36 views

Is there a Quartus Signal Tap II equivalent for the Microsemi Libero SoC?

Quartus Signal Tap is extremely beneficial in debugging complex problems. However, there is no such toolset in the Microsemi Libero SmartDebug toolset. I would expect that Microsemi does provide ...
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558 views

Quartus II: USB Blaster not found, even after installing the driver

I've purchased this USB blaster: https://www.amazon.com/dp/B07F5H5LPZ/ Because I have this Ep2c5/ep2c8 dev board, I've been following this video to begin my work with FPGAs: https://www.youtube.com/...
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Why can't dual port RAM be read out using the Quartus In-System Memory Content Editor?

Here are the screen shots from Quartus; When I want to instantiate the single port RAM, I get option to assign an instance ID and thus read it using the ISMCE (In-System Memory Content Editor). ...
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How do I get started with my Cyclone IV EP4CE FPGA development board? (Assignment file) [closed]

I have bought a Cyclone IV FPGA development board on AliExpress. I have installed Quartus II 14.01 and I have a sample VHDL file but I do not know how to do the pin assignment without an assignment ...
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Pin assignments do not appear to be assigning in bdf - Quartus 17.1

Following the pin assignment diagram in the device manual for my Max 10 DE10-Lite, I assigned all the correct pins to their associated inputs and outputs as seen below: However, when I go back to my ...
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How can i export synthesized netlist from Quartus 2?

I need to get a netlist that creates by synthesis and optimization from different hdl languages in Quartus 2. I need a netlist in basic logic. Rtl viewer shows me something similar, but i need it in ...
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Quartus Prime Syntax Check Only

I have a variable in my code where I can change "modes". Some (timer and counter) values are reduced and I can run in Modelsim and enjoy the fast error checking. Currently, I need Signal Tap for real ...
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139 views

Cyclone IV FPGA: How to use nCSO pin (101) as normal I/O pin?

(I'm new to this -- so sorry if this is a dumb question). I've got a RZ-EasyFPGA dev board with a built in VGA port. I want mess around with generating a simple VGA signal. Dev board pin-out: I ...
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103 views

PIN Placement Errors In Quartus

So I am writing a simple blinking LED Verilog code that will be run on a Cyclone10 LP (Device is called 10CL025YU256I7G) and will be tested on a Cyclone 10 Evaluation Kit (6XX-44504R-0D) All code is ...
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54 views

Setting Pin Assignments For Quartus

So I have written a simple Verilog module which works well in the ModelSim emulator. I would like to now program my Cyclone 10 Dev board to perform this simple task, but I need to set up the pin ...
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71 views

Input CLK Keeps Showing As Hi-Z on ModelSim

I am writing some basic verilog code that blinks an LED at some frequency. The code for the design file is the following: ...
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1answer
105 views

I am not getting output I want in ModelSim - Altera (perhaps something related to timing requirements not being met?)

I am writing some basic verilog code that blinks an LED at some frequency. The code is the following: ...
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122 views

Problems with Memory Initialization in Quartus

I have the following code snippet in my VHDL code to initialize a ROM block: ...
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765 views

How I can resolve the problem of conversion (to_integer(unsigned(variable))

I want to solve a problem in VHDL with Quartus II. I made a model of VGA protocol 640/480. When I made the part of displaying I made one two signal in integer. Error (10621): VHDL Use Clause ...
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35 views

I want to find out how many Nios processors are on the board that I am linked with using JTAG, how to do this?

I just want to test how many Nios II exist inside the Qsys system and if they are in reset or executing code. Can this be done via the Nios II terminal?
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970 views

FPGA starts working after irrelevant changes, why?

I have written a UART module in Verilog. By using that module I get data from PC via UART and then send that data back again via this UART module. I uploaded it to FPGA for testing. It works flawless ...
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What is purpose of the “assignments” in the Qsys custom component editor signals and interfaces tab?

Here is the image showing what I am talking about, For Avalon Memory Mapped Slave port I can see that there are 4 options already there and they are already assigned custom values. I just want to ...
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268 views

Why are VHDL “external names” that are used to create alias to signal at another level of hierarchy, not synthesizeable?

I am using Quartus 18.0 and have set the settings for VHDL-2008. However, when I try to compile a trivial project where one "external name" signal exists, I get this error: Error (10500): VHDL syntax ...
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Measuring the external memory power consumption in FPGAs?

I am trying to get a power/energy breakdown of DDR3 and core logic. I used Quartus power analyzer tool to get the power estimates, but I am not sure whether it includes the power consumption of ...

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