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Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Intel FPGA (formerly Altera).

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32 bit Multiplication synthesis in Quartus in VHDL on cyclone V FPGA

I encountered a strange behavior while simulating my ALU. I designed a 32-bit ALU in VHDL to perform addition, subtraction, multiplication, division, OR, AND, and XOR operations. During simulation, ...
UserHomeInit's user avatar
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What is the purpose of monitor BFMs in Quartus Prime Platform Designer Simulation models?

Here is screenshot from Quartus Prime Platform Designer showing the Verification Components. I understand the master/slave and source/sink. I have used them in the past long ago. What I don't ...
quantum231's user avatar
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Quartus: too long compilation time problem - Stratix 10

I have a big design the suffering from very long compilation times, The time is about 7hours to 8hours. I would like to know if its normal according to the following details: FPGA Device: Intel ...
Michael Rahav's user avatar
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(Verilog) Why $signed() and >>> operation cannot generate ASR when inside ?: operator in such case?

Here is the module, I want to use signext to determine whether it is ASR or LSR. ...
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SDRAM connection to Nios2 on DE10-Nano

I am pretty new to fpga world and trying to do an image processing application using Nios2 processor on a DE10-Nano dev board for university and I'm using the platform designer from Quartus. The goal ...
Mag's user avatar
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Packaging synthesized design as netlist for use in future designs

I am attempting to create a synthesized netlist of an FSM to help decrease my synthesis time, but I've been unable to get Quartus to generate the correct output files or even find any resources on ...
John B's user avatar
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How to properly constrain this hold time?

I am puzzled, can't get to any seemingly simple and, what's more important, solution looking correctly. There's a main fast clock, fclk, and I divide it by 4, ...
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2 votes
4 answers
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Is there any way to know how real discrete components are being connected to each other using logical gates?

Let's say we created some gates or something with VHDL. How can I convert that code into those diagrams that show how discrete components (such as transistors and resistors) are connected to each ...
dsa's user avatar
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Does this Verilog HDL code of a decoder look strange in any way?

I am wondering if it is ok to use output instead of wire for another output in Verilog coding (using Quartus for this). Just ...
towel Lijiang's user avatar
1 vote
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207 views

How to obtain the counting of TTL pulses from an FPGA?

I'm currently working on a project in which I need to program an FPGA in order to connect it to a photon detector, that generates a TTL pulse when detecting a photon; I need to count this pulses, ...
Jorsa's user avatar
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How to make a waveform simulation in Quartus II from testbench module

I wrote a Verilog gate-level description and a testbench for these requirements. However, I don't know how to make a waveform simulation in Quartus II. How can I make the waveform simulation to get ...
South goodman's user avatar
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SDC constraints at the module level

Must be simple question I can't find answer for. I design Synposys design constraints file, and have a module, let's call it module1. A the top I connect it using ...
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Choose the right strategy to divide two values [closed]

Info: After getting some comments and already one answer, I decided to rewrite this question to better fit into this site. I had a problem where I needed to downsize a 12 bit value to an 8 bit value. ...
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Calculating timing constraings for interfacing with sdram

I want to set the set_input_delay and set_output_delay constraints for my design but I'm having trouble to find the values to calculate them. My understanding so far: To calculate the set_output_delay ...
TimSch's user avatar
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Discrepancy between simulation results and RTL viewer in Quartus II 18.0 for my Verilog code

Here's the Verilog code for my UsedBeforeAssign module: ...
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Confusion about Synthesis Results of Verilog Code: DATAIN has no connection

I am quite puzzled about the synthesis results of the following code. Here is the code: ...
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Intel DCFIFO IP crashing when using a clock with decimal place

I need to build a FIFO with a 96 MHz write clock and a 25.175 MHz read clock. The data are read from an SDRAM and are fed into the VGA output. To do that I use the intel DCFIFO IP and PLL IP. The PLL ...
TimSch's user avatar
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Reading Incorrect Values from Flip Flops in Non-FIFO Queue Implementation

I am working on a non-FIFO queue design using flip flops to store data elements. During testing, I encountered an issue where reading the value from a flip flop after storing a new value in another ...
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Verilog, Question about 'include'

I'm trying to learn how to use the 'include thing properly. I had this basic code that works fine to run some 7 segment displays. ...
Alex Kibbe's user avatar
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1 answer
739 views

Error while trying to bind SystemVerilog module with properties module

I have a SystemVerilog module that I want to test using assertions. For simplicity let's say the DUT is this: ...
Kyriafinis Vasilis's user avatar
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51 views

SDRAM Voltage and pin planner consequences

I have this SDRAM module: According to the docs: am I right that it's the 3,3V version? If yes: what are the consequences of that fact using the Pin Planner? Is it correct that I have to set the I/O ...
TimSch's user avatar
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How can I circumvent wiring all inputs to ports in Quartus 2 schematic block diagram?

I am trying to create a 32-bit adder in Quartus 2 block diagram by stringing 2 12-bit adders and an 8-bit one together. I have created the symbols (components) for the smaller adders already. I ...
Amir Kooshky's user avatar
4 votes
1 answer
147 views

Debuging verilog SDRAM controller

I've been working on a project that involves the creation of a SDRAM Controller in verilog for an Altera DE2 prototyping board. Despite reading the documentation for the memory chip on the board, ...
bieux's user avatar
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2 answers
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How to give an input stimulus to the DUT in a testbench when we have a 10-bit input?

How do you get around this problem? I am spending a lot of time in giving a 10-bit input all the way from 1111111111 to 0000000000. How do I effectively write loops in my testbench when I am giving an ...
EngineeringStudent's user avatar
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JK flip-flop simulation

I'm trying to simulate JK flip-flop behavior. Everything seems to be working perfectly except that the Q output is not toggling, but Q̅ does when both J and K are up. My circuit: The result of the ...
Hibou's user avatar
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Constraining FPGA design on the lower level module

I have design consisting of several interconnected modules. The TimeQuest complains about timing violations, and it is correct in its complaints. The paths it highlights must be out of the ...
Anonymous's user avatar
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2 votes
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Problem in programming ALTERA MAX 7000S CPLD with homemade Byte Blaster

I am trying to read back an ALTERA MAX 7000S CPLD (EPM7064SLC84-10) mounted on a board (a part of the board's schematic is shown below) and copy it on another CPLD. In the schematic, X4 is a male 10 ...
pooya's user avatar
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2 answers
366 views

What does ' #period ' mean in Verilog code?

What does #period indicate or mean in Verilog in general terms? I have posted the image just as an example.
Aneesh's user avatar
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Need some help with my Quartus code since it is not showing my waveform correctly because of an error

I need some help regarding some of my Quartus II work. This is the problem I have to solve. This my code for the 7 segment display and the multiplexer. I believe it is correct: ...
Minseok Park's user avatar
1 vote
1 answer
1k views

Error (209025): Can't recognize silicon ID for device 1

I migrated project from DE0-Nano to custom board with Altera Cyclone IV EP4CE22E22 (TQFP-144). I don't know if I migrated it correctly since I am not the author of the project and it's first project ...
Jirka Picek's user avatar
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240 views

FPGA I2C master not working

I have written an I2C master for the DE10-Nano FPGA which is meant to communicate with the SSD1306 OLED display driver. The issue I'm having is that it simply is not working when I actually test it on ...
IanRider's user avatar
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168 views

Is there a tool or method to list signals that have no reset in the HDL design for an FPGA?

I have to reuse an old VHDL draft design which was not fully verified and validated. The code is huge - it takes around 30k slices to be implemented on an FPGA. I see that some signals are forgotten ...
dsp_curious's user avatar
-1 votes
1 answer
990 views

Is it possible to display a custom error message in Synplify syntezis with SystemVerilog code?

I write some library module on SystemVerilog. I want to check input parameters on synthesis and then if their values are wrong I want to stop synthesis with a custom error that will tell which ...
Arseniy's user avatar
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1 vote
0 answers
191 views

ModelSim can not simulate my VHDL code

I am learning to program FPGAs and my code is compiled in Quartus prime but my .do file does not simulate in ModelSim. Any help is appreciated. ...
koushiksk's user avatar
4 votes
3 answers
1k views

Quartus Can't fit design into Device, is there any way to optimize it to get it to fit?

I have a module that takes in a sample, puts it in a large buffer, and sums the buffer. When it synthesizes, Quartus says it requires too many combinational nodes. I tried many things to see what ...
user2704336's user avatar
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1 answer
656 views

Change clock frequency from 50MHz to 40MHz using Altera Cyclone IV and Quartus Lite 20.1

I'm using the FPGA board EasyFPGAv2.2 which have Altera Cyclone IV with chip EP4CE6E22C6 and I made a verilog program to generate VGA 640x480 60Hz signal. It works great dividing 50MHz by 2 generating ...
Yury Euceda's user avatar
1 vote
1 answer
408 views

How can one pass values to a bus in Verilog without first making a wrapper bus?

I have just defined an SR flip flop, and I need to now define a D flip flop. I am going about this by using an SR flip flop within my D flip flop. However, because I used a bus for my S and R inputs ...
Papu's user avatar
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1 vote
1 answer
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SystemVerilog output issue with "m" in a 5-to-1 Mux

I'm having an issue that I can't resolve on my own. I nested a 2-to-1 mux module inside of this 5-to-1, and no errors occur. Yet my output "m" will only ...
Karl.52's user avatar
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3 votes
1 answer
333 views

How to make a D flip flop circuit that pulses 4 times per switch toggle?

For a school project we must design an ALU and its control circuit (see schematic). As part of the controller, we must make a circuit that clocks our registers (one is PISO, the other SIPO). The ...
Nick Lybarger's user avatar
1 vote
0 answers
819 views

Quartus keeps closing on me

Every time I create a new project quartus just closes on me. no error message no new window somewhere else it just closes. It makes the new project, and I can restart the program and work on the ...
Michael Hiltz's user avatar
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1 answer
492 views

Syntax Help: VHDL Syntax Error at *.vhd near text ["process", "behave"] expecting "if"

Problem I'm developing a simple LED blinking system in Quartus Prime Lite 18.1 to be instantiated on a DE0-Nano development board that makes use of the Cyclone IV E generation of Intel FPGAs. To do so ...
Mark Musil's user avatar
2 votes
1 answer
316 views

Why is the number of instances shown in the RTL viewer and technology map (post-fit) different in Quartus Prime Lite?

I am a beginner in using FPGA and Quartus Prime Lite. I created a 32-bit adder using four 8-bit adders. These 8-bit adders were created using eight full adders. I did the design using schematic .BDF ...
kalana sanhinda jayalath's user avatar
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2k views

How to open pin planner in Xilinx Vivado?

I am an Intel Quartus user getting to know Xilinx Vivado. I am using Xilinx Vivado for the first time. I am using Digilent ARTY S-7 FPGA board for learning purpose. I am have created a blinking LED ...
quantum231's user avatar
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1 answer
228 views

Build on-chip ROM in HDL

I wrote the next code in quartus 15.0, where I show what I want to do for a specific project. I can write it both in VHDL and Verilog HDL, but verilog is notoriously shorter. ...
emma97's user avatar
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JTAG Communication Failure in ARRIA 10 FPGA

Has anyone bricked an ARRIA 10 FGPA (or any FPGA) and successfully unbricked it? I have an ARRIA 10 that uses an EPCQ-L256 external memory to configure the FPGA. When I uploaded some code, I think I ...
Aaron's user avatar
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1 vote
1 answer
1k views

I'm trying to build a 16-bit adder in Verilog but my output and carryout always have a value of X

...
RiceBoy25's user avatar
1 vote
0 answers
130 views

7-segment display communication

I have attempted to solve this problem making kmaps for the binary counter, mux and decoder however I'm getting stuck on the making them all talk to each other bit, I am using a ATmega32L and a ...
Desired's user avatar
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1 answer
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What does 1'h1 mean in the RTL viewer diagram

Just new to Quartus, from my understanding 1'b1 basically means 1 as input, but why it shows 1'h1 on the diagram instead of 1'b1 or just 1?
GotYaLoot's user avatar
1 vote
1 answer
439 views

Why is my code output always showing 0?

This is a 4 bit counter code written using Verilog HDL on Quartus. Can somebody explain why is my output o always showing 0? Code in Text : ...
Akib Ahmed Ishan's user avatar
1 vote
1 answer
496 views

What does symbol width and "beat" mean for Avalon-ST interface?

This is the GUI for the Avalon-ST Source BFM found in Quartus Platform Designer. I am trying to understand, what is the meaning of Symbol width and "beat" for streaming interface? The ...
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