Questions tagged [quartus]
Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Intel FPGA (formerly Altera).
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Calculating timing constraings for interfacing with sdram
I want to set the set_input_delay and set_output_delay constraints for my design but I'm having trouble to find the values to calculate them.
My understanding so far:
To calculate the set_output_delay ...
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Discrepancy between simulation results and RTL viewer in Quartus II 18.0 for my Verilog code
Here's the Verilog code for my UsedBeforeAssign module:
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Confusion about Synthesis Results of Verilog Code: DATAIN has no connection
I am quite puzzled about the synthesis results of the following code.
Here is the code:
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Intel DCFIFO IP crashing when using a clock with decimal place
I need to build a FIFO with a 96 MHz write clock and a 25.175 MHz read clock.
The data are read from an SDRAM and are fed into the VGA output.
To do that I use the intel DCFIFO IP and PLL IP. The PLL ...
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Reading Incorrect Values from Flip Flops in Non-FIFO Queue Implementation
I am working on a non-FIFO queue design using flip flops to store data elements. During testing, I encountered an issue where reading the value from a flip flop after storing a new value in another ...
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Crossbar switch IP Core help [closed]
I'm newbie on Quartus Prime Lite.
I need to implement an very big crossbar with 96 inputs and outputs where we have a control signal in the standard format of an multiplexer and an demultiplexer (2 ...
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Verilog, Question about 'include'
I'm trying to learn how to use the 'include thing properly. I had this basic code that works fine to run some 7 segment displays.
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Error while trying to bind SystemVerilog module with properties module
I have a SystemVerilog module that I want to test using assertions. For simplicity let's say the DUT is this:
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How do you create a Platform Designer component with a parameterisable number of Avalon ST Ports?
I want to create a Platform Designer (PD) component that has a parameter which controls the number of Avalon ST ports (sinks and sources). I cannot find any documentation that explains what the HDL or ...
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SDRAM Voltage and pin planner consequences
I have this SDRAM module:
According to the docs: am I right that it's the 3,3V version?
If yes: what are the consequences of that fact using the Pin Planner?
Is it correct that I have to set the I/O ...
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How can I circumvent wiring all inputs to ports in Quartus 2 schematic block diagram?
I am trying to create a 32-bit adder in Quartus 2 block diagram by stringing 2 12-bit adders and an 8-bit one together. I have created the symbols (components) for the smaller adders already.
I ...
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Debuging verilog SDRAM controller
I've been working on a project that involves the creation of a SDRAM Controller in verilog for an Altera DE2 prototyping board. Despite reading the documentation for the memory chip on the board, ...
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How to give an input stimulus to the DUT in a testbench when we have a 10-bit input?
How do you get around this problem?
I am spending a lot of time in giving a 10-bit input all the way from 1111111111 to 0000000000.
How do I effectively write loops in my testbench when I am giving an ...
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JK flip-flop simulation
I'm trying to simulate JK flip-flop behavior. Everything seems to be working perfectly except that the Q output is not toggling, but Q̅ does when both J and K are up.
My circuit:
The result of the ...
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Constraining bidir pin can't clear setup violation
The design based on Cyclone 3 and works with its serial configuration device. The pins are declared as:
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Constraining FPGA design on the lower level module
I have design consisting of several interconnected modules. The TimeQuest complains about timing violations, and it is correct in its complaints. The paths it highlights must be out of the ...
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Problem in programming ALTERA MAX 7000S CPLD with homemade Byte Blaster
I am trying to read back an ALTERA MAX 7000S CPLD (EPM7064SLC84-10) mounted on a board (a part of the board's schematic is shown below) and copy it on another CPLD.
In the schematic, X4 is a male 10 ...
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What does ' #period ' mean in Verilog code?
What does #period indicate or mean in Verilog in general terms? I have posted the image just as an example.
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Quartus II 64 bit assignment editor is causing strange error
I found this error not only from my circuit also various student's circuit.
So I selected pins and whenever I added,
Quartus just combine those names with ;. Is there any way that solve this error?
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Need some help with my Quartus code since it is not showing my waveform correctly because of an error
I need some help regarding some of my Quartus II work.
This is the problem I have to solve.
This my code for the 7 segment display and the multiplexer. I believe it is correct:
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Error (209025): Can't recognize silicon ID for device 1
I migrated project from DE0-Nano to custom board with Altera Cyclone IV EP4CE22E22 (TQFP-144). I don't know if I migrated it correctly since I am not the author of the project and it's first project ...
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FPGA I2C master not working
I have written an I2C master for the DE10-Nano FPGA which is meant to communicate with the SSD1306 OLED display driver.
The issue I'm having is that it simply is not working when I actually test it on ...
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Is there a tool or method to list signals that have no reset in the HDL design for an FPGA?
I have to reuse an old VHDL draft design which was not fully verified and validated.
The code is huge - it takes around 30k slices to be implemented on an FPGA. I see that some signals are forgotten ...
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Is it possible to display a custom error message in Synplify syntezis with SystemVerilog code?
I write some library module on SystemVerilog. I want to check input parameters on synthesis and then if their values are wrong I want to stop synthesis with a custom error that will tell which ...
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ModelSim can not simulate my VHDL code
I am learning to program FPGAs and my code is compiled in Quartus prime but my .do file does not simulate in ModelSim. Any help is appreciated.
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Quartus Can't fit design into Device, is there any way to optimize it to get it to fit?
I have a module that takes in a sample, puts it in a large buffer, and sums the buffer. When it synthesizes, Quartus says it requires too many combinational nodes. I tried many things to see what ...
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Change clock frequency from 50MHz to 40MHz using Altera Cyclone IV and Quartus Lite 20.1
I'm using the FPGA board EasyFPGAv2.2 which have Altera Cyclone IV with chip EP4CE6E22C6 and I made a verilog program to generate VGA 640x480 60Hz signal. It works great dividing 50MHz by 2 generating ...
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How can one pass values to a bus in Verilog without first making a wrapper bus?
I have just defined an SR flip flop, and I need to now define a D flip flop. I am going about this by using an SR flip flop within my D flip flop. However, because I used a bus for my S and R inputs ...
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SystemVerilog output issue with "m" in a 5-to-1 Mux
I'm having an issue that I can't resolve on my own. I nested a 2-to-1 mux module inside of this 5-to-1, and no errors occur. Yet my output "m" will only ...
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How to make a D flip flop circuit that pulses 4 times per switch toggle?
For a school project we must design an ALU and its control circuit (see schematic).
As part of the controller, we must make a circuit that clocks our registers (one is PISO, the other SIPO). The ...
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Quartus keeps closing on me
Every time I create a new project quartus just closes on me. no error message no new window somewhere else it just closes. It makes the new project, and I can restart the program and work on the ...
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Syntax Help: VHDL Syntax Error at *.vhd near text ["process", "behave"] expecting "if"
Problem
I'm developing a simple LED blinking system in Quartus Prime Lite 18.1 to be instantiated on a DE0-Nano development board that makes use of the Cyclone IV E generation of Intel FPGAs. To do so ...
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Why is the number of instances shown in the RTL viewer and technology map (post-fit) different in Quartus Prime Lite?
I am a beginner in using FPGA and Quartus Prime Lite. I created a 32-bit adder using four 8-bit adders. These 8-bit adders were created using eight full adders.
I did the design using schematic .BDF ...
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How to open pin planner in Xilinx Vivado?
I am an Intel Quartus user getting to know Xilinx Vivado. I am using Xilinx Vivado for the first time. I am using Digilent ARTY S-7 FPGA board for learning purpose.
I am have created a blinking LED ...
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Build on-chip ROM in HDL
I wrote the next code in quartus 15.0, where I show what I want to do for a specific project. I can write it both in VHDL and Verilog HDL, but verilog is notoriously shorter.
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JTAG Communication Failure in ARRIA 10 FPGA
Has anyone bricked an ARRIA 10 FGPA (or any FPGA) and successfully unbricked it?
I have an ARRIA 10 that uses an EPCQ-L256 external memory to configure the FPGA. When I uploaded some code, I think I ...
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7-segment display communication
I have attempted to solve this problem making kmaps for the binary counter, mux and decoder however I'm getting stuck on the making them all talk to each other bit, I am using a ATmega32L and a ...
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What does 1'h1 mean in the RTL viewer diagram
Just new to Quartus, from my understanding 1'b1 basically means 1 as input, but why it shows 1'h1 on the diagram instead of 1'b1 or just 1?
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Why is my code output always showing 0?
This is a 4 bit counter code written using Verilog HDL on Quartus. Can somebody explain why is my output o always showing 0?
Code in Text :
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What does symbol width and "beat" mean for Avalon-ST interface?
This is the GUI for the Avalon-ST Source BFM found in Quartus Platform Designer.
I am trying to understand, what is the meaning of Symbol width and "beat" for streaming interface?
The ...
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How to see the conections in a decoder Quartus II web edition
I have a decoder whos 16 bit output is conecting to a one bit input. Acording to my knowldge of the design it would make sense. How can i know which output port of the decoder is conecting to that ...
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Quartus cannot place PLL
I am using Intel/Altera Cyclone V 5CSEMA4U23C6 on DE0-nano-SoC board.
My design is using one PLL that I added a while ago in Platform Designer.
Though it isn't explicitly calling Fractional PLL based ...
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Constraining simple design
I am stydying the Quartus II + TimeQuest Analyzer. The documentation is abreast, the examples are not that of, and explanations for beginners are scarce.
Here's the simple code:
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How to use command-line to cause Qsys to generate only synthesis or only simulation files?
In my project there are several Qsys files. Some of them are for synthesis but most are for testbench. When changes are made to source code, I usually just run generate Qsys system from the GUI and ...
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How to make Quartus generated programming files for two different but pin compatible FPGAs?
On most porotype boards there is a smaller FPGA which does fit the design but cannot fit a lot of signal tap tap to aid in debugging. Thus, I got a few boards modified with the largest pin compatible ...
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Manually override Quartus Fitter/Pin Assignment constraints
I have a design that I want to synthesize for / upload to a Max 10 FPGA.
One of the inputs goes to a PLL. Quartus now claims, that the neighbouring IO pin is too close to the PLL input pin and won't ...
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Unexpected change when reading input signals in a VHDL Finite State Machine
I implemented a FSM in vhdl using two processes;
A sync process for state transition
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How can I correct these Verilog syntax and declaration errors?
I am currently working on an Arduino to NIOS II Compiler that I am using on GitHub. I have provided a link to the compiler here: https://github.com/dimag0g/nios_duino. The issue I am having is that I ...
