Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Intel FPGA (formerly Altera).

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Is it possible to display a custom error message in Synplify syntezis with SystemVerilog code?

I write some library module on SystemVerilog. I want to check input parameters on synthesis and then if their values are wrong I want to stop synthesis with a custom error that will tell which ...
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ModelSim can not simulate my VHDL code

I am learning to program FPGAs and my code is compiled in Quartus prime but my .do file does not simulate in ModelSim. Any help is appreciated. ...
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Quartus Can't fit design into Device, is there any way to optimize it to get it to fit?

I have a module that takes in a sample, puts it in a large buffer, and sums the buffer. When it synthesizes, Quartus says it requires too many combinational nodes. I tried many things to see what ...
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Change clock frequency from 50MHz to 40MHz using Altera Cyclone IV and Quartus Lite 20.1

I'm using the FPGA board EasyFPGAv2.2 which have Altera Cyclone IV with chip EP4CE6E22C6 and I made a verilog program to generate VGA 640x480 60Hz signal. It works great dividing 50MHz by 2 generating ...
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How can one pass values to a bus in Verilog without first making a wrapper bus?

I have just defined an SR flip flop, and I need to now define a D flip flop. I am going about this by using an SR flip flop within my D flip flop. However, because I used a bus for my S and R inputs ...
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SystemVerilog output issue with "m" in a 5-to-1 Mux

I'm having an issue that I can't resolve on my own. I nested a 2-to-1 mux module inside of this 5-to-1, and no errors occur. Yet my output "m" will only ...
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How to make a D flip flop circuit that pulses 4 times per switch toggle?

For a school project we must design an ALU and its control circuit (see schematic). As part of the controller, we must make a circuit that clocks our registers (one is PISO, the other SIPO). The ...
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Quartus keeps closing on me

Every time I create a new project quartus just closes on me. no error message no new window somewhere else it just closes. It makes the new project, and I can restart the program and work on the ...
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Syntax Help: VHDL Syntax Error at *.vhd near text ["process", "behave"] expecting "if"

Problem I'm developing a simple LED blinking system in Quartus Prime Lite 18.1 to be instantiated on a DE0-Nano development board that makes use of the Cyclone IV E generation of Intel FPGAs. To do so ...
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Why is the number of instances shown in the RTL viewer and technology map (post-fit) different in Quartus Prime Lite?

I am a beginner in using FPGA and Quartus Prime Lite. I created a 32-bit adder using four 8-bit adders. These 8-bit adders were created using eight full adders. I did the design using schematic .BDF ...
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How to open pin planner in Xilinx Vivado?

I am an Intel Quartus user getting to know Xilinx Vivado. I am using Xilinx Vivado for the first time. I am using Digilent ARTY S-7 FPGA board for learning purpose. I am have created a blinking LED ...
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Build on-chip ROM in HDL

I wrote the next code in quartus 15.0, where I show what I want to do for a specific project. I can write it both in VHDL and Verilog HDL, but verilog is notoriously shorter. ...
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JTAG Communication Failure in ARRIA 10 FPGA

Has anyone bricked an ARRIA 10 FGPA (or any FPGA) and successfully unbricked it? I have an ARRIA 10 that uses an EPCQ-L256 external memory to configure the FPGA. When I uploaded some code, I think I ...
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I'm trying to build a 16-bit adder in Verilog but my output and carryout always have a value of X

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7-segment display communication

I have attempted to solve this problem making kmaps for the binary counter, mux and decoder however I'm getting stuck on the making them all talk to each other bit, I am using a ATmega32L and a ...
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What does 1'h1 mean in the RTL viewer diagram

Just new to Quartus, from my understanding 1'b1 basically means 1 as input, but why it shows 1'h1 on the diagram instead of 1'b1 or just 1?
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Why is my code output always showing 0?

This is a 4 bit counter code written using Verilog HDL on Quartus. Can somebody explain why is my output o always showing 0? Code in Text : ...
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What does symbol width and "beat" mean for Avalon-ST interface?

This is the GUI for the Avalon-ST Source BFM found in Quartus Platform Designer. I am trying to understand, what is the meaning of Symbol width and "beat" for streaming interface? The ...
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How to see the conections in a decoder Quartus II web edition

I have a decoder whos 16 bit output is conecting to a one bit input. Acording to my knowldge of the design it would make sense. How can i know which output port of the decoder is conecting to that ...
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Quartus cannot place PLL

I am using Intel/Altera Cyclone V 5CSEMA4U23C6 on DE0-nano-SoC board. My design is using one PLL that I added a while ago in Platform Designer. Though it isn't explicitly calling Fractional PLL based ...
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Why doesn't Qsys let me connect two conduits together by complaining that they do not have associated resets?

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Automatic launch of a tcl script at start of Quartus PlatformDesigner

Intel Quartus supports tcl scripts automation - specifically three specific options where user may define variables in the project file to automatically invoke custom tcl scripts at given points of ...
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Constraining simple design

I am stydying the Quartus II + TimeQuest Analyzer. The documentation is abreast, the examples are not that of, and explanations for beginners are scarce. Here's the simple code: ...
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How to use command-line to cause Qsys to generate only synthesis or only simulation files?

In my project there are several Qsys files. Some of them are for synthesis but most are for testbench. When changes are made to source code, I usually just run generate Qsys system from the GUI and ...
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2 votes
3 answers
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How to make Quartus generated programming files for two different but pin compatible FPGAs?

On most porotype boards there is a smaller FPGA which does fit the design but cannot fit a lot of signal tap tap to aid in debugging. Thus, I got a few boards modified with the largest pin compatible ...
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Manually override Quartus Fitter/Pin Assignment constraints

I have a design that I want to synthesize for / upload to a Max 10 FPGA. One of the inputs goes to a PLL. Quartus now claims, that the neighbouring IO pin is too close to the PLL input pin and won't ...
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Unexpected change when reading input signals in a VHDL Finite State Machine

I implemented a FSM in vhdl using two processes; A sync process for state transition ...
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How can I correct these Verilog syntax and declaration errors?

I am currently working on an Arduino to NIOS II Compiler that I am using on GitHub. I have provided a link to the compiler here: https://github.com/dimag0g/nios_duino. The issue I am having is that I ...
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How to form a 8-Bit bidirectional shift register using two 4-bit bidirectional shift registers?

I really had some trouble with one design question in my homework (the deadline has passed). We were asked to design a 4-bit bidirectional shift register using D-Flip flops and after that to create a ...
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TeraTerm can't detect the correct port, FPGA Project

I'm a beginner at FPGA design and have been actively trying to complete new projects to get more hands on experience. The project I'm currently working on is a tutorial from nandland. This video ...
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How do I correct this SystemVerilog syntax error?

I am working to reuse some Arduino code on my Cyclone V GX FPGA using a compiler I have found on GitHub. https://github.com/dimag0g/nios_duino I was also able to generate the HDL code for both the ...
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2 votes
1 answer
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How to ignore simulation only ports when mapping to FPGA pins?

A design has a number of simulation ports that should not be tied to FPGA pins. A VHDL example is shown in the source below, where the sim_only_* ports are for simulation only, thus should not be ...
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Reusing Quartus block schematic symbol file in another project

I am working on a Quartus project, requiring the usage of some designs previously created as block schematic design files in some other Quartus projects. I generated symbol files from the top design ...
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Avoiding node removal during optimization for preliminary estimation

I'm doing a preliminary FPGA design where I want to establish whether I will be able to implement the pinout and clock routing -- basically I'm placing all the hard IP blocks and wiring up the clocks, ...
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How does Quartus pin planner know about voltage in each I/O bank?

It is possible to specify a range of I/O standard options in Quartus pin planner. I am trying to understand a few things: How does Quartus know what voltage is supplied to each bank? Why does Quartus ...
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Quartus II - State Machine Viewer does't show all arrows/conditions?

As can be seen in the red circle, only arrows with condition a are shown, there is no !a condition at all. To replicate this ...
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Quartus Prime Lite: Error (209053): Unexpected error in JTAG server -- error code 35 and Error 202940 Can't access JTAG chain with SSH

Today I received a Terasic USB Blaster and I want to program an Altera 10M04SCE144C8G FPGA. I am using the Intel Quartus Prime 20.1.1 Lite Edition installed in Ubuntu 20.04. This FPGA has already been ...
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2 answers
243 views

Registered signal and Fmax in Timing Analyzer from Quartus II

I have the following module that is a simple register: ...
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How to view the internal signals of module in ModelSim using the testbench?

I have looked over this tutorial (Tutorial - Using Modelsim for Simulation, for Beginners. ) how to add waves and write test benches for VHDL module I looked over some answers as well like this one to ...
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typing error showing on quartus prime lite?

I am trying for few hours to understand why Quartus Prime Lite keep showing an error when I compile this basic VHDL code, I kept it like this to understand why it is showing an error just by typing!!!....
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How to implement a comparator logic gate in Quartus software? [closed]

Been trying for hours...How do I properly implement the following expressions: F0 = A0'A1'B0 + A0'B0B1 + A0B0'B1' + A1'B0B1 F1 = A1'B1 + A0'A1B1' + A0A1'B0' + A0B0'B1 + A1B0B1' I'm using NAND & ...
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Does Quartus support UVM in files with .sv extension?

I want to learn UVM later (i am starting with verilog first, systemverilog is next) but i have this doubt in my head, i have seem examples in the web but they use Modelsim, so my doubt is, if i make ...
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What is the proper method to become able to connect conduit signals inside Qsys?

Qsys (now known as Platform designer) identifies Avalon MM, Avalon ST, Clock, Reset and some other type of interfaces and makes it trivial to be able to connect them between different blocks. However, ...
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Help me debug these VHDL errors please

There are just 6 errors now Can't trace errors in this VHDL ...
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1 answer
570 views

How to make a very large lookup table in Verilog?

I have a requirement to make a verilog module that takes a Gray code integer i and returns the Gray coded integer i-1 using combinatorial logic only. When I look up examples of Gray decoding, for ...
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Unable to generate device simulation libraries from Quartus Prime

I am using Quartus 18.1. I am trying to generate device simulation libraries as per the procedure here: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/...
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What does "database" do in Quartus?

Quartus has settings to export/import database under the project drop-down box. The project directory contains two folders named db and incremental_db. What is this "database" and what does ...
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Output waveform of TCS3200

I am trying to use TCS3200 color sensor for my project with De0 nano FPGA board. The output of TCS3200 is a square waveform and i am confused how to use that waveform for a particular task. I searched ...
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why the D-FF does not use the clock assigned by me Quartus schematic

The schematic given above is a simplified version of a design. But this is enough to explain my problem. As you can see from the schematic, clock signal of second dff is connected to (Q0' & clk). ...
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UART receiving random values

I tried to transmit "S" using De0 nano FPGA board and UART over USB module . The problem is i am not receiving "s" constantly . I am using the software Called Hterm to see ...
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