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0answers
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In Intel Quartus Static Timing Analyzer should -ve setup slack on a path in Slow_900mV_0C model also show up in Slow_900mV_100C model?

I am trying to understand why the paths with -ve slack in Slow_900mV_0C model do not show up in Slow_900mV_100C model. I am using Arria 10 GX. I would think the process part of the model is likely ...
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1answer
393 views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
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1answer
245 views

Is it possible to find the critical path in specific part of the design?

I have written RTL description of a circuit in VHDL which is hierarchical and I am using Altera Quartus II; my design meets timing. I had set 50MHz clock frequency (20ns period) constraint using ...
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0answers
38 views

What is a feasable design goal for maximum clock frequency (related to setup timing) for a modern CPLD containing the attached circuit?

The CPLD is an Altera MAX V, with speed grade 5 (note that the MAX V comes with speed grades 4 and 5, where 4 is the faster one). The circuit consists of a 5-bit binary up counter where the count ...
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1answer
1k views

TimeQuest Timing Analyzer: What is the difference between post fit and post map timing netlists?

When we wish to add timing constraints to our design in TimeQuest Timing Analyzer, we have two options. We can use either a post fit netlist or post map netlist. Post map netlist is available after ...
3
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1answer
605 views

Constraining the reset line

I am using Quartus II to compile my Verilog design, and I'm working to properly constrain my signals. I know how to constrain clocks, for example: ...
5
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3answers
4k views

Setting FPGA pins as virtual

I have a Verilog module for which I want to check its timing in isolation to the rest of the system. The problem is that the FPGA has a limited number of physical pins, and my module has more inputs ...