Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Intel FPGA (formerly Altera).

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Can FPGA out perform a multi-core PC?

I don't understand how FPGA can be used to accelerate an algorithm. Currently I'm running a time consuming real time algorithm on a quadcore laptop so that four computations can be done in parallel. ...
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How to upgrade a Quartus II project from SOPC to QSys?

I don't understand my errors in QSys, can you help me? I'm trying to go through this exercise: http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf In Qsys when I connect the components I ...
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2 votes
3 answers
14k views

Using VHDL code to design a JK Flip Flop

I'm using quartus II to design a JK Flip Flop. However, my results show unknown output. Why is it? Intended design circuit: VHDL code: ...
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2 answers
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Counter in verilog

i want to make a counter that increases by the value of its inputs, but i did the testbench and the output is undetermined, xxxx. Can someone tell me if there is something wrong in this code? ...
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1 answer
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Get more AS-attached flash chip information from ALTASMI

I am playing with the attaching various configuration flash devices to the Altera Cyclone 3. In particular, I want to replace EPCS16 (2MB) with W25Q128 (16MB) - for both size and cost reasons. Is ...
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6 votes
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Setting FPGA pins as virtual

I have a Verilog module for which I want to check its timing in isolation to the rest of the system. The problem is that the FPGA has a limited number of physical pins, and my module has more inputs ...
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12 votes
1 answer
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FPGA starts working after irrelevant changes, why?

I have written a UART module in Verilog. By using that module I get data from PC via UART and then send that data back again via this UART module. I uploaded it to FPGA for testing. It works flawless ...
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3 votes
1 answer
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How to assign clock/reset to sram in Quartus?

I'm building a system in Quartus according to this question How to upgrade a Quartus II project from SOPC to QSys? Now a part of the problem is how to assign clock/reset pins to my sram. In Quartus ...
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2 votes
1 answer
864 views

Avoid using DSPs in Quartus Prime

I like to implement a simple module without using any DSPs on the FPGA. In other words, I like the whole design to be implemented using logic. Is there an option in Quartus Prime that allows me to ...
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1 answer
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How to wire a system for Nios 2 in Qsys?

I've managed to reduce the number of errors but I still have some: ...
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2 votes
3 answers
632 views

Does setting pins as virtual affect timing?

I have a Verilog submodule which I am testing independently. This module has too many top level pins to fit in my FPGA, so I have set some of the pins as virtual so that it would compile without ...
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Can't synthesize my VHDL in Qsys

I'm trying to make a module with VHDL for my DE2 where the easy thing ("Hello World") is nearly impossible. The bakground is that I'm trying to run Hello World: https://stackoverflow.com/questions/...
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1 answer
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Quadrature counter on FPGA is running away

I am attempting to count pulses from a quadrature encoder in an Altera FPGA. I believe I have my counter set up correctly (circuit diagram below, following this tutorial), but when I turn my encoder ...
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2 answers
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Quartus Gives Undefined Signal For the State of a Finite State Machine. Supposed to Be Showing Enum of the State_type

Before beginning a larger project in Quartus II I'm trying to do the section 8.8 "FSM as an Arbiture Circuit" example from the book "Fundamentals of Digital Logic with VHDL Design 3rd ed" and I can't ...
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2 answers
206 views

FPGA Synthesis = 0 LE (Altera Quartus II)

Just starting with FPGAs and stuck with a synthesis issue. Basically, the circuit I am designing is coming out with 0 logic units and 0 for all resources except for the pins assignment. The code ...
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2 answers
3k views

Quartus, Modelsim, VHDL - Viewing Internal Signals

This question is rather specific which makes it rather hard to answer. I'm using Quartus Prime software from Altera to do an FPGA design in VHDL. Quartus exports to Modelsim for the simulation. I'm ...
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-1 votes
1 answer
406 views

Help me debug these VHDL errors please

There are just 6 errors now Can't trace errors in this VHDL ...
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-2 votes
1 answer
180 views

Design of carry chain -- Problems with clock's in design

I am trying to implement carry chain on FPGA and i want that resault from each block is written in register. Each block is 10 bit adder with following code: ...
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