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Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Altera.

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5answers
8k views

Can FPGA out perform a multi-core PC?

I don't understand how FPGA can be used to accelerate an algorithm. Currently I'm running a time consuming real time algorithm on a quadcore laptop so that four computations can be done in parallel. ...
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1answer
4k views

How to upgrade a Quartus II project from SOPC to QSys?

I don't understand my errors in QSys, can you help me? I'm trying to go through this exercise: http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf In Qsys when I connect the components I ...
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3answers
8k views

Using VHDL code to design a JK Flip Flop

I'm using quartus II to design a JK Flip Flop. However, my results show unknown output. Why is it? Intended design circuit: VHDL code: ...
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2answers
1k views

Counter in verilog

i want to make a counter that increases by the value of its inputs, but i did the testbench and the output is undetermined, xxxx. Can someone tell me if there is something wrong in this code? ...
0
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1answer
85 views

Get more AS-attached flash chip information from ALTASMI

I am playing with the attaching various configuration flash devices to the Altera Cyclone 3. In particular, I want to replace EPCS16 (2MB) with W25Q128 (16MB) - for both size and cost reasons. Is ...
3
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1answer
793 views

How to assign clock/reset to sram in Quartus?

I'm building a system in Quartus according to this question How to upgrade a Quartus II project from SOPC to QSys? Now a part of the problem is how to assign clock/reset pins to my sram. In Quartus ...
2
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1answer
2k views

How to wire a system for Nios 2 in Qsys?

I've managed to reduce the number of errors but I still have some: ...
2
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1answer
350 views

Avoid using DSPs in Quartus Prime

I like to implement a simple module without using any DSPs on the FPGA. In other words, I like the whole design to be implemented using logic. Is there an option in Quartus Prime that allows me to ...
2
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3answers
571 views

Does setting pins as virtual affect timing?

I have a Verilog submodule which I am testing independently. This module has too many top level pins to fit in my FPGA, so I have set some of the pins as virtual so that it would compile without ...
1
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1answer
3k views

Can't synthesize my VHDL in Qsys

I'm trying to make a module with VHDL for my DE2 where the easy thing ("Hello World") is nearly impossible. The bakground is that I'm trying to run Hello World: https://stackoverflow.com/questions/...
0
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1answer
946 views

Quadrature counter on FPGA is running away

I am attempting to count pulses from a quadrature encoder in an Altera FPGA. I believe I have my counter set up correctly (circuit diagram below, following this tutorial), but when I turn my encoder ...
0
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2answers
2k views

Quartus Gives Undefined Signal For the State of a Finite State Machine. Supposed to Be Showing Enum of the State_type

Before beginning a larger project in Quartus II I'm trying to do the section 8.8 "FSM as an Arbiture Circuit" example from the book "Fundamentals of Digital Logic with VHDL Design 3rd ed" and I can't ...
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0answers
2k views

VHDL gate level simulation using quartus prime lite edition, error

I've designed an adder and the related testbench. I've run the RTL simulation, and it works as I expect, however I can't run the gate level simulation. adder.vhd ...
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1answer
158 views

Design of carry chain — Problems with clock's in design

I am trying to implement carry chain on FPGA and i want that resault from each block is written in register. Each block is 10 bit adder with following code: ...