Stack Exchange Network

Stack Exchange network consists of 175 Q&A communities including Stack Overflow, the largest, most trusted online community for developers to learn, share their knowledge, and build their careers.

Visit Stack Exchange

Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Altera.

-2
votes
2answers
68 views

Trouble understanding timing simulations in Quartus?

I have tried my ALU on the functional simulation and I get the correct waveforms. However, I am confused about how to interpret the timing simulations. What causes the ripples in the carry_out, and ...
3
votes
4answers
349 views

Synthesis Result : RTL vs Technology Map Viewer

I am evaluating this code below. But I saw that the logic output of the RTL and Technology Map Viewer are different. I use Quartus Prime Elite Edition. Am I missing something? this is the truth table ...
0
votes
1answer
52 views

Why am I getting my result as a string of Zs in Quartus?

I am new to Quartus, and have been trying to test out my 32-bit ALU on Quartus 13.1. When I try the functional simulation, I get a string of Zs. The results for the individual components, like the ...
2
votes
1answer
506 views

Error (209015): Can't configure device. Expected JTAG ID code 0x020B10DD for device 1, but found JTAG ID code 0x000210DD

I bought from ebay Altera Cyclone II EP2C5T144 development board. It came with USB Blaster. I'm using Quartus II 13.0sp1. FPGA is programmed with default settings as it should be (flashing onboard ...
1
vote
1answer
338 views

How to read values from a ROM to control a VGA monitor

first I have to say that I'm still a beginner and learning VHDL so any advice is a lot of help. What I'm trying to do is control an image in a VGA monitor with an FPGA (Cyclone II), using a .mif ...
0
votes
0answers
38 views

What is a feasable design goal for maximum clock frequency (related to setup timing) for a modern CPLD containing the attached circuit?

The CPLD is an Altera MAX V, with speed grade 5 (note that the MAX V comes with speed grades 4 and 5, where 4 is the faster one). The circuit consists of a 5-bit binary up counter where the count ...
0
votes
1answer
21 views

How to synthesis, fit, and generate assembly bistream without re-launch all proccess in Quartus?

In Quartus Prime (17.0) it take a looong time to generate bitstream on my computer. To generate the rbf for cycloneV, with DDR3 controller and serializer/deserializer in design it take about 12 ...
1
vote
1answer
98 views

Easiest way to instantiate a transceiver in Quartus to avoid unused channel degradation

This answer in the altera knowledge base indicates that the TX channels on the Arria 10 degrade over time if left unused. I have added the recommended assignment to my QSF file, but it has no effect ...
1
vote
0answers
58 views

Verilog code indetermination [duplicate]

i have a problem with this code, because in the RTL simulation, the output Cookie appears as StX. I don't know why this is happening since i don't know verilog well. Can someone help me? ...
1
vote
2answers
1k views

Counter in verilog

i want to make a counter that increases by the value of its inputs, but i did the testbench and the output is undetermined, xxxx. Can someone tell me if there is something wrong in this code? ...
0
votes
1answer
651 views

Quartus, Modelsim, VHDL - Viewing Internal Signals

This question is rather specific which makes it rather hard to answer. I'm using Quartus Prime software from Altera to do an FPGA design in VHDL. Quartus exports to Modelsim for the simulation. I'm ...
-1
votes
1answer
59 views

how does resources being handled for bitmaps (and graphical objects) in Quartus

in a project I've made recently (Quartus, Cyclone 2, altera) I wanted to produce both VGA graphical output, and sound output (via another board). I've noticed a large amount of logic cells went on ...
0
votes
2answers
2k views

Eliminate VHDL inferred latch in case statement

I'm a mostly analog EE who's trying to set up an fpga dev kit (terasic de0-nano) to twiddle the control bits on some pulse control parts I'm doing an evaluation board for. I'm using an external dip ...
0
votes
1answer
519 views

DE0-Nano-Soc programmer “failed” error

I am very new to FPGA programming. Got my Atlas DE0-Nano-SoC 5CSEMA4U23C5N board today and now trying to program the board using Quartus Prime Lite. Have created some VHDL code and run analysis and ...
1
vote
2answers
955 views

FPGA maximum frequency : limiting factor

I would like to know which in general may limit the maximum clock frequency of a circuit implemented in FPGA. In the specific case I am building some FIR filters using Quartus and simulating them on a ...
2
votes
1answer
1k views

Quartus Prime: Automatically program .sof file after compilation

I found a resource on Automatic Script Execution so I know how to create a .tcl script that executes when compilation is complete. I'd like to know what needs to be in that .tcl script to ...
0
votes
1answer
575 views

FPGA, accessing data in RAM

I'm using an Altera Cyclone V DE1-SoC for an image processing project and to be able to do the "processing" on the FPGA, I thought I probably needed to store the image data on the FPGA first. So I ...
0
votes
0answers
568 views

Modelsim: Unresolved defparam reference to somewhere

In Quartus ii schematic diagram, i've generated an lpm_ff. Then i've converted the design to a .v file. when i want to use this ...
1
vote
1answer
277 views

Quartus Prime Qsys HPS(Hard Processor System) Error

I'm trying to generate a system including HPS(Hard Processor System) of the Cyclone V SoC in Quartus Prime Qsys. At the "Generate HDL" stage I got the following errors. I'm not expecting all the error ...
-1
votes
1answer
65 views

VHDL Syntax Errors for Counter

Here is my code for an n mod k counter in VHDL. I keep getting various syntax errors but can't seem to pin down exactly what I'm doing wrong. Any help would be appreciated. ...
-1
votes
1answer
1k views

How to create Verilog or VHDL from a Quartus design

I have done a Quartus design from logical primitives for FPGA. Now I would like to see the corresponding Verilog or VHDL if feasible. Is that possible with Quartus and if so, how?
2
votes
3answers
7k views

Using VHDL code to design a JK Flip Flop

I'm using quartus II to design a JK Flip Flop. However, my results show unknown output. Why is it? Intended design circuit: VHDL code: ...
3
votes
1answer
6k views

Altera Quartus “Warning (18236): Number of processors has not been specified…”, how to suppress?

My Altera Quartus builds show this warning... ...
0
votes
1answer
3k views

QUARTUS II: Error: Port “cg” does not exist in macro function “ADD0”

So i got 8 error while compiling this 4 bit Carry-lookahead adder. I got the above error for ports cg and cp in macro functions ADD0-ADD3. For my code check the attachments. Edit: Here i've copied the ...
0
votes
1answer
66 views

Msg about opencore in Quartus programmer

I did some changes to a design in Quartus and in Qsys. Now when I load the design to my FPGA with Quartus programmer then I get a message about opencores and that there is unlimited time. The msg was ...
2
votes
2answers
560 views

Which files are required to copy / version my Quartus project?

I created a 4-bit CPU in latest version of Quartus. Now I wonder which files are necessary if I want to put the files in source control? I understand that bdf, sof and qpf files should be versioned. ...
1
vote
2answers
633 views

Interfacing 64Kx16 bit SRAM with Qsys

I have two 64Kx8 bit memory chips which I have connected to an FPGA configured using Qsys as a single 64Kx16 block. I have used a Generic Tri-state controller as interface, with both address width and ...
-2
votes
1answer
54 views

Using ieee.proposed package for a dft. Quartus showing just 10 logic elements corresponding to just 10 states. [closed]

Can anyone suggest possible reasons why this might be happening? Compilation is succesful. We have analyzed the code. Can't figure out any logical errors or syntax errors(else wouldn't compile).
0
votes
1answer
438 views

How to add a 32-bit input in Quartus 2

Can you help me to add a multiple pins input in Quartus 2? If there is not a default one, how can I add it by MegaWizard Plug-in Manager? Thanks!
0
votes
0answers
122 views

Unable to use the VGA port correctly, De1 Soc distorts signal depending on the output pin

This is a followup to my previous question. The code I was using, pin assigmnets and the theoretical timings for VSYNC and HSYNCH were correct. I have used to oscilloscope to look at the signals, ...
2
votes
1answer
809 views

What is a safe state machine?

When I implement a "safe" state machine in Quartus, what is the difference between a normal/unsafe state machine? Edit: And is this the same as: ...
0
votes
1answer
225 views

What is the real speed of my system implemented on FPGA? How to check this value?

I created an FPGA system on ModelSim (a simple algorithm that calculate an equation and save on-chip), synthesized with Quartus Prime, then downloaded to my DE1-SOC. My intention is to compare my ...
1
vote
2answers
739 views

Are there open free USB designs?

I want to learn USB and its hardware interface and start with a trivial design. I found some VHDL in github for the ISP1362 and I wonder if that is a good starting point. I have already used Quartus ...
1
vote
1answer
71 views

Quartus II Error (18994): configuration scheme “passive serial” is not valid for the device

I'm trying to synthesize a System Verilog design into a Stratix 10 device using quartus II v.17 but keep getting the following error. Error (18994): configuration scheme "passive serial" is not ...
2
votes
0answers
2k views

How to assign constant value to bus in Quartus II schematic editor?

No matter what I try, Quartus just spams errors similar to this: Error (12009): Node "modulus[31]" is missing source
0
votes
0answers
69 views

How to know the speed and energy of a particular Digital Design in Quartus-II and DE1-SOC FPGA (Altera)

I did a digital design in Quartus II and my board DE1-SOC FPGA, now I want to read 3 factors: general speed that digital design takes to finish the application, area of the design if it would be a ...
0
votes
1answer
674 views

Up/Down mod 105 counter based on 74193

I'm assigned with creating up/down counter in quartus II, but I can't find a way to do it properly. In simulation it always ends in transient state, so I guess there are some metastability issues that ...
0
votes
1answer
368 views

How to see the content of the SDRAM in my DE1-SOC while running (JTAG Altera cable)?

I have made a simple design in Quartus Prime, in verilog code, not using megawizard, but directly accessing the pins of the SDRAM. I am saving 2 x 16 bits binary numbers on 3 of the 4 banks of the ...
1
vote
1answer
95 views

Verilog Synchronous bit alternator (Quartus/Modelsim) - Altera FPGA

I am trying to make a simple bit alternator for the purpose of learning how to use verilog for FGPA design and how to simulate in modelsim. Here is my code: ...
0
votes
1answer
207 views

Implementing VHDL FSM in Quartus with “couldn't implement registers for assignments on this clock edge”

I'm supposed to write code for simple frequency meter. What it is supposed to do is: when you press button it should measure frequency of input signal based on 1Hz clock signal so the outcome won't ...
0
votes
3answers
850 views

can quartus synthesize a tri-state bus?

Would the following Verilog be synthesize (in Altera's Quartus) to a bus of 1024 tri-state devices connected to one wire? Will it be faster (clock latency) than a binary tree of 1024 or-gates? ` <...
-2
votes
2answers
977 views

Is there a connection between circular buffer, FIFO and shift register?

I know that circular buffer and FIFO are similar but do not understand the difference that causes different terms to be used. How do these two compare with a shift register? How do I know if I need ...
2
votes
2answers
3k views

What is the standard way to represent fixed point numbers in VHDL?

Is there a native type in VHDL language similar to std_logic_vector that allows one to create a signed or unsigned fixed point number for given length of fractional and whole parts? If so, can it be ...
0
votes
0answers
434 views

How to view wire values in Altera Quartus Prime

I would like to be able to view waveforms showing internal nodes in a circuit specified in Verilog in Altera Quartus Prime. I am having trouble doing so when a wire is an output of one module and an ...
2
votes
2answers
14k views

How do I generate a schematic block diagram from Verilog with Quartus Prime?

The answers to this question say that Altera Quartus will generate block diagrams from Verilog files. I'm a user of Quartus Prime Lite Edition. How do I generate block diagrams?
0
votes
1answer
4k views

Vhdl error 10327 - can't determine definition of operator “”&“” — found 0 possible definitions

I'm adjusting some vhdl code an am getting the following error: Error (10327): VHDL error at myfile.vhd(87): can't determine definition of operator ""&"" -- found 0 possible definitions The ...
0
votes
1answer
188 views

Unexpected behaviour in Altera clock crossing FIFO

As far as I am aware, in a FIFO as we keep reading it will eventually become empty i.e no more data inside and its output shall become 0x0. If we keep reading it after it has become empty, we shall ...
2
votes
1answer
778 views

Why don't my programs stay in the FPGA MAX 10 after a power cycle? [closed]

I program my FPGA (MAX 10) with a .sof file and works, but when I turn off my device everything erases from my FPGA. After exploration on the internet I found the EPCS IC, and I find out my board ...
0
votes
1answer
135 views

How do I add a node to a point in a circuit in Quartus Prime?

I would like to be able to view not just the output of my circuit in simulation but also an interior node. You can see it in the below diagram. I named the connection "D2". Do I have to connect that ...