Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Altera.

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Quartus II - Can I include other files into a *.qsf file?

An Altera Quartus II project consists of one *.qpf and one or more *.qsf files. The qsf seems to be a TCL script like other EDA related settings and config files (e.g. xdc, sdc, ...). Is is possible ...
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1k views

What is Verilog Output (.vo) file? When it is created?

I was running PCI Express reference design simulation in Modelsim. Compilation failed and an error "cannot open top_core.vo file in read mode" was displayed. I went through respective folder, but that ...
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1answer
293 views

Nesting entities in VHDL (Altera Quartus)

I want to ask a question. I'm trying to simulate a cpu. I did my schema and basically there are two logical parts of the CPU. The first part is composed of a FIFO buffer, Cache memory for ...
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1answer
149 views

Benefits of using Altera IP in FPGA designs?

I've just started using Quartus to synthesize a VHDL design that I created a while ago. Inside of this design are things like DFFs, decoders, etc. I noticed that Altera has IP of its own with the same ...
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1k views

Is it possible to change the grid size in Quartus II schematic window?

Having a schematic for the top level structure of design appears to be a good idea. I have a few schematic symbols that I want to edit. The signal name is too long and does not appear correctly in the ...
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2k views

Can one instantiate RAM with 2 read ports and 1 write port as IP in Quartus?

As part of MIPS design we have something called as register file. It only has 32 registers each 32 bit which only makes 1024 bits or 128 bytes. I am not sure how to tell Quartus to instantiate this as ...
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1answer
251 views

Does the altera ROM megafunction have a startup delay?

I'm trying to make a very simple single cycle CPU in VHDL. My machine code is stored in a ROM that was made by the Altera MegaWizard. The first word that is stored in this ROM is 0x1111. After writing ...
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2answers
591 views

Process statement in vhdl

I have a very basic question here. When I learnt Processes it was said the statements occur sequentially.This is what I believed in. In the NCO process image file,there is proof for it. fword is ...
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7k views

How to read firmware from Altera's FPGA (Cyclone IV) with USB Blaster?

I'm starting to investigate Altera's Cyclone IV FPGA to use in my projects. Now I borrowed from neighboring company a real device with USB Baster Rev.C. I'd try to use one instead of evaluation board ...
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1answer
788 views

Write an I2C code for Cyclone 2 architecture

I really need to I2C interface my FPGA with some slave device. I figured I could use the audio codec in my FPGA as a slave.I have gone through some codes from the internet for I2C. But I do not get ...
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1answer
4k views

Using a mif file in Quartus

I have created an mif file in Quartus and I am working with cyclone 2 Altera. My query is "How can I use this mif file to initialize a variable in my top level design architecture"? Let me elaborate. ...
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1k views

Altera's DRAM Controller with UniPHY

I am trying to port a design from Xilinx to Altera, and I have issues with the DRAM controller IP (for a Cyclone-V and a LPDDR2 mem). I have managed to generate the IP, but I don't understand which ...
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1answer
646 views

Using the ROM megafunction in VHDL code

I have created a ROM megafunction using the MegaWizard plug-in Manager. This created a new file which I named rom.vhd. My code: ...
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3answers
10k views

How to define a clock in Quartus II?

I have this piece of code here: ...
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2answers
1k views

FPGA SPI slave not working well

I'm tring to integrate a SPI Slave in VHDL (opencores) http://opencores.org/project,spi_master_slave the idea is to interface a Microcontroller and an FPGA I'm Using Quartus.. more info: ...
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1answer
498 views

How to tell pin planner to not connect an IO signal

In my CycloneV design, I have a 64 bit GPIO port but I only want to connect 40 pins in my design. If I left it unconnected, Quartus will try to place it and will generate an error because of there ...
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1answer
183 views

Using Enable to switch between two Decoders

I am trying to put an enable input in a 4-to-16 decoder so I can select between two decoder. Here is a schematic: I am using two decoders to select two different addresses in a 16x16 SRAM. I am ...
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1answer
3k views

De1-soc HPS-to-FPGA AXI bridge

I work on DE1-Soc. I am using a linux BSP (linux console) that i found in terasic's website linux image. I have some questions about the AXI bridge. In fact i would like to send some data from the ...
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1answer
203 views

Why build errors when connecting timers in Quartus ii?

I use the Nios 2 IDE from Altera with the Altera DE2. I add a file Functions.c with code that needs a timer e.g. ...
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1answer
3k views

How to install Altera USB master driver for Windows 8 (64 bit)?

I am trying to connect Altera Stratix 4 board with my PC in which Quartus 11.0 is per-installed. But my PC is not detecting USB JTAG connection from the board. What I am guessing is that, this ...
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1answer
170 views

Is it technically feasible to design a microchip that won't fail foreign characters? [closed]

I used to work as web developer and did the same part of the project for several decades: Making sure that our Scandinavian characters åäöÅÄÖ... will work. It was feasible and it did work, basically ...
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2answers
200 views

Verilog megawizard RAM not read

I used Quartus II Magawizard to ask for a two port RAM(one read and one write). The addresses are correct but the data out is always z. Can some one help me with this problem? I have stuck here for a ...
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1answer
351 views

VHDL - Quartus II inferring latches on circuit

My circuit is based on a state-machine. I checked it and it's working fine, the only issue is that it's inferring one latch per flip-flop (The state machine has 11 states and the circuit is one-hot so ...
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2answers
529 views

VHDL - Flip Flop inferring on a signal

I have to design a circuit to count up to a number and return to zero. It must have a carry signal (which I named a_o in my circuit) as flag to show that the ...
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1answer
574 views

Verilog only assigns first bit of a bus

I'm trying to assign a 12bit parallel bus to a 12bit register. I've reduced the problem to this literal assignment but as with the previous case, only the first bit is being written to anything when ...
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5answers
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Can FPGA out perform a multi-core PC?

I don't understand how FPGA can be used to accelerate an algorithm. Currently I'm running a time consuming real time algorithm on a quadcore laptop so that four computations can be done in parallel. ...
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1answer
138 views

How to constrain fitter to assign signals to specific LE input in Quartus II?

I have noticed that the time delay through a combinatorial cell in an LE can depend significantly (up to .1 ns on my DE-0 Nano Cyclone IV board) on which input, A thru D, the input is assigned to. To ...
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1answer
3k views

Shortest time required UART- UART transfer of 32 Byte block

I need to transfer 32 Byte block UART to UART 8 clock cycles per bit 1 start bit Struct 8-E-2 8bits 1 UART char, Even Parity, 2 stop bits/ char 1 + 8 + Even parity + 2 stop bits = 11 efficiency = 8/...
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2answers
470 views

Quartus FPGA migration issues

I have an FPGA design Quartus that compiles and works correctly for a cyclone IV EP4CE15F17C8 (42% used). I'm trying to migrate same design to a smaller FPGA EP4CE10F17C8, but when changing FPGA ...
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1answer
212 views

Report entire failing path in Quartus

I am trying to optimize a design that does not meet the constrains. I know that you can use Timequest Timing Analyzer -> Report Top Failing Paths to report the paths that have negative slack but it ...
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2answers
972 views

FPGA outputs are always high with basic and/or program

So I am just getting started developing with an Altera Cyclone II EP265 mini board, and I am having some trouble getting a program that outputs the "and" and "or" of three inputs working. The full ...
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1answer
1k views

TimeQuest Timing Analyzer: What is the difference between post fit and post map timing netlists?

When we wish to add timing constraints to our design in TimeQuest Timing Analyzer, we have two options. We can use either a post fit netlist or post map netlist. Post map netlist is available after ...
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1k views

Problem simulating FSM in Quartus II Simulator

I am trying to simulate a FSM using vector simulator... the state machine variable is called "Tstep_Q", I added it to waveform editor... however, when I start the functional simulation all signals are ...
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1answer
797 views

Quartus II: Suppress warnings by Verilog module

In my FPGA project I use the Quartus II PCIe megafunction. The number of warning messages this Altera library module produces baffles me. Is there a way to have Quartus II suppress all the warnings ...
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2answers
532 views

Simple FPGA serial communication not working

FPGA board (manual) USB-to-RS232 cable (controller) synthesis reports I created a simple schematic which shorts the TXD and RXD pins according to the manual. However, when I use RealTerm to send ...
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929 views

Quartus II hangs when trying to create new project [closed]

I have Quartus II installed under Ubuntu 13.10. It starts up fine, but when I click "finish" on the "Create New Project" wizard, it loads infinitely, stuck at 0%, then stops responding. I have tried ...
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136 views

Access to Quartus II beta

My FPGA card (a BittWare card, datasheet available here) comes with example designs which require Quartus II 14 (beta). I cannot find where the beta versions of Quartus II can be downloaded from the ...
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1answer
153 views

A simple VHDL circuit won't display initial value

Here is my code and it's pretty simple. I'm to cycle through the first 8 letters of the alphabet on a Altera Cyclone II board. ...
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0answers
49 views

Change CatapultC RTL naming scheme

I hope someone is familiar with Catapult - available tags make it seem unlikely. My issue is that I have two blocks (as seen in Quartus) being worked on independently, separate RTL. Unfortunately, ...
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1answer
582 views

Data Transmission Using RJ45 Cable in Stratix IV dev board

I'm totally a beginner and my question may seem a little bit stupid, but I would be grateful if you provide any help. I want to transmit data between my laptop and a Stratix IV GX Development board ...
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2answers
2k views

Quartus Gives Undefined Signal For the State of a Finite State Machine. Supposed to Be Showing Enum of the State_type

Before beginning a larger project in Quartus II I'm trying to do the section 8.8 "FSM as an Arbiture Circuit" example from the book "Fundamentals of Digital Logic with VHDL Design 3rd ed" and I can't ...
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1answer
200 views

Quartus II Memory Read Clock Problem

I used LPM_RAM to store data and made read and write operations. But it seems like placing the data to wrong addresses. Here is screenshots; Wave Result; Memory Block;
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1answer
270 views

What must be done, a new design?

I tried to compile a TCP / IP project for the MicroC / OS II RTOS with an Altera DE2 and a .sof design. I can run the MicroC / OS II with other apps but when trying ...
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1answer
968 views

Reason behind Altera's divide functions pipeline delay?

In Quartus II, the standard lpm_divide function has a parameter PIPELINE_DELAY. The default value is floor(WIDTH_Q div 2) - ...
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3answers
6k views

How to efficiently implement a single output pulse from a long input on Altera?

I have a fast clock and a switch called 'ready'. When the switch is flipped (ready goes HIGH), I would like the output pcEn to produce a pulse that lasts only for one clock cycle. pcEn will only ...
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1answer
783 views

How do I make use of multipliers to generate a simple adder?

I'm trying to synthesize an Altera circuit using as few logic elements as possible. Also, embedded multipliers do not count against logic elements, so I should be using them. So far the circuit looks ...
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1answer
2k views

How to reference subsets of logic[31:0] in SystemVerilog?

(I have two questions for you at the end.) I'm using SystemVerilog to do various exercises (for personal edification) in Digital Design and Computer Architecture's chapter 7. I'm using Altera's ...