Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Altera.

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Internal fmax of FPGA program

When I compile my project in QUARTUS, it provides me with information about "internal fmax" ...
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1answer
605 views

Constraining the reset line

I am using Quartus II to compile my Verilog design, and I'm working to properly constrain my signals. I know how to constrain clocks, for example: ...
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3answers
4k views

Setting FPGA pins as virtual

I have a Verilog module for which I want to check its timing in isolation to the rest of the system. The problem is that the FPGA has a limited number of physical pins, and my module has more inputs ...
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1answer
836 views

Quartus II - SignalTap II Getting the Period of Sampled Data

I am working on a VHDL project where I am trying to make an LCD controller. I have been trying to get the period of my scaled clocks using Signal Tap, however the time bar does not show the time ...
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633 views

Structuring Large Quartus Projects

I'm working on a project which will contain lots of smaller modules written in VHDL, how in quartus can I make this manageable also to the point that I can test the smaller modules. I am trying to ...
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2answers
2k views

How to implement FIR filter for Altera DE2?

I understand that a DSP is preferred rather than FPGA for an FIR filter, but my task is to implement both fixed-point and floating-point software filters (in C) for the Altera DE2. I barely know what ...
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2answers
4k views

Why no JTAG connection?

This used to work before I installed Quartus v10 to ensure backward-compatibility. Now I get no hardware found in Quartus both v13 and v10. The USB-Blaster used to show up, then I installed Quartus ...
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2answers
918 views

What OS do I install on parallels to run Quartus II and other design software?

NOTE: I see a few similar questions on here in regards to Quartus II but I have some additional questions I believe would be best delivered in a new thread. I'm fixing to run windows 7 or 8 off ...
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2k views

How to wire a system for Nios 2 in Qsys?

I've managed to reduce the number of errors but I still have some: ...
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305 views

VHDL variable behaving strangely

I have the following snippet of VHDL code which is misbehaving and I don't know why: ...
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1answer
764 views

How to assign clock/reset to sram in Quartus?

I'm building a system in Quartus according to this question How to upgrade a Quartus II project from SOPC to QSys? Now a part of the problem is how to assign clock/reset pins to my sram. In Quartus ...
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3answers
551 views

Does setting pins as virtual affect timing?

I have a Verilog submodule which I am testing independently. This module has too many top level pins to fit in my FPGA, so I have set some of the pins as virtual so that it would compile without ...
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2answers
5k views

Quartus II: Where are the worst-case paths?

In the Quartus II settings (under TimeQuest timing analyser), I have checked the Report worst-case paths during compilation checkbox. However, I do not see any ...
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How to upgrade a Quartus II project from SOPC to QSys?

I don't understand my errors in QSys, can you help me? I'm trying to go through this exercise: http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf In Qsys when I connect the components I ...
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1answer
3k views

Can't synthesize my VHDL in Qsys

I'm trying to make a module with VHDL for my DE2 where the easy thing ("Hello World") is nearly impossible. The bakground is that I'm trying to run Hello World: https://stackoverflow.com/questions/...
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1answer
180 views

How to route a node from one block to another block in Altera Quartus II [closed]

I am new to designing in and coding with with Altera Quartus II version 13 Web edition FPGA software. I am trying to split my design across serval blocks in order to make it more manageable. How do I ...
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1answer
377 views

Enabling uClinux to run on Altera DE2-115?

I'm trying to learn Qsys and Quartus II to define a system that can run linux according to this document: http://uuoc.org/uClinux_nios2_custom_hardware.pdf But I'm running into problem as the ...
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2answers
3k views

FPGA encoder counter running away randomly

I am programming an Altera FPGA using Quartus II v9.0 to count encoder pulses and output that count to an external LabVIEW program (see diagram below). I was able to debug one issue with my code ...
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4answers
12k views

Generating pulse train of varying frequency on an FPGA

I am working on generating a pulse train to control a motor that accepts a pulse train as an input. Each pulse corresponds to a pre-set movement increment; I can set one pulse equal to 1/1000 degree (...
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1answer
922 views

Quadrature counter on FPGA is running away

I am attempting to count pulses from a quadrature encoder in an Altera FPGA. I believe I have my counter set up correctly (circuit diagram below, following this tutorial), but when I turn my encoder ...
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1answer
431 views

Altera Quartus - How do I simulate a different Entity

I tested the first entity in my project successfully. Now, when I try to create a Vector Waveform File for my second entity, it only lets me add the pins of my first entity. I did set my new entity ...
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1answer
237 views

Grouping input and output signals with the corresponding clock

In my Verilog design, I have two asynchronous clocks, clk1 and clk2. Associated with each clock is a bunch of inputs and outputs....
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1answer
1k views

Can a system task like $display be used in code in Quartus II?

I started learning verilog recently and I tried this simple code: module hello_world ; initial begin $display ("Hello World by jai"); #10 $finish; end endmodule ...
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1answer
4k views

Free linting tool for Verilog

Is there an opensource linting tool for Verilog. I've seen HDL companion and other but they all come with a price tag.
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1answer
434 views

What to change when migrating designs from Altera DE2 to DE2-115?

I'm migrating a working design from Altera DE2 to Altera DE2-115 and I'm running into problems. First everything works with DE2 just like mentioned in the exercises doing what is instructed. Now I ...
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2answers
8k views

Can we run Quartus II on Ubuntu?

I can compile digital components and download them to the boards DE2 and DE2-115 I got. I do it from Windows 7 but I want to enable this on ubuntu while the files from Altera are for Red Hat Linux. I'...
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1answer
189 views

Custom SOPC Builder Components in Quartus II

I am trying to understand how to interface with a custom component within SOPC builder. Basically I have a verilog module which creates and outputs a tone to the audio out line on an Altera DE2 ...
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2answers
183 views

FPGA Synthesis = 0 LE (Altera Quartus II)

Just starting with FPGAs and stuck with a synthesis issue. Basically, the circuit I am designing is coming out with 0 logic units and 0 for all resources except for the pins assignment. The code ...
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3answers
356 views

View more than 100 worst-case paths in Quartus II

I am using Quartus II to compile Verilog for my FPGA project. For debug, I use SignalTap, which introduces a lot of timing warnings. When I go to the TimeQuest report, and look at the worst-case ...
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1answer
5k views

How can I avoid “Minimum Pulse Width” slack violations in Quartus FPGA synthesis?

I am synthesizing a toy application on DE2, but I hit a timing problem (despite every inputs and outputs are clocked in my design). These violations are related to "minimum pulse width"... How can I ...
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1answer
756 views

Set toggle rate in Quartus II

According to this document, I need to: assign 0 MHz toggle rate to Toggle Rate assignments for the pin in the Assignment Editor to place a non-differential pin ...
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1answer
1k views

VHDL code compiling on quartus II

Look at this piece of code (flip image on X) ...
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1answer
254 views

Why is carry on for an adder that is simply on? [closed]

I've understood that the behaviour is correct when I make a simple adder: But why does carry on light up just because I switch on the + operation for my 4-bit system? http://www.ict.kth.se/courses/...
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2answers
406 views

Need Quartis II CPLD tutorial for learning VHDL from ZERO [closed]

I am learning VHDL from zero using Altera CPLD. Already got Quartis II 12.1 and a 15-lines example VHDL (like Hello World for C learner). To avoid learning bad coding style or digging too deep too ...
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1answer
564 views

Configure Quartus 2 Simulator to run for longer

My simulation in Quartus 2 finishes at 1uS. How can I get it to go on for longer? This is because my test hasn't finished by this point so I can't tell whether or not my part is successful or not with ...
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1answer
10k views

Why do I get a Top Level Design Entity undefined in my VHDL

I'm building an 8-bit register from d-type flipflops in VHDL for a lab exercise but I can't seem to diagnose a problem. Firstly I can't get it to compile because of the difference in types for the ...
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1answer
950 views

Quartus II: Pin incompatible with a bank it is not on

I am using the pin planner of Quartus II to place my I/O signals on my Cyclone IV pins. I am stuck on the following fitter error: Error (169029): Pin adc0_in[0] is incompatible with I/O bank 3. ...
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2answers
2k views

Doesn't quartus II support simulate with a verilog file?

I want to simulate my module StreamLight ,So I create a Simulatefile module: ...
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1answer
355 views

Weird output Pulse in Vector Waveform in Quartus 2

I have an obscure output pulse in my output waveforms for my half-adder. Is it because that the inputs are both high at 40ns? So I should slightly delay b going high after a has gone low? The time ...
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1answer
1k views

My design is not meeting timing. What can I do?

I am using the Altera Quartus II software to compile Verilog for a Cyclone IV FPGA. In my case, the FPGA is fixed; I cannot get a faster one. Now one isolated module in my design, which deals with ...
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2answers
3k views

What is the I/O standard for the PCIe data lines?

I am entering the pin information of my FPGA design using the Altera Quartus II PinPlanner. One of the components of my design is PCIe, and I am having troubles understanding the "I/O standard" ...
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1answer
3k views

Quartus II ignoring synthesis attribute noprune

There is a register in my design that I am using for debug purposes with zero fan-out. Since it isn't driving any logic, the synthesizer optimizes it away. However, as far as my knowledge goes, ...
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1answer
128 views

Which 3.3V I/O standard should I use?

I am using the Altera Quartus II PinPlanner to enter all my pin details for my FPGA design. Some of the pins are connected to the SPI configuration bus of this ADC. As can be seen on page 8, the 3 ...
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2answers
305 views

Quartus II: Customise compiler messages

I am working with the Altera Quartus II compiler for my Cyclone IV. I am not happy with what is considered Info, Warning, ...
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1answer
6k views

Specify include path in Quartus II

I'm compiling Verilog using the Quartus II for the Altera platform. In my Verilog, I have a Verilog header global.vh, and Quartus II cannot find it: ...