Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Intel FPGA (formerly Altera).

47 questions with no upvoted or accepted answers
Filter by
Sorted by
Tagged with
4 votes
1 answer
3k views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
user avatar
  • 141
2 votes
1 answer
55 views

Why is the number of instances shown in the RTL viewer and technology map (post-fit) different in Quartus Prime Lite?

I am a beginner in using FPGA and Quartus Prime Lite. I created a 32-bit adder using four 8-bit adders. These 8-bit adders were created using eight full adders. I did the design using schematic .BDF ...
user avatar
2 votes
1 answer
144 views

My RTL viewer replaces NAND gates with AND gates with the inversion bubbles

I want it to show this MUX only with 3 NAND gates and an Inverter. so, I specified NAND gate in the verilog HDL code, but it keeps replacing it with AND gates with inversion bubbles without having a ...
user avatar
2 votes
0 answers
438 views

Cyclone IV FPGA: How to use nCSO pin (101) as normal I/O pin?

(I'm new to this -- so sorry if this is a dumb question). I've got a RZ-EasyFPGA dev board with a built in VGA port. I want mess around with generating a simple VGA signal. Dev board pin-out: I ...
user avatar
2 votes
1 answer
2k views

Quartus Prime: Automatically program .sof file after compilation

I found a resource on Automatic Script Execution so I know how to create a .tcl script that executes when compilation is complete. I'd like to know what needs to be in that .tcl script to ...
user avatar
1 vote
1 answer
61 views

SystemVerilog output issue with "m" in a 5-to-1 Mux

I'm having an issue that I can't resolve on my own. I nested a 2-to-1 mux module inside of this 5-to-1, and no errors occur. Yet my output "m" will only ...
user avatar
  • 21
1 vote
0 answers
50 views

Quartus keeps closing on me

Every time I create a new project quartus just closes on me. no error message no new window somewhere else it just closes. It makes the new project, and I can restart the program and work on the ...
user avatar
1 vote
0 answers
92 views

7-segment display communication

I have attempted to solve this problem making kmaps for the binary counter, mux and decoder however I'm getting stuck on the making them all talk to each other bit, I am using a ATmega32L and a ...
user avatar
  • 11
1 vote
0 answers
33 views

Avoiding node removal during optimization for preliminary estimation

I'm doing a preliminary FPGA design where I want to establish whether I will be able to implement the pinout and clock routing -- basically I'm placing all the hard IP blocks and wiring up the clocks, ...
user avatar
1 vote
0 answers
332 views

Quartus II - State Machine Viewer does't show all arrows/conditions?

As can be seen in the red circle, only arrows with condition a are shown, there is no !a condition at all. To replicate this ...
user avatar
  • 131
1 vote
0 answers
64 views

How to let Quartus generate VHDL out of Qsys automatically

I was wondering how I can get Quartus to automatically generate VHDL IP from Qsys files, instead of the default Verilog. I know I can change this in the command line or Platform Designer GUI for each ...
user avatar
1 vote
0 answers
298 views

VHDL Integer Range Output Bus Width

I'm currently working on writing a simple counter in VHDL, trying to genericize it as much as possible. Ideally I end up with a counter that can pause, count up/down, and take just two integer (min, ...
user avatar
  • 11
1 vote
0 answers
116 views

Difference in SystemVerilog-2005 HDL simulation behavior between Quartus Prime Lite (20.1) and ModelSim-Intel Starter Edition(2020.1)

A SystemVerilog module using an always@ block with a gated trigger does not compile in Quartus Prime Lite (20.1). Quartus Prime reports the following compiler error message: Error (10170): Verilog ...
user avatar
  • 141
1 vote
0 answers
259 views

I'm getting this error over and over and I don't know how to fix it . Error (12002): Port "S[0]" does not exist in macrofunction "inst8"

I'm working in Quartus 2, trying to use a busmux to select the what to do, but when I click compile I just get this error:
user avatar
1 vote
0 answers
84 views

Quartus produces different synthesis for same design

I synthesized my design in Quartus for Arria 10 in a remote server. In my memory instantiation, it is saying that it is unable to infer a Block RAM due to asynchronous reads. I tried to synthesize ...
user avatar
1 vote
0 answers
331 views

Problems with Memory Initialization in Quartus

I have the following code snippet in my VHDL code to initialize a ROM block: ...
user avatar
1 vote
1 answer
584 views

Bug in my SPI implementation (VHDL)

I'm new to VHDL/FPGA programming and I experienced some weird behavior in my SPI-Slave implementation. What I did: SPI-Master: I'm using an Arduino (ATMega328p MCU) as the SPI-Master. For debugging, ...
user avatar
  • 630
1 vote
1 answer
2k views

Set input low or high in Quartus

I have created a 4 bit register in VHDL, within Quartus. Normally, I connect each of my inputs to one of the dip switch pins or push button pins in the "pin planner" for my particular development ...
user avatar
  • 27
1 vote
1 answer
320 views

Easiest way to instantiate a transceiver in Quartus to avoid unused channel degradation

This answer in the altera knowledge base indicates that the TX channels on the Arria 10 degrade over time if left unused. I have added the recommended assignment to my QSF file, but it has no effect ...
user avatar
  • 133
1 vote
0 answers
55 views

Change CatapultC RTL naming scheme

I hope someone is familiar with Catapult - available tags make it seem unlikely. My issue is that I have two blocks (as seen in Quartus) being worked on independently, separate RTL. Unfortunately, ...
user avatar
  • 258
0 votes
0 answers
54 views
+50

Is it possible to display a custom error message in Synplify syntezis with SystemVerilog code?

I write some library module on SystemVerilog. I want to check input parameters on synthesis and then if their values are wrong I want to stop synthesis with a custom error that will tell which ...
user avatar
  • 1,784
0 votes
0 answers
57 views

ModelSim can not simulate my VHDL code

I am learning to program FPGAs and my code is compiled in Quartus prime but my .do file does not simulate in ModelSim. Any help is appreciated. ...
user avatar
0 votes
1 answer
54 views

Change clock frequency from 50MHz to 40MHz using Altera Cyclone IV and Quartus Lite 20.1

I'm using the FPGA board EasyFPGAv2.2 which have Altera Cyclone IV with chip EP4CE6E22C6 and I made a verilog program to generate VGA 640x480 60Hz signal. It works great dividing 50MHz by 2 generating ...
user avatar
0 votes
0 answers
372 views

How to open pin planner in Xilinx Vivado?

I am an Intel Quartus user getting to know Xilinx Vivado. I am using Xilinx Vivado for the first time. I am using Digilent ARTY S-7 FPGA board for learning purpose. I am have created a blinking LED ...
user avatar
  • 9,669
0 votes
1 answer
36 views

How to see the conections in a decoder Quartus II web edition

I have a decoder whos 16 bit output is conecting to a one bit input. Acording to my knowldge of the design it would make sense. How can i know which output port of the decoder is conecting to that ...
user avatar
0 votes
0 answers
38 views

Automatic launch of a tcl script at start of Quartus PlatformDesigner

Intel Quartus supports tcl scripts automation - specifically three specific options where user may define variables in the project file to automatically invoke custom tcl scripts at given points of ...
user avatar
0 votes
0 answers
38 views

Manually override Quartus Fitter/Pin Assignment constraints

I have a design that I want to synthesize for / upload to a Max 10 FPGA. One of the inputs goes to a PLL. Quartus now claims, that the neighbouring IO pin is too close to the PLL input pin and won't ...
user avatar
  • 121
0 votes
0 answers
311 views

How to form a 8-Bit bidirectional shift register using two 4-bit bidirectional shift registers?

I really had some trouble with one design question in my homework (the deadline has passed). We were asked to design a 4-bit bidirectional shift register using D-Flip flops and after that to create a ...
user avatar
0 votes
1 answer
280 views

Reusing Quartus block schematic symbol file in another project

I am working on a Quartus project, requiring the usage of some designs previously created as block schematic design files in some other Quartus projects. I generated symbol files from the top design ...
user avatar
0 votes
0 answers
1k views

Quartus Prime Lite: Error (209053): Unexpected error in JTAG server -- error code 35 and Error 202940 Can't access JTAG chain with SSH

Today I received a Terasic USB Blaster and I want to program an Altera 10M04SCE144C8G FPGA. I am using the Intel Quartus Prime 20.1.1 Lite Edition installed in Ubuntu 20.04. This FPGA has already been ...
user avatar
0 votes
0 answers
33 views

typing error showing on quartus prime lite?

I am trying for few hours to understand why Quartus Prime Lite keep showing an error when I compile this basic VHDL code, I kept it like this to understand why it is showing an error just by typing!!!....
user avatar
  • 301
0 votes
1 answer
103 views

What is the proper method to become able to connect conduit signals inside Qsys?

Qsys (now known as Platform designer) identifies Avalon MM, Avalon ST, Clock, Reset and some other type of interfaces and makes it trivial to be able to connect them between different blocks. However, ...
user avatar
  • 1,390
0 votes
0 answers
138 views

Unable to generate device simulation libraries from Quartus Prime

I am using Quartus 18.1. I am trying to generate device simulation libraries as per the procedure here: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/...
user avatar
  • 1,390
0 votes
0 answers
55 views

why the D-FF does not use the clock assigned by me Quartus schematic

The schematic given above is a simplified version of a design. But this is enough to explain my problem. As you can see from the schematic, clock signal of second dff is connected to (Q0' & clk). ...
user avatar
0 votes
1 answer
249 views

Problem in adding IP to Platform Designer

I'm new to Platform Designer and I want to add an ALT PLL intel FPGA IP to a Platform Designer project, but after opening Mega wizard plugin manager and setting up the requirements, the IP does not ...
user avatar
0 votes
0 answers
109 views

How can Quartus Prime System Console be used to read/write a whole file?

I want to find a way to read/write whole file from/to my Intel FPGA design. The file being written provides data to be processed and the file being read shall contain the results of the processing ...
user avatar
  • 1,390
0 votes
1 answer
66 views

Connecting a signal to a pin in Quartus

I want to connect a signal in a .v file to a top level pin assigned in the pin planner but I've no idea where to start. I've looked at several guides but as a C programmer this is all quite alien to ...
user avatar
0 votes
0 answers
293 views

Pin assignments do not appear to be assigning in bdf - Quartus 17.1

Following the pin assignment diagram in the device manual for my Max 10 DE10-Lite, I assigned all the correct pins to their associated inputs and outputs as seen below: However, when I go back to my ...
user avatar
0 votes
0 answers
38 views

I want to find out how many Nios processors are on the board that I am linked with using JTAG, how to do this?

I just want to test how many Nios II exist inside the Qsys system and if they are in reset or executing code. Can this be done via the Nios II terminal?
user avatar
  • 1,390
0 votes
1 answer
341 views

Error (10536): VHDL Loop Statement error at InstructionMemory.vhd(31): loop must terminate within 10,000 iterations

Can someone help me solve this problem? Its my code below: ...
user avatar
0 votes
0 answers
258 views

How can I edit my quartus project to work with relative paths?

I have a project in quartus with many files containing full-path-links to other files. I found a way to make it work on my machine with a different location, but that is the cheat way. I would like to ...
user avatar
0 votes
0 answers
269 views

Quartus Prime: Block synthesized away - why?

Doing my very first steps with FPGA. I successfully built an SPI slave (code found somewhere in the web) that receives something and turns an LED (via output SPI_DONE) on my Altera Max10 evaluation ...
user avatar
  • 966
0 votes
0 answers
50 views

What is a feasable design goal for maximum clock frequency (related to setup timing) for a modern CPLD containing the attached circuit?

The CPLD is an Altera MAX V, with speed grade 5 (note that the MAX V comes with speed grades 4 and 5, where 4 is the faster one). The circuit consists of a 5-bit binary up counter where the count ...
user avatar
  • 125
0 votes
0 answers
163 views

Unable to use the VGA port correctly, De1 Soc distorts signal depending on the output pin

This is a followup to my previous question. The code I was using, pin assigmnets and the theoretical timings for VSYNC and HSYNCH were correct. I have used to oscilloscope to look at the signals, ...
user avatar
0 votes
0 answers
119 views

How to know the speed and energy of a particular Digital Design in Quartus-II and DE1-SOC FPGA (Altera)

I did a digital design in Quartus II and my board DE1-SOC FPGA, now I want to read 3 factors: general speed that digital design takes to finish the application, area of the design if it would be a ...
user avatar
  • 225
0 votes
0 answers
797 views

How to view wire values in Altera Quartus Prime

I would like to be able to view waveforms showing internal nodes in a circuit specified in Verilog in Altera Quartus Prime. I am having trouble doing so when a wire is an output of one module and an ...
user avatar
0 votes
2 answers
91 views

Unexpected change when reading input signals in a VHDL Finite State Machine

I implemented a FSM in vhdl using two processes; A sync process for state transition ...
user avatar
  • 7