Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Intel FPGA (formerly Altera).

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How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
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Cyclone IV FPGA: How to use nCSO pin (101) as normal I/O pin?

(I'm new to this -- so sorry if this is a dumb question). I've got a RZ-EasyFPGA dev board with a built in VGA port. I want mess around with generating a simple VGA signal. Dev board pin-out: I ...
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1answer
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Quartus Prime: Automatically program .sof file after compilation

I found a resource on Automatic Script Execution so I know how to create a .tcl script that executes when compilation is complete. I'd like to know what needs to be in that .tcl script to ...
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How to assign constant value to bus in Quartus II schematic editor?

No matter what I try, Quartus just spams errors similar to this: Error (12009): Node "modulus[31]" is missing source
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Quartus produces different synthesis for same design

I synthesized my design in Quartus for Arria 10 in a remote server. In my memory instantiation, it is saying that it is unable to infer a Block RAM due to asynchronous reads. I tried to synthesize ...
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How can i export synthesized netlist from Quartus 2?

I need to get a netlist that creates by synthesis and optimization from different hdl languages in Quartus 2. I need a netlist in basic logic. Rtl viewer shows me something similar, but i need it in ...
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1answer
175 views

Easiest way to instantiate a transceiver in Quartus to avoid unused channel degradation

This answer in the altera knowledge base indicates that the TX channels on the Arria 10 degrade over time if left unused. I have added the recommended assignment to my QSF file, but it has no effect ...
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272 views

What is the significance of sensitivity list?

I implemented BCD counter using JK Flip_Flop. While implementing I missed to add "reset" to the sensitivity list of JK-FlipFlop. Because of that my simulation result appeared like this. Later I ...
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Change CatapultC RTL naming scheme

I hope someone is familiar with Catapult - available tags make it seem unlikely. My issue is that I have two blocks (as seen in Quartus) being worked on independently, separate RTL. Unfortunately, ...
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8 views

How exactly does the AvalonMM interconnect work using all the pieces that it has?

When looking into the "memory-mapped interconnect" in Qsys for my system, I can see many components that are inserted by Qsys when the system is generated. These are all part of the Qsys ...
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Is it possible to limit the address space accessed by a master using the Avalon-Memory Mapped bus?

Provided that a slave is shared by multiple masters which connect to the same slave's Avalon-MM slave port in Qsys, is there a way to control the read/write access to certain address locations inside ...
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48 views

Synchronizing an asynchronous interface without a clock

I am trying to implement a custom bridge between a clocked synchronous interface and an asynchronous interface which is not clocked. I am having difficuties in synchronizing the asnychronous interface....
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Is there a standard way to extract the base addresses in Qsys SOPC info file into a VHDL file?

For an FGPA fabric AvalonMM master, it is very important that the base addresses be correctly defined in a HDL source file so it can make use of them. The base addresses can change easily as we make ...
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Error while building project in Quartus with Eclipse tool

I'm pretty new to the forum so if something is wrong with the question, sorry in advance. Currently, I'm working on a free project for school. My teammates and I decided to make a 'drawing glove'. ...
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32 views

Interface mpu6050 with de2-115 board i2c

I'm currently working on a project for school. My teammates and I want to make a magic glove, that can draw on a VGA monitor with data from an accelerometer and gyrosensor. Therefore we are using a ...
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34 views

Connecting a signal to a pin in Quartus

I want to connect a signal in a .v file to a top level pin assigned in the pin planner but I've no idea where to start. I've looked at several guides but as a C programmer this is all quite alien to ...
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What is the easiest way to simulate and experiment with FPGA using simulated external DDR3?

For a computer architecture school project I have to implement an algorithm in verilog, such design have to input and output a VERY large ammount of data that wouldn't fit in on-chip memory, hence I ...
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28 views

What are <device_name>@<device_index> to quartus_pgm?

I am trying to download the firmware of a MAX 10 FPGA with the "examine" operation. The help for the command line interface quartus_pgm to Quartus Prime says ...
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Multiplexer Simulation failed in Quartus II Web Edition 15.0

I'm currently working on some assignment for digital electronics. Before this, as in , before I reformat my laptop, everything works just fine. After that, After i reinstall Quartus II, the same ...
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How to force arbitrary vector in Quartus II schematic editor?

So let's say I have a block in my schematic diagram which requires multi-bit input, and I want to drive it with arbitrary vector, say 0b0001 or 0b0000. For a single bit input, I would simply use VCC ...
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130 views

Quartus II: USB Blaster not found, even after installing the driver

I've purchased this USB blaster: https://www.amazon.com/dp/B07F5H5LPZ/ Because I have this Ep2c5/ep2c8 dev board, I've been following this video to begin my work with FPGAs: https://www.youtube.com/...
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Pin assignments do not appear to be assigning in bdf - Quartus 17.1

Following the pin assignment diagram in the device manual for my Max 10 DE10-Lite, I assigned all the correct pins to their associated inputs and outputs as seen below: However, when I go back to my ...
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Quartus Prime Syntax Check Only

I have a variable in my code where I can change "modes". Some (timer and counter) values are reduced and I can run in Modelsim and enjoy the fast error checking. Currently, I need Signal Tap for real ...
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1answer
66 views

PIN Placement Errors In Quartus

So I am writing a simple blinking LED Verilog code that will be run on a Cyclone10 LP (Device is called 10CL025YU256I7G) and will be tested on a Cyclone 10 Evaluation Kit (6XX-44504R-0D) All code is ...
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Quartus Prime design input/output array

I'm designing a decoder 3:8 and I would like to make an input/output array of it. How can I do it with the right sequence of ports?
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Problems with Memory Initialization in Quartus

I have the following code snippet in my VHDL code to initialize a ROM block: ...
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35 views

I want to find out how many Nios processors are on the board that I am linked with using JTAG, how to do this?

I just want to test how many Nios II exist inside the Qsys system and if they are in reset or executing code. Can this be done via the Nios II terminal?
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28 views

How to initialize/load Intel HBM memory in simulation

I am trying to simulate the Intel HBM example design using ModelSim. Is there a way to initialize/load the HBM memory with some data before the simulation? If so, how can we do it?
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What is purpose of the “assignments” in the Qsys custom component editor signals and interfaces tab?

Here is the image showing what I am talking about, For Avalon Memory Mapped Slave port I can see that there are 4 options already there and they are already assigned custom values. I just want to ...
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433 views

How to use tcl script to generate Qsys system inside Quartus?

When I change .vhd files I need to regenerate Qsys and then compile the design. How can I use tcl commands inside Quartus to regenerate the Qsys and then compile the project as well?​ Is there a way ...
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151 views

Error (10536): VHDL Loop Statement error at InstructionMemory.vhd(31): loop must terminate within 10,000 iterations

Can someone help me solve this problem? Its my code below: ...
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132 views

How can I edit my quartus project to work with relative paths?

I have a project in quartus with many files containing full-path-links to other files. I found a way to make it work on my machine with a different location, but that is the cheat way. I would like to ...
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142 views

Quartus Prime: Block synthesized away - why?

Doing my very first steps with FPGA. I successfully built an SPI slave (code found somewhere in the web) that receives something and turns an LED (via output SPI_DONE) on my Altera Max10 evaluation ...
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1answer
909 views

Set input low or high in Quartus

I have created a 4 bit register in VHDL, within Quartus. Normally, I connect each of my inputs to one of the dip switch pins or push button pins in the "pin planner" for my particular development ...
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447 views

Weird quartus waveform diagram from JK flip flop schematic diagram

I tried building a JK flip flop from logic gates. This is my schematic design: However, my waveform for the case J=1, K=1 does not have the Q toggled. Instead, Qnot just copied completely CLK in that ...
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46 views

What is a feasable design goal for maximum clock frequency (related to setup timing) for a modern CPLD containing the attached circuit?

The CPLD is an Altera MAX V, with speed grade 5 (note that the MAX V comes with speed grades 4 and 5, where 4 is the faster one). The circuit consists of a 5-bit binary up counter where the count ...
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792 views

Modelsim: Unresolved defparam reference to somewhere

In Quartus ii schematic diagram, i've generated an lpm_ff. Then i've converted the design to a .v file. when i want to use this ...
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147 views

Unable to use the VGA port correctly, De1 Soc distorts signal depending on the output pin

This is a followup to my previous question. The code I was using, pin assigmnets and the theoretical timings for VSYNC and HSYNCH were correct. I have used to oscilloscope to look at the signals, ...
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How to know the speed and energy of a particular Digital Design in Quartus-II and DE1-SOC FPGA (Altera)

I did a digital design in Quartus II and my board DE1-SOC FPGA, now I want to read 3 factors: general speed that digital design takes to finish the application, area of the design if it would be a ...
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589 views

How to view wire values in Altera Quartus Prime

I would like to be able to view waveforms showing internal nodes in a circuit specified in Verilog in Altera Quartus Prime. I am having trouble doing so when a wire is an output of one module and an ...
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VHDL gate level simulation using quartus prime lite edition, error

I've designed an adder and the related testbench. I've run the RTL simulation, and it works as I expect, however I can't run the gate level simulation. adder.vhd ...