Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Altera.

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20
votes
5answers
8k views

Can FPGA out perform a multi-core PC?

I don't understand how FPGA can be used to accelerate an algorithm. Currently I'm running a time consuming real time algorithm on a quadcore laptop so that four computations can be done in parallel. ...
6
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2answers
1k views

Improve Quartus partial compile or recompile time

I run Altera Quartus, and I'm using the SignalTap logic analyzer on a Max 10 FPGA. It takes tens of minutes to compile, and every time I'd like to add a signal to SignalTap, I have to compile again. ...
5
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4answers
12k views

Generating pulse train of varying frequency on an FPGA

I am working on generating a pulse train to control a motor that accepts a pulse train as an input. Each pulse corresponds to a pre-set movement increment; I can set one pulse equal to 1/1000 degree (...
5
votes
3answers
5k views

Setting FPGA pins as virtual

I have a Verilog module for which I want to check its timing in isolation to the rest of the system. The problem is that the FPGA has a limited number of physical pins, and my module has more inputs ...
5
votes
1answer
4k views

Free linting tool for Verilog

Is there an opensource linting tool for Verilog. I've seen HDL companion and other but they all come with a price tag.
4
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3answers
4k views

Altera FPGA I/O weak pull ups

In altera FPGA documentation they make reference to a "I/O weak pullup" functionality. I would like to use internal weak pull up instead of external pullups , avoiding a PCB modification. It seems ...
4
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2answers
5k views

Quartus II: Where are the worst-case paths?

In the Quartus II settings (under TimeQuest timing analyser), I have checked the Report worst-case paths during compilation checkbox. However, I do not see any ...
4
votes
2answers
126 views

Inherent Pseudo-Randomness in modern FPGA design tools

Do Place & Route algorithms of modern FPGA design tools ( Qaurtus / Vivado / etc... ) have inbuilt randomness in them ? I.E: Would it be possible to get 2 different results when compiling the ...
4
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3answers
6k views

How to efficiently implement a single output pulse from a long input on Altera?

I have a fast clock and a switch called 'ready'. When the switch is flipped (ready goes HIGH), I would like the output pcEn to produce a pulse that lasts only for one clock cycle. pcEn will only ...
4
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2answers
306 views

Quartus II: Customise compiler messages

I am working with the Altera Quartus II compiler for my Cyclone IV. I am not happy with what is considered Info, Warning, ...
4
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2answers
3k views

FPGA encoder counter running away randomly

I am programming an Altera FPGA using Quartus II v9.0 to count encoder pulses and output that count to an external LabVIEW program (see diagram below). I was able to debug one issue with my code ...
4
votes
1answer
789 views

How do I make use of multipliers to generate a simple adder?

I'm trying to synthesize an Altera circuit using as few logic elements as possible. Also, embedded multipliers do not count against logic elements, so I should be using them. So far the circuit looks ...
4
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1answer
1k views

Altera's DRAM Controller with UniPHY

I am trying to port a design from Xilinx to Altera, and I have issues with the DRAM controller IP (for a Cyclone-V and a LPDDR2 mem). I have managed to generate the IP, but I don't understand which ...
3
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2answers
1k views

Quartus: What is the purpose to “register output port” when RAM or ROM megawizard?

The RAM and ROM megawizards in Altera Quartus II give the following option in the GUI "Which ports should be registered?" The options vary but are: ...
3
votes
1answer
6k views

Altera Quartus “Warning (18236): Number of processors has not been specified…”, how to suppress?

My Altera Quartus builds show this warning... ...
3
votes
1answer
978 views

Reason behind Altera's divide functions pipeline delay?

In Quartus II, the standard lpm_divide function has a parameter PIPELINE_DELAY. The default value is floor(WIDTH_Q div 2) - ...
3
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4answers
391 views

Synthesis Result : RTL vs Technology Map Viewer

I am evaluating this code below. But I saw that the logic output of the RTL and Technology Map Viewer are different. I use Quartus Prime Elite Edition. Am I missing something? this is the truth table ...
3
votes
1answer
1k views

VHDL code compiling on quartus II

Look at this piece of code (flip image on X) ...
3
votes
1answer
6k views

Specify include path in Quartus II

I'm compiling Verilog using the Quartus II for the Altera platform. In my Verilog, I have a Verilog header global.vh, and Quartus II cannot find it: ...
3
votes
3answers
5k views

Quartus II - Can I include other files into a *.qsf file?

An Altera Quartus II project consists of one *.qpf and one or more *.qsf files. The qsf seems to be a TCL script like other EDA related settings and config files (e.g. xdc, sdc, ...). Is is possible ...
3
votes
2answers
537 views

VHDL - Flip Flop inferring on a signal

I have to design a circuit to count up to a number and return to zero. It must have a carry signal (which I named a_o in my circuit) as flag to show that the ...
3
votes
1answer
238 views

Grouping input and output signals with the corresponding clock

In my Verilog design, I have two asynchronous clocks, clk1 and clk2. Associated with each clock is a bunch of inputs and outputs....
3
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2answers
8k views

Can we run Quartus II on Ubuntu?

I can compile digital components and download them to the boards DE2 and DE2-115 I got. I do it from Windows 7 but I want to enable this on ubuntu while the files from Altera are for Red Hat Linux. I'...
3
votes
1answer
300 views

Altera Cyclone II Quartus II JTAG Programming Error

I'm trying to program a Cyclone II I bought here using Quartus II 13.0sp1 on Arch Linux. I'm trying to program it with a very simple Verilog program with three inputs and two outputs and a few simple ...
3
votes
1answer
613 views

Constraining the reset line

I am using Quartus II to compile my Verilog design, and I'm working to properly constrain my signals. I know how to constrain clocks, for example: ...
3
votes
1answer
313 views

VHDL - Subtype or type has null range

What is the meaning of the following warning (raised by Quartus)? ...
3
votes
4answers
5k views

How to speed up Modelsim simulation

How can I get Modelsim to run faster for simulation rather than something in the picosecond range (time interval)? Are there any other methods for speeding up simulation? It takes 45 minutes to get ...
3
votes
2answers
472 views

Quartus FPGA migration issues

I have an FPGA design Quartus that compiles and works correctly for a cyclone IV EP4CE15F17C8 (42% used). I'm trying to migrate same design to a smaller FPGA EP4CE10F17C8, but when changing FPGA ...
3
votes
1answer
768 views

How to assign clock/reset to sram in Quartus?

I'm building a system in Quartus according to this question How to upgrade a Quartus II project from SOPC to QSys? Now a part of the problem is how to assign clock/reset pins to my sram. In Quartus ...
3
votes
1answer
189 views

Custom SOPC Builder Components in Quartus II

I am trying to understand how to interface with a custom component within SOPC builder. Basically I have a verilog module which creates and outputs a tone to the audio out line on an Altera DE2 ...
3
votes
1answer
108 views

What is the proper methodology to create portable FPGA designs?

FPGA designs may contain RTL along with IP blocks. These IP blocks most likely shall be from the vendor of the FPGA. Examples of such IP blocks are instantiating dual clock FIFOs, floating point and ...
2
votes
2answers
14k views

How do I generate a schematic block diagram from Verilog with Quartus Prime?

The answers to this question say that Altera Quartus will generate block diagrams from Verilog files. I'm a user of Quartus Prime Lite Edition. How do I generate block diagrams?
2
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2answers
3k views

What is the I/O standard for the PCIe data lines?

I am entering the pin information of my FPGA design using the Altera Quartus II PinPlanner. One of the components of my design is PCIe, and I am having troubles understanding the "I/O standard" ...
2
votes
2answers
3k views

What is the standard way to represent fixed point numbers in VHDL?

Is there a native type in VHDL language similar to std_logic_vector that allows one to create a signed or unsigned fixed point number for given length of fractional and whole parts? If so, can it be ...
2
votes
1answer
811 views

Why don't my programs stay in the FPGA MAX 10 after a power cycle? [closed]

I program my FPGA (MAX 10) with a .sof file and works, but when I turn off my device everything erases from my FPGA. After exploration on the internet I found the EPCS IC, and I find out my board ...
2
votes
1answer
6k views

Bus to wire in quartus

I sometimes run into a problem with altera's Quartus that I would like a better solution to. Sometimes I use the graphical interface for design and I have a bus that I would like to pull off just one ...
2
votes
1answer
149 views

Benefits of using Altera IP in FPGA designs?

I've just started using Quartus to synthesize a VHDL design that I created a while ago. Inside of this design are things like DFFs, decoders, etc. I noticed that Altera has IP of its own with the same ...
2
votes
1answer
763 views

Set toggle rate in Quartus II

According to this document, I need to: assign 0 MHz toggle rate to Toggle Rate assignments for the pin in the Assignment Editor to place a non-differential pin ...
2
votes
3answers
7k views

Using VHDL code to design a JK Flip Flop

I'm using quartus II to design a JK Flip Flop. However, my results show unknown output. Why is it? Intended design circuit: VHDL code: ...
2
votes
2answers
606 views

Which files are required to copy / version my Quartus project?

I created a 4-bit CPU in latest version of Quartus. Now I wonder which files are necessary if I want to put the files in source control? I understand that bdf, sof and qpf files should be versioned. ...
2
votes
3answers
357 views

View more than 100 worst-case paths in Quartus II

I am using Quartus II to compile Verilog for my FPGA project. For debug, I use SignalTap, which introduces a lot of timing warnings. When I go to the TimeQuest report, and look at the worst-case ...
2
votes
1answer
356 views

Weird output Pulse in Vector Waveform in Quartus 2

I have an obscure output pulse in my output waveforms for my half-adder. Is it because that the inputs are both high at 40ns? So I should slightly delay b going high after a has gone low? The time ...
2
votes
1answer
3k views

Quartus II ignoring synthesis attribute noprune

There is a register in my design that I am using for debug purposes with zero fan-out. Since it isn't driving any logic, the synthesizer optimizes it away. However, as far as my knowledge goes, ...
2
votes
1answer
833 views

What is a safe state machine?

When I implement a "safe" state machine in Quartus, what is the difference between a normal/unsafe state machine? Edit: And is this the same as: ...
2
votes
3answers
558 views

Does setting pins as virtual affect timing?

I have a Verilog submodule which I am testing independently. This module has too many top level pins to fit in my FPGA, so I have set some of the pins as virtual so that it would compile without ...
2
votes
1answer
5k views

How can I avoid “Minimum Pulse Width” slack violations in Quartus FPGA synthesis?

I am synthesizing a toy application on DE2, but I hit a timing problem (despite every inputs and outputs are clocked in my design). These violations are related to "minimum pulse width"... How can I ...
2
votes
1answer
10k views

Why do I get a Top Level Design Entity undefined in my VHDL

I'm building an 8-bit register from d-type flipflops in VHDL for a lab exercise but I can't seem to diagnose a problem. Firstly I can't get it to compile because of the difference in types for the ...