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Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Altera.

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35 views

I want to find out how many Nios processors are on the board that I am linked with using JTAG, how to do this?

I just want to test how many Nios II exist inside the Qsys system and if they are in reset or executing code. Can this be done via the Nios II terminal?
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911 views

FPGA starts working after irrelevant changes, why?

I have written a UART module in Verilog. By using that module I get data from PC via UART and then send that data back again via this UART module. I uploaded it to FPGA for testing. It works flawless ...
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RTL Simulation Error, Can't Launch ModelSim

I am new on FPGAs so I am using the Altera Cyclone II EP2C5T144 The Quartus Prime version that supports Cyclone II is 13.0 ; I am trying to run a very simple code to turn on a LED ...
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20 views

How to initialize/load Intel HBM memory in simulation

I am trying to simulate the Intel HBM example design using ModelSim. Is there a way to initialize/load the HBM memory with some data before the simulation? If so, how can we do it?
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16 views

What is purpose of the “assignments” in the Qsys custom component editor signals and interfaces tab?

Here is the image showing what I am talking about, For Avalon Memory Mapped Slave port I can see that there are 4 options already there and they are already assigned custom values. I just want to ...
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49 views

Why are VHDL “external names” that are used to create alias to signal at another level of hierarchy, not synthesizeable?

I am using Quartus 18.0 and have set the settings for VHDL-2008. However, when I try to compile a trivial project where one "external name" signal exists, I get this error: Error (10500): VHDL syntax ...
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50 views

Measuring the external memory power consumption in FPGAs?

I am trying to get a power/energy breakdown of DDR3 and core logic. I used Quartus power analyzer tool to get the power estimates, but I am not sure whether it includes the power consumption of ...
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82 views

How do D flip-flops (dff) start up in Quartus?

If I connect Q0 of one dff to its D0, its Q0 stays 0. But if I take another dff and connect its Q1 with Q0 of the first dff through OR to his D1, its Q1 stays 1. I understood that all registers are ...
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36 views

Is it possible to add an existing IP variant to a Platform Designer/Qsys system through TCL?

I have a .ip file that contains a parameterized component which I'd like to use in my Qsys system. I can add the component via the GUI but I would like to be able to add it via TCL or another ...
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69 views

How to assign different pins in Pin Planner in Quartus?

I am trying to make the 7 segment display of my FPGA work. I found some working code, but I got issues with the pin planner. The FPGA is this, a knockoff Altera Cyclone IV E EP4CE6E22C8. The code : <...
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155 views

Why is this VHDL pseudo random number generator not working as expected?

I'll start off by saying I have about 2 days experience in VHDL so there's a strong chance my code is horrible. I would appreciate any tips on better VHDL practice. I am busy trying to simulate a ...
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62 views

VHDL: case when using constants constructs

I'm having some trouble with the following statement ...
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19 views

Quartus Prime Lite: Generate a 25.18 MHz clock and Constrain to clock input in HDL

I am trying to use a generated clock in .sdc to drive my logic in my DE1-SoC Cyclone V chip. When I load the design onto the chip currently, nothing happens. My counter led does not even blink to show ...
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95 views

Error in simulating bdf with Waveform.vwf.vht, but bdf compiles successfully

I am trying to design an instruction register and controller for an ALU that I designed previously. I made the register with 2 muxes and 2 D flip-flops, and I made the controller with a T flip-flop ...
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105 views

Why is my seconds counter in verilog jumping values behaviour?

I am implementing a seconds counter on the Altera DE-1 Educational Board powered by the old Cyclone 2 FPGA. My plan is to make a 'down-clocker' that takes the on-board 50 MHz clock and produces a 1 Hz ...
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176 views

How to use tcl script to generate Qsys system inside Quartus?

When I change .vhd files I need to regenerate Qsys and then compile the design. How can I use tcl commands inside Quartus to regenerate the Qsys and then compile the project as well?​ Is there a way ...
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38 views

How can Qsys component configuration be accessed in software?

I'm designing a Qsys component which I want to be user-configurable. It has config parameters which are defined in the TCL file. For example, for a GPIO bank component I would write: ...
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73 views

Error (10536): VHDL Loop Statement error at InstructionMemory.vhd(31): loop must terminate within 10,000 iterations

Can someone help me solve this problem? Its my code below: ...
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98 views

PLL with input depend output CLK

Is it possible to generate a PLL that has the same clock frequency at the output as the input clock has, but with a phase shift? The output clock should also change if the input clock has changed. In ...
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77 views

altera FPGA acting like OR gate when programed as AND gate

I'm new to altera fpga , I've bought development board based on EP4CE6E22 cyclon IV and tryed to program it with basic program in quartus environment ...
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47 views

Can't achieve requested … bandwidth type?

I have two cascaded PLLs in the design, and read here that it is the best to set first PLL into low bandwidth, and second PLL into high bandwidth in order to decrease jitter accumulation. I had "Auto" ...
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135 views

Why doesn't my verilog state machine toggle state?

I have written a state machine in Verilog. However, when I try to simulate it with my testbench, it does not advance from the STATUS_IDLE state to the STATUS_READY state. Why isn't the state machine ...
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153 views

Inherent Pseudo-Randomness in modern FPGA design tools

Do Place & Route algorithms of modern FPGA design tools ( Qaurtus / Vivado / etc... ) have inbuilt randomness in them ? I.E: Would it be possible to get 2 different results when compiling the ...
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regarding bidirectional accessing of array in verilog

Accessing ram logic in Verilog with an initial block gives an error "cannot synthesize initialized RAM logic <name> " A part of the code will be as follows (...
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134 views

For a Quartus project what files must be added to a git repository?

A Quartus project generates huge number of files as we proceed with design compilation and debug automatically. Provided that I wish to add my Quartus project to a Git repository and not just the hdl ...
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114 views

FPGA too slow for my ripple carry adder?

I wanted to make simple LED counter on my FPGA board (Cyclone IV EP4CE). I've made (from scratch - from NANDs) 4bit counter and 26 bit one. I have 26bit signal that is wired (port map) into 26 bit ...
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27 views

In Intel Quartus Static Timing Analyzer should -ve setup slack on a path in Slow_900mV_0C model also show up in Slow_900mV_100C model?

I am trying to understand why the paths with -ve slack in Slow_900mV_0C model do not show up in Slow_900mV_100C model. I am using Arria 10 GX. I would think the process part of the model is likely ...
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103 views

What's the actual cause of unbalanced combinational logic?

So far when I find timing issues, I try to pipeline combinational logic. It always works. Today, my Quartus Compilation Report show up -ve slack values. I double check it with TimeQuest Timing ...
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85 views

How can I edit my quartus project to work with relative paths?

I have a project in quartus with many files containing full-path-links to other files. I found a way to make it work on my machine with a different location, but that is the cheat way. I would like to ...
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229 views

Bug in my SPI implementation (VHDL)

I'm new to VHDL/FPGA programming and I experienced some weird behavior in my SPI-Slave implementation. What I did: SPI-Master: I'm using an Arduino (ATMega328p MCU) as the SPI-Master. For debugging, ...
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29 views

Why does functional simulation generate Zs?

I have a very simple project, I share the files in this github repo If I run a functional simulation (Waveform.vwf in the repository) I get some 'Z' in the value of an internal register, see the ...
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72 views

Quartus Prime: Block synthesized away - why?

Doing my very first steps with FPGA. I successfully built an SPI slave (code found somewhere in the web) that receives something and turns an LED (via output SPI_DONE) on my Altera Max10 evaluation ...
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19 views

Is there a way for Quartus System Console to get base addresses of memory mapped peripherals from the sopc file?

The Quartus System Console is a powerful tool when it comes to design verification. We can use tcl script to read/write memory mapped slaves. I have noticed that in the examples I have seen so far, ...
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20 views

Why doesn't Qsys force all peripherals (and masters) to use fixed data width of say 32 or 64 bits?

In Qsys, the address space is byte addressable. However, the datawidth of the master shall most likely be more than a byte. This could create a situation where sometimes a peripheral has wider data ...
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292 views

How do I know if not using FPGA dedicated clock input for a PLL pin is bad for my design?

PLLs are hard blocks in silicon. They are connected to specific pins for their clock input and drive specific pins for clock output. It is possible that we choose a "non-dedicated" pin for clock input/...
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26 views

Can specific pipeline latency arithmatic block be inferred when using * or / operator in VHDL?

When using the * or / in VHDL, the synthesis tool shall infer the appropriate IP block to carry out that operation. If we open the actual GUI for that IP block we can find a lot of options e.g select ...
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116 views

What is the proper methodology to create portable FPGA designs?

FPGA designs may contain RTL along with IP blocks. These IP blocks most likely shall be from the vendor of the FPGA. Examples of such IP blocks are instantiating dual clock FIFOs, floating point and ...
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88 views

Get more AS-attached flash chip information from ALTASMI

I am playing with the attaching various configuration flash devices to the Altera Cyclone 3. In particular, I want to replace EPCS16 (2MB) with W25Q128 (16MB) - for both size and cost reasons. Is ...
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90 views

74193 stops working after compilation on another PC (QUARTUS)

I got a Quartus project with a mod 22 counter using 74193 from a friend. It works just fine when I run a simulation before a compilation on my PC, but after I compile it on my PC, it stops working ...
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328 views

Error (10028): Can't resolve multiple constant drivers for net “rf[7][XX]” at registerfile8x32.v

Hello Im making a register file 8x32 in verilog, the sim looks good but when I compile on quartus it makes Error (10028): Can't resolve multiple constant drivers for net "rf[7][31]" at ...
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60 views

SDC constraints for reusable component

I have a simple register based clock divider component I can drop in when I don't have a spare PLL: ...
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380 views

Altera Cyclone II Quartus II JTAG Programming Error

I'm trying to program a Cyclone II I bought here using Quartus II 13.0sp1 on Arch Linux. I'm trying to program it with a very simple Verilog program with three inputs and two outputs and a few simple ...
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750 views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
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414 views

Altera-Modelsim simulation wont start when I add a module instance in my main testbench module

Edit: it is something with the simulate_camera_output module that Modelsim doesn't like. Tried with a simple test module and it works fine. Looking for a way to ...
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83 views

1 Byte Register broken into 2 Nibble outputs not working VHDL/ModelSim

I have made a 1 byte instruction register in VHDL. Instead of having a 1 byte output, I have created an upper nibble output and a lower nibble output. The lower nibble output is special because it ...
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186 views

Negative Edge Trigger and Asynchronous Clear not working in ModelSim

I have created a 4 bit counter with the following inputs and outputs clockN: active low clock clearN: active low clear cP: When high, the counter counts. When low, the counter stays the same. eP: ...
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217 views
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633 views

Error (suppressible): (vsim-3601) Iteration limit Quartus

I have created a Simulation of a 4 bit register in quartus. Each of the four D flip flops test fine by themselves, but when I test 4 of them connected together into a register, I get the "Error (...
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608 views

Set input low or high in Quartus

I have created a 4 bit register in VHDL, within Quartus. Normally, I connect each of my inputs to one of the dip switch pins or push button pins in the "pin planner" for my particular development ...