Questions tagged [quartus]

Quartus (and in particular Quartus Prime/Quartus II since the original Quartus is no longer used) is a programmable logic device design software from Altera.

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How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
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1answer
1k views

Quartus Prime: Automatically program .sof file after compilation

I found a resource on Automatic Script Execution so I know how to create a .tcl script that executes when compilation is complete. I'd like to know what needs to be in that .tcl script to ...
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2k views

How to assign constant value to bus in Quartus II schematic editor?

No matter what I try, Quartus just spams errors similar to this: Error (12009): Node "modulus[31]" is missing source
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41 views

How I can resolve the problem of conversion (to_integer(unsigned(variable))

I want to solve a problem in VHDL with Quartus II. I made a model of VGA protocol 640/480. When I made the part of displaying I made one two signal in integer. Error (10621): VHDL Use Clause ...
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103 views

What's the actual cause of unbalanced combinational logic?

So far when I find timing issues, I try to pipeline combinational logic. It always works. Today, my Quartus Compilation Report show up -ve slack values. I double check it with TimeQuest Timing ...
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1answer
724 views

Is it possible to change the size and look of blocks/symbols in Quartus Schematic Editor

I want to change shapes of and resize blocks/symbols to make the schematic tidier. For example, I want to make my multiplexers the shape of a trapezoid (like commonly drawn on paper) and make them ...
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1answer
131 views

Easiest way to instantiate a transceiver in Quartus to avoid unused channel degradation

This answer in the altera knowledge base indicates that the TX channels on the Arria 10 degrade over time if left unused. I have added the recommended assignment to my QSF file, but it has no effect ...
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260 views

What is the significance of sensitivity list?

I implemented BCD counter using JK Flip_Flop. While implementing I missed to add "reset" to the sensitivity list of JK-FlipFlop. Because of that my simulation result appeared like this. Later I ...
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49 views

Change CatapultC RTL naming scheme

I hope someone is familiar with Catapult - available tags make it seem unlikely. My issue is that I have two blocks (as seen in Quartus) being worked on independently, separate RTL. Unfortunately, ...
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35 views

I want to find out how many Nios processors are on the board that I am linked with using JTAG, how to do this?

I just want to test how many Nios II exist inside the Qsys system and if they are in reset or executing code. Can this be done via the Nios II terminal?
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20 views

How to initialize/load Intel HBM memory in simulation

I am trying to simulate the Intel HBM example design using ModelSim. Is there a way to initialize/load the HBM memory with some data before the simulation? If so, how can we do it?
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16 views

What is purpose of the “assignments” in the Qsys custom component editor signals and interfaces tab?

Here is the image showing what I am talking about, For Avalon Memory Mapped Slave port I can see that there are 4 options already there and they are already assigned custom values. I just want to ...
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49 views

Why are VHDL “external names” that are used to create alias to signal at another level of hierarchy, not synthesizeable?

I am using Quartus 18.0 and have set the settings for VHDL-2008. However, when I try to compile a trivial project where one "external name" signal exists, I get this error: Error (10500): VHDL syntax ...
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19 views

Quartus Prime Lite: Generate a 25.18 MHz clock and Constrain to clock input in HDL

I am trying to use a generated clock in .sdc to drive my logic in my DE1-SoC Cyclone V chip. When I load the design onto the chip currently, nothing happens. My counter led does not even blink to show ...
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176 views

How to use tcl script to generate Qsys system inside Quartus?

When I change .vhd files I need to regenerate Qsys and then compile the design. How can I use tcl commands inside Quartus to regenerate the Qsys and then compile the project as well?​ Is there a way ...
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1answer
74 views

Error (10536): VHDL Loop Statement error at InstructionMemory.vhd(31): loop must terminate within 10,000 iterations

Can someone help me solve this problem? Its my code below: ...
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47 views

Can't achieve requested … bandwidth type?

I have two cascaded PLLs in the design, and read here that it is the best to set first PLL into low bandwidth, and second PLL into high bandwidth in order to decrease jitter accumulation. I had "Auto" ...
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30 views

regarding bidirectional accessing of array in verilog

Accessing ram logic in Verilog with an initial block gives an error "cannot synthesize initialized RAM logic <name> " A part of the code will be as follows (...
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27 views

In Intel Quartus Static Timing Analyzer should -ve setup slack on a path in Slow_900mV_0C model also show up in Slow_900mV_100C model?

I am trying to understand why the paths with -ve slack in Slow_900mV_0C model do not show up in Slow_900mV_100C model. I am using Arria 10 GX. I would think the process part of the model is likely ...
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87 views

How can I edit my quartus project to work with relative paths?

I have a project in quartus with many files containing full-path-links to other files. I found a way to make it work on my machine with a different location, but that is the cheat way. I would like to ...
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29 views

Why does functional simulation generate Zs?

I have a very simple project, I share the files in this github repo If I run a functional simulation (Waveform.vwf in the repository) I get some 'Z' in the value of an internal register, see the ...
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74 views

Quartus Prime: Block synthesized away - why?

Doing my very first steps with FPGA. I successfully built an SPI slave (code found somewhere in the web) that receives something and turns an LED (via output SPI_DONE) on my Altera Max10 evaluation ...
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19 views

Is there a way for Quartus System Console to get base addresses of memory mapped peripherals from the sopc file?

The Quartus System Console is a powerful tool when it comes to design verification. We can use tcl script to read/write memory mapped slaves. I have noticed that in the examples I have seen so far, ...
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20 views

Why doesn't Qsys force all peripherals (and masters) to use fixed data width of say 32 or 64 bits?

In Qsys, the address space is byte addressable. However, the datawidth of the master shall most likely be more than a byte. This could create a situation where sometimes a peripheral has wider data ...
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26 views

Can specific pipeline latency arithmatic block be inferred when using * or / operator in VHDL?

When using the * or / in VHDL, the synthesis tool shall infer the appropriate IP block to carry out that operation. If we open the actual GUI for that IP block we can find a lot of options e.g select ...
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616 views

Set input low or high in Quartus

I have created a 4 bit register in VHDL, within Quartus. Normally, I connect each of my inputs to one of the dip switch pins or push button pins in the "pin planner" for my particular development ...
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271 views

Weird quartus waveform diagram from JK flip flop schematic diagram

I tried building a JK flip flop from logic gates. This is my schematic design: However, my waveform for the case J=1, K=1 does not have the Q toggled. Instead, Qnot just copied completely CLK in that ...
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42 views

What is a feasable design goal for maximum clock frequency (related to setup timing) for a modern CPLD containing the attached circuit?

The CPLD is an Altera MAX V, with speed grade 5 (note that the MAX V comes with speed grades 4 and 5, where 4 is the faster one). The circuit consists of a 5-bit binary up counter where the count ...
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634 views

Modelsim: Unresolved defparam reference to somewhere

In Quartus ii schematic diagram, i've generated an lpm_ff. Then i've converted the design to a .v file. when i want to use this ...
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141 views

Unable to use the VGA port correctly, De1 Soc distorts signal depending on the output pin

This is a followup to my previous question. The code I was using, pin assigmnets and the theoretical timings for VSYNC and HSYNCH were correct. I have used to oscilloscope to look at the signals, ...
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81 views

How to know the speed and energy of a particular Digital Design in Quartus-II and DE1-SOC FPGA (Altera)

I did a digital design in Quartus II and my board DE1-SOC FPGA, now I want to read 3 factors: general speed that digital design takes to finish the application, area of the design if it would be a ...
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498 views

How to view wire values in Altera Quartus Prime

I would like to be able to view waveforms showing internal nodes in a circuit specified in Verilog in Altera Quartus Prime. I am having trouble doing so when a wire is an output of one module and an ...
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2k views

VHDL gate level simulation using quartus prime lite edition, error

I've designed an adder and the related testbench. I've run the RTL simulation, and it works as I expect, however I can't run the gate level simulation. adder.vhd ...