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Questions tagged [questasim]

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Timing issues in netlist simualtion - SDF simulation of IP block

TOOLs and Tech: Questasim 10.5c-2 / Synopsys design_vision I-2013.12 / STM 65nm Hi I am running some timing simulations on my design and have some doubts and issues with the results. 1- My design is ...
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Is there a way to define enumeration for certain signals after simulation?

I have run some verilog simulations in questa simulator and while viewing the waveforms i see that it would have been easier for me to debug the signals had there been some enums defined for them (To ...
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1answer
228 views

VHDL: reading integers from a text file, storing them in array, and writing in text format again

In a certain simulation testbench using questasim, I am trying to read the files with integers numbers which looks like, ...
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0answers
77 views

VHDL-2008 generic packages for post-fit simulation in QuestaSim

I created a testbench for a VHDL design including integrated circuit models to check interface timing requirements. Within each model, I instantiate a generic package (genpkg) to print detected errors ...
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1answer
64 views

A question about randomization in verilog

I am now working on a verilog testbench file and I want to get a random value in my code, but I have found that Questa Sim uses the same seed again and again. I have read through $random in Verilog ...
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1answer
55 views

Is there a way to suppress the output when compiling multiple vhd files except for errors?

I have a compilation script I run before simulating on QuestaSim 10.7: ...
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0answers
30 views

Simulating one Altera IP causes another to break?

I'm working on a new iteration of a previous design that required a clock domain crossing FIFO and a Viterbi decoder. Both of these are Altera IP. When putting together a testbench, I noticed the ...
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1answer
614 views

VHDL: Non-locally static choice warning

I have the following code: constant HALF_RANGE: unsigned(RANGE_WIDTH-1 downto 0) := (RANGE_WIDTH-1 => '1', others=>'0'); where RANGE_WIDTH is a generic of ...
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1answer
236 views

“Numeric value exceeds 32-bit capacity” error in QuestaSim

In the testbench for a SystemVerilog module, I have the following array declaration and initialization: ...
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1answer
1k views

ModelSim: Why can't I see generics in simulation?

When I start simulation, I can see signals and ports in the objects window for what I have selected in the Sim window. Besides this, I can see processes for the same thing in the processes window. ...