Questions tagged [questasim]
The questasim tag has no usage guidance.
14
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Simulation only code and Synthesis only code in QuestaSim
Pragma exist to tell the synthesis tool to ignore lines or blocks of code, using this:
-- synthesis translate_off
... code to ignore
-- synthesis translate on
...
- 1,557
1
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224
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Multiple wire type objects declaration Verilog
I get an error everytime I try to use the same line to declare more than one wire type, is this because they are of different size (but I get the error even when they're of the same size, declaring ...
- 357
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176
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0
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1
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609
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How to randomize the seed-number in Modelsim?
In EDA-Playground, I know that we use +ntb_random_seed_automatic to randomize the seed number. However, I'm not sure how I'd go about doing that in Modelsim so that I have a random seed number.
I was ...
0
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1
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296
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For QuestaSim, what's the difference between vsim.exe and vsimk.exe? [closed]
For QuestaSim, what's the difference between vsim.exe and vsimk.exe under C:\questasim64_2020.4\win64\vsimk.exe?
for some reason, in order to invoke QuestaSim in batch mode from the Powershell prompt, ...
- 183
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0
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664
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Syntax error in SystemVerilog based UVM testbench
I have been getting the following syntax error on compilation-
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- 9
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1
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700
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Error with Assert statement in Verilog
I have the following assert statement in a for loop, which is within a generate block:
...
- 157
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2
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860
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Is there a way to define enumeration for certain signals after simulation?
I have run some verilog simulations in questa simulator and while viewing the waveforms i see that it would have been easier for me to debug the signals had there been some enums defined for them (To ...
- 29
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3k
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VHDL: reading integers from a text file, storing them in array, and writing in text format again
In a certain simulation testbench using questasim, I am trying to read the files with integers numbers which looks like,
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- 3
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370
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A question about randomization in verilog
I am now working on a verilog testbench file and I want to get a random value in my code, but I have found that Questa Sim uses the same seed again and again. I have read through $random in Verilog ...
- 9
0
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1
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418
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Is there a way to suppress the output when compiling multiple vhd files except for errors?
I have a compilation script I run before simulating on QuestaSim 10.7:
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- 235
4
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1
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4k
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VHDL: Non-locally static choice warning
I have the following code:
constant HALF_RANGE: unsigned(RANGE_WIDTH-1 downto 0) := (RANGE_WIDTH-1 => '1', others=>'0');
where RANGE_WIDTH is a generic of ...
- 2,205
0
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455
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"Numeric value exceeds 32-bit capacity" error in QuestaSim
In the testbench for a SystemVerilog module, I have the following array declaration and initialization:
...
- 828
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2
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2k
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ModelSim: Why can't I see generics in simulation?
When I start simulation, I can see signals and ports in the objects window for what I have selected in the Sim window. Besides this, I can see processes for the same thing in the processes window. ...
- 10.1k