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Can QuestaSim wave view show arrow for signal rising edge? [closed]

Is it possible to customize the QuestaSim wave view so it can show small arrow on the rising edge or calling edge of the clock signal?
quantum231's user avatar
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What is difference between QuestaSim "batch mode" and "command line" mode

Running vsim -h in the terminal reveals these two switches: ...
quantum231's user avatar
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1 answer
53 views

QuestaSim shows internal signals of VHDL module but not SystemVerilog module

So for the first time, I created a SystemVerilog module and testbench in QuestaSim today. I created a project inside QuestaSim and then created a counter and a testbench for the counter. When I ...
quantum231's user avatar
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0 answers
13 views

Questa instantiation during testbench issues

I'm new to EDA and trying to get the hang of simulations in Questa. I wrote the Verilog code "clock_divider" and the testbench "tb_clock_divider". They both compile successfully ...
Raquel's user avatar
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1 answer
70 views

Post Synthesis Simulation in QuestaSim

I am attempting to perform post-synthesis simulation of a Verilog system designed in Vivado on QuestaSim. I am using QuestaSim 2021.2_1 and Vivado 2020.2. Here are the steps I have followed: I ...
Adam01's user avatar
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-2 votes
2 answers
148 views

How can I run Verilog code with data at a specific time in the past?

My simulation takes hours until it's stopped from my SystemVerilog code using $stop;. When it stops, to have proper information, I need to run a Verilog task/...
None's user avatar
  • 372
1 vote
1 answer
78 views

How to stop ModelSim at a condition based on signals?

From the window, I'd like to give a condition in the console when to stop the simulation. I've tried: when {/tb/DUT/sequence==256806} {stop} run -all but it doesn'...
None's user avatar
  • 372
2 votes
2 answers
391 views

(vcom-1136) Unknown identifier "std_logic" & "std_logic_vector"

I am relatively new to VHDL, and I am getting the errors below although I used the same procedure before: ...
Andre_van_stone's user avatar
0 votes
1 answer
442 views

Questasim Unable to find VHDL package not compiled into work

I'm currently trying to simulate a VHDL module with a SV testbench. The VHDL module contains several packages that are compiled into various libraries so in order to avoid compile errors within the ...
EpicFoodCartDestroyer's user avatar
1 vote
1 answer
446 views

Bad default binding, component port not on entity

I am trying to write a testbench for a basic component, but I am getting an error saying: bad default binding for component instance (component port not on entity) I have tried recompiling multiple ...
Baddioes's user avatar
  • 113
-1 votes
1 answer
371 views

Simulation only code and Synthesis only code in QuestaSim

Pragma exist to tell the synthesis tool to ignore lines or blocks of code, using this: -- synthesis translate_off ... code to ignore -- synthesis translate on ...
gyuunyuu's user avatar
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1 vote
1 answer
1k views

Multiple wire type objects declaration Verilog

I get an error everytime I try to use the same line to declare more than one wire type, is this because they are of different size (but I get the error even when they're of the same size, declaring ...
SM32's user avatar
  • 406
2 votes
1 answer
666 views

How to set QuestaSim/ModelSim to print time value in arbitrary unit?

Here is the code: ...
gyuunyuu's user avatar
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0 votes
1 answer
1k views

How to randomize the seed-number in Modelsim?

In EDA-Playground, I know that we use +ntb_random_seed_automatic to randomize the seed number. However, I'm not sure how I'd go about doing that in Modelsim so that I have a random seed number. I was ...
Taher Anaya's user avatar
0 votes
1 answer
522 views

For QuestaSim, what's the difference between vsim.exe and vsimk.exe? [closed]

For QuestaSim, what's the difference between vsim.exe and vsimk.exe under C:\questasim64_2020.4\win64\vsimk.exe? for some reason, in order to invoke QuestaSim in batch mode from the Powershell prompt, ...
pico's user avatar
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0 answers
1k views

Syntax error in SystemVerilog based UVM testbench

I have been getting the following syntax error on compilation- ...
em.'s user avatar
  • 9
2 votes
1 answer
1k views

Error with Assert statement in Verilog

I have the following assert statement in a for loop, which is within a generate block: ...
Lakshya Goyal's user avatar
0 votes
2 answers
1k views

Is there a way to define enumeration for certain signals after simulation?

I have run some verilog simulations in questa simulator and while viewing the waveforms i see that it would have been easier for me to debug the signals had there been some enums defined for them (To ...
ECEVLSI's user avatar
  • 29
0 votes
1 answer
4k views

VHDL: reading integers from a text file, storing them in array, and writing in text format again

In a certain simulation testbench using questasim, I am trying to read the files with integers numbers which looks like, ...
rooter's user avatar
  • 3
0 votes
1 answer
455 views

A question about randomization in verilog

I am now working on a verilog testbench file and I want to get a random value in my code, but I have found that Questa Sim uses the same seed again and again. I have read through $random in Verilog ...
eric yau's user avatar
0 votes
1 answer
534 views

Is there a way to suppress the output when compiling multiple vhd files except for errors?

I have a compilation script I run before simulating on QuestaSim 10.7: ...
Cit5's user avatar
  • 245
4 votes
1 answer
5k views

VHDL: Non-locally static choice warning

I have the following code: constant HALF_RANGE: unsigned(RANGE_WIDTH-1 downto 0) := (RANGE_WIDTH-1 => '1', others=>'0'); where RANGE_WIDTH is a generic of ...
Botnic's user avatar
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0 votes
1 answer
526 views

"Numeric value exceeds 32-bit capacity" error in QuestaSim

In the testbench for a SystemVerilog module, I have the following array declaration and initialization: ...
skrrgwasme's user avatar
1 vote
2 answers
3k views

ModelSim: Why can't I see generics in simulation?

When I start simulation, I can see signals and ports in the objects window for what I have selected in the Sim window. Besides this, I can see processes for the same thing in the processes window. ...
quantum231's user avatar