Questions tagged [ram]
RAM is an abbreviation for Random Access Memory. A type of memory in which the information can be accessed from random location.
311
questions
0
votes
0answers
31 views
How to calculate RAM size from chip markings and number of chips
I have a RAM with 8 TMS44400DJ chips on it. It says the word length is 1048576, so would it mean times 8 I have 8MB RAM on this module?
0
votes
0answers
31 views
Why DDR4 Specs recommend that Address, Control and Clock buses be referenced to VDD?
Micron's Technical Note TN-40-40: DDR4 Point-to-Point Design Guide, page 19, says:
Designs should reference data bus signals to VSS.
CA bus and clock should reference VDD.
Why Command, Address bus ...
0
votes
0answers
34 views
Why IMB 7030 did use byte and word addressing simultaneously [migrated]
In 1950s machines had a 36 bits word. And in this word we could pack symbols using ...
0
votes
0answers
31 views
How to output a determined number of characters in VHDL regardless of the input
I´m working on a code VHDL with a RAM memory which purpose is show me the output data in the TeraTerm software. I enter the data via the Arduino COM window (The Arduino MEGA 2560 is connected to an ...
1
vote
0answers
27 views
lowering voltage of high frequency signal
One of the parts I have is RAM (1.5V logic level).
The hardware communicating with it, is at a 1.8V logic level. The RAM signals are sent quickly - around 350-450Mhz.
So I am pretty sure I can't ...
0
votes
0answers
35 views
Embedded system - copying data from flash to RAM
This question uses some Xilinx-specific terminology.
I'm currently working with a Zynq Ultrascale+ MPSoC (CPU + FPGA in same package). I'm using a QSPI flash chip to hold the CPU configuration code, ...
0
votes
1answer
41 views
Is a metallic conductor within an electrostatic field necessarily subject to discharge?
Basically what I'm trying to determine is if the new RAM chips I received in the mail were potentially damaged from static electricity.
Late last night, tired and foggy, I built up a considerable ...
2
votes
2answers
81 views
What is the probability of a bit error occurring in modern computers?
What is the probability of a bit error occuring when reading/writing from/to the latest memory technologies (ssd, hdd, ram) in modern computers? If the same terminology is used in this context as in ...
1
vote
2answers
126 views
Why does dynamic ram need to be 'refreshed'?
I read this question, but it didn't really answer my question. I also want to preface this question by saying that I'm asking this from the perspective of being a computer science student that took ...
2
votes
2answers
81 views
Access elements randomly in RAM based FIFO VHDL FPGA
The thing is: new data is being generated every "time step" that can be few clock cycles. So I want to store the data generated for few time steps in a "buffer". The data must be stored like in a ...
0
votes
5answers
199 views
Why are bytes 8 bits? (and more)
An 8 bit value can range anything from 0 to 255 in decimal, or 00 to FF in hexadecimal. But why did they choose 8 bits for the byte, out of all of the powers of 2 they could have chosen? Even still, a ...
1
vote
3answers
119 views
How can a 4-bit CPU have 40 instructions?
Currently, I am using Logisim(yes, still Logisim) to build a 4-bit variant of the 8-bit SAP-1 microcomputer. However, I ran into a problem with the instruction register. Let me explain.
The SAP-1 has ...
1
vote
2answers
45 views
Dynamically pushing instructions to SRAM IC
Sorry if this isn't the right place to ask this. Coming from a programming background, and I'm not 100% sure how to read some of these data sheets.
I'm looking at using IC 628512LP-70 CMOS SRAM" (or ...
1
vote
0answers
61 views
FPGA and CPU design: Moving from ideal memory to real RAM blocks
I implemented the single-cycle MIPS design from "Computer Organisation and Design" in Verilog, shown below:
I used my own "ideal" data memory implementation, which asynchronously presents the read ...
0
votes
1answer
94 views
Why cant clock be directly used instead of DQS in DDR during read and write
I have been reading about DDR lately and I am not able to understand the exact use of the DQS signal. The timing diagrams show dqs in phase with clock so why cant the clock only be used for the write ...
1
vote
1answer
63 views
How can I make Lattice Symplify Pro infer RAM correctly from VHDL code?
I have a design on an iCE40 FPGA, I use iCEcube2 to compile the VHDL code and in my design I try to infer two small RAM buffers.
The type of the buffers is as follow :
...
2
votes
1answer
60 views
Why can't dual port RAM be read out using the Quartus In-System Memory Content Editor?
Here are the screen shots from Quartus;
When I want to instantiate the single port RAM, I get option to assign an instance ID and thus read it using the ISMCE (In-System Memory Content Editor). ...
0
votes
0answers
28 views
Dual-die FBGA RAM compatibility with older single-die
I have a small Smart TV running Android 6, which only comes with 512 MB RAM.
On the board close to the CPU are 1 NAND IC and 2x H5TQ4G63CFR which are 4Mb each. I would imagine one is for main memory ...
0
votes
2answers
77 views
Does RAM always use a big Mux to ‘read’ from its addresses?
I’ve designed a 64 bit (16 words * 4-Bits at each location) RAM in logic simulation software, using simple registers. I had to create a 16-to-1, 4-bit wide Mux (no mean feat) in order to ‘select’ one ...
2
votes
1answer
599 views
How can multiple ICs access shared RAM?
I'm trying to build a game console from scratch (as an exercise, not necessarily for practicality).
What I want to do is to have multiple "CPUs", in this case one being the Main CPU and the other one ...
0
votes
1answer
89 views
Why do we need interleaved memory?
I am trying to understand the DRAM working paradigm. I just read this article about interleaved memory. It says:
Interleaved memory results in contiguous reads (which are common both
in ...
0
votes
1answer
91 views
How to free up memory in a CircuitPython board?
I'm using a Feather M0 Express from Adafruit with a DS3231 Precision RTC FeatherWing for a custom clock project that displays time with LEDs.
The clock works as follows:
When the clock gets plugged ...
1
vote
1answer
82 views
Thevenin Theorem seems to not work in this 1 bit RAM RC circuit
I have a problem which consist in 1 bit RAM made of 3 MOSFETs. One of the questions is to calculate the maximum voltage that the memory element can receive. I have obtained the result by inspection (...
0
votes
2answers
122 views
SRAM: Purpose of Upper and Lower Byte Enable when Data Bus is greater than 8-bits?
What is the point of an upper byte and lower byte enable on an SRAM if the data bus is already 16-bits?
Is it related to multiplexing? I had always assumed that SRAMs were either designed with either ...
-1
votes
1answer
31 views
What do CT numbers in SO-DIMM RAMs mean? [closed]
Here is a picture from the "crucial" website. I am trying to understand:
What is the difference between buying 2 separate 8GB sticks and one kit of two sticks.
What do the CT numbers mean and why are ...
0
votes
0answers
76 views
Addressing the RAM on the DS1302 RTC timer chip with an Arduino
I'm trying to access the RAM of my DS1302 RTC chip. According to the data sheet, I need to clear bit 7 of the control register. The control register can be accessed at address 8Eh.
To test this out, ...
0
votes
0answers
46 views
6T SRAM write operation calculations
C: Cut off , L: Linear , S : Saturation
[keep in mind I am teaching this to myself ahead of time]
I understand how to go about finding desired ratio (W/L) for read operation. In the image, M1 would ...
0
votes
1answer
140 views
Accessing RAM on TERASIC DE0 Nano
I'm just wondering how to access more than 32Kb on a TERASIC DE0 nano. It is based on an Altera Cyclone IV FPGA. https://www.ti.com/lit/ug/tidu737/tidu737.pdf
It has 32Mb DRAM but there are
12 ...
2
votes
0answers
56 views
DDR3 SODIMM slow clock specification
I am considering to design memory controller handling 1GB of the RAM. I did already design controller for Micron's 32MB SDRAM in the past using Cyclone III device.
The new design is for retro ...
0
votes
3answers
80 views
External Memory IC which increments data on a clock pin
I am searching, with no success, in multiple categories of the external memory IC market for a chip that can do the following:
Store 1MB of data of 16-bit data
This data is stored at specific ...
30
votes
7answers
12k views
Can we not simply connect a battery to a RAM to prevent data loss during power cuts?
So, I was just wondering about how volatile memory storage loses data when the power to them is cut off. But can we not solve that problem by using a battery in conjunction with a RAM and a ROM and ...
1
vote
1answer
113 views
Cortex M4 memory management suggestions: best data/code placement
I'm trying to implement a rather complex (at least for me!) system on a Cortex M4 mcu: LPC4370. This one has HighSpeed ADC (up to 80Msps), DMA and DSP (Single Instruction Multiple Data) instructions.
...
1
vote
1answer
62 views
Is writing in FeRAM memory cell destructive?
I have read that writing in Ferroelectric random access memory is not destructive. But in a WL||PL memory architecture, if I try to write a '0' in a cell and the adjacent cell holds a '1', shouldn't ...
0
votes
2answers
72 views
How does a computer address ddr 4 sdram memory?
I want to be able to manual address a 4gb ddr4 memory stick. looking at the datasheet for ddr 4 there are only address pins from A0 to A17 which is 18 bits, 2^18 = 262, 144 address spaces. So how does ...
0
votes
3answers
119 views
RAM and Flash structure difference
I am trying to get a better understanding for RAM and Flash and I hope you could help me out with some things.
What I know about Flash (or at least I think to know), is that there are different Flash ...
6
votes
1answer
266 views
DDR3 Data Errors
I am looking for post layout solutions for DDR3 data errors.
I have a PCB with a FPGA and a 2 banks (2 rank) DDR3 ram setup.
Data errors occur either when the RAM (FPGA is not confirmed, but could ...
-1
votes
1answer
66 views
Find ROM and RAM in .bin file for micro controller
I use the Arduino IDE to compile some code to a 32-bit ARM Cortex-M3 based microcontroller.
The result of the compilation is <...
1
vote
1answer
285 views
What is the point of inverting RAM output?
The 74LS189 is a 4 bit RAM IC. The datasheet specifies that the output of the chip is inverted. Thus, if you put 1011 into address 1, when you read back address 1 ...
0
votes
2answers
127 views
DDR UDQS and LDQS into one DQS controller
I have one x16 memory chip () that has two Data Strobe pairs (UDQS and LDQS), on the other hand, I have arm chip (i.MX6 ULZ) that has one Data Strobe pair (DQS). Is there any way of connecting them, I'...
0
votes
2answers
59 views
Running code from different storage
So i know this question is being asked almost everyday on thousands of forums, but i am still going to ask that same question but with a different intent.
Question #1:
As an example lets use linux ...
5
votes
2answers
434 views
Why have apparent memory bitflips in non-ECC memory not increased?
Back in the early 2000s I remember asking about why it was so important that servers use ECC memory. The prevailing wisdom at the time was that systems with lots of RAM would be, statistically, more ...
7
votes
5answers
2k views
Why is this clock signal connected to a capacitor to gnd?
I am trying to understand the following circuit:
My problem is to understand why the CLK signal is connected to the capacitor (C7). The bottom side of C7 is connected with a resistor to GND. This ...
0
votes
1answer
31 views
Can more than one memory device transmit on the data bus at once?
I know that in general only one device can transmit over the bus at once, but if they are all memory devices, can they act as one? I have four 256x8 chips, which I think means that I have 256 cells ...
0
votes
1answer
360 views
Single Clock FIFO with Single Port RAM
I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...
0
votes
1answer
156 views
Home-brew cpu ram
I’m trying to build a cpu out of ttl logic chips. I’ve just about got everything finished, however, I’m still working on the ram. I don’t have any suitable ram chips I can use, however, I do have a ...
0
votes
1answer
101 views
Writing and reading from and to SRAM memory [closed]
im just learning SRAM.
I wanted to ask, consider the 4x4 memory cell array below
If i wanted to select a word line or row, would the row decoder be a 4x1 multiplexer where each wordline is connected ...
1
vote
1answer
110 views
How to validate that a function is executing from RAM?
I'm trying to execute a control function as quickly as possible from SRAM on an STM32F3xx using GCC (System Workbench toolchain).
...
2
votes
1answer
885 views
RAM Row and Column Decoders
I keep seeing similar diagrams of RAM like this abstract picture of a simplified RAM Layout. So I just arbitrarily selected this picture but my question is about this layout in general. My ...
22
votes
3answers
6k views
Why does RAM (any type) access time decrease so slowly?
This article shows that DDR4 SDRAM has approximately 8x more bandwidth DDR1 SDRAM. But the time from setting the column address to when the data is available has only decreased by 10% (13.5ns).
A ...
1
vote
1answer
699 views
connect Micron SDRAM to STM32H7 FMC but what should I do with DQM pin?
I plan to connect SDRAM from MICRON MT48LC series ( datasheet. The pin connection diagram is automatic generate by STM32CubeMX ( STM32H743 ). The setting is an 8-bit data bus, a 13-bit address, 4 ...
