Questions tagged [ram]
RAM is an abbreviation for Random Access Memory. A type of memory in which the information can be accessed from random location.
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For DDR4 and DDR5, is tCCD_l timing to be obeyed for accesses in a single row as well?
So I have been trying to learn about DDR4 and DDR5 memories, and it seems that the Column-to-Column delay values (in clock cycles) are different depending on whether consecutive accesses are inter-...
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What is the theoretical maximum capacity of 72-pin RAM modules?
I'm asking, because the information on Wikipedia is extremely lackluster, perhaps even incorrect.
This is my current understanding:
A 72-pin module has 12 address pins, 4 CAS, and 4 RAS pins. (For ...
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DS1220 vs X2816A
I have a legacy device from 1996 that uses a Dallas DS1220 NV RAM. The battery is shot and the device won't even boot. But if I swap in 6116 RAM chip, it comes up and works but of course won't save ...
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Why do STM32 MCUs divide RAM into SRAM1 and SRAM2?
Why do STM32 MCUs divide RAM into SRAM1 and SRAM2? They seem contiguous, so that I could simply configure my linker to treat both as just one chunk of RAM.
Should I do that? If not, how do I tell the ...
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MUX in a 4 bit by 3 bit memory
Here is a 3-bit adressable memory with an adress space of 4.
My question is why is the book calling the 3 rightmost highlighted circuits MUXes? And what type of MUXes are they? 4:1 MUX? And if it is ...
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Calculate Memory Address
I know this is a simple arithmetic question for many of you, but I can't figure out how to solve this problem.
In a uController (this is an example, it doesn't matter which one) SRAM1 has ...
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Ideas about generating images for E-Paper display
I am currently working on a project where I'm using a DA14531 BLE-module to collect data from some sensors and display the collected data on an E-paper display. As the display is quite large (400x300 ...
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PIC18 Bit-addressable RAM
Given that the PIC18 architecture does not provide any bit-addressable RAM, would it be a sane idea to utilize carefully considered unused bit-addressable SFR's? For example, if my project does not ...
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STM32H750B configuring DMA to transfer from GPIO to RAM
on STM32F769i
I used DMA2 triggered by TIM1 to read data from GPIOB port like this
so timer1 counted and when it triggered DMA read data in circular mode from GPIOB into my buffer
...
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NVRAM data is reset to 0 when using NVIC_SystemReset()
I am working on nRF52840 with Mbed5.15. Trying to persist data in NVRAM.
In the linker script nRF52840.ld I have something like this:
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How does DDR SDRAM increase the bandwidth without increasing the frequency at which a memory array operates?
I am reading about SDRAM, and how the bandwidth was increased with DDR optimizations. From my understanding DDR can send data at a rising and falling edge, effectively doubling the data being sent. ...
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Soldering to data bus of DDR3 ram
Lets say I solder a 2 inch, 30 AWG wire to each data pin on a DDR3 RAM module.
Would this damage the RAM module enough to make it useless?
Would the added resistance because of the wire cause a ...
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Circuit for Read/Write RAM Control Signals
I have the following architecture of an 8-bit bus / RAM interface where the bus can read from and write to the SRAM:
There are two 74LS245 8-bit bi-directional buffers, with there direction input ...
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How to write the scatter file for Keil uVision to force linker to allocate variables in SRAM?
Development environment
I'm working with STM32F427 and I use Keil uVision V5.29 to develop my application. The version of the ArmCLang Compiler, of the Assembler and the linker is 6.131.1.
Scatter ...
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How can I improve this RAM implementation in VHDL?
I'm practicing for a lab exam and I'm trying to solve one from past years. I feel like I'm doing something wrong because I don't have much experience with VHDL.
Exam question
Write the VHDL code for ...
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Why does RAM VHDL simulation output unexpectedly always shows zero?
I wrote VHDL to instantiate some RAM (256 bytes) using BRAM on a Digilent BASYS 3 FPGA development board using Vivado design tools. It takes 8 bits as the data input and outputs 8 bits on the output. ...
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Computer architecture: Count of RAM, ROM and I/O interface addressing
I am trying to work through this question and I appreciate any help or hint. Thank you
Problem:
A computer system uses RAM chips of size 512x8 and ROM chips of size 256x8. The computer system needs 4k ...
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Is there any reference to design a 4*4 bit ram only using transistors
I'm currently doing a project and would like some help. I need to create a 4-bit 4-word RAM using PSPICE. (I'm both new to the PSPICE program and new to the topic of RAM)
I currently have successfully ...
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How are system clock and bus clock frequencies related?
I see a frequency in RAM specs which is different than the frequency of the system clock. Having a separate clock makes sense if RAM can't run at the same frequency, but is there a constraint that its ...
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How to allocate a constant array to RAM other than LUTs [closed]
I'm still pretty new to hardware design.
Now I need to store a number of constants and then use them as indexes.
My first idea is to declare registers, ...
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How to test DDR3 PC3 / DDR4 PC4 RAM works fine using a micro controller
I am trying to make a device that can test if above mentioned RAMs are working without a problem. Does anyone have a place to read about RAMs and how to test them. Any help would be appriciated.
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What happens if malloc() fails in a microcontroller?
What happens if malloc() fails in a microcontroller (e.g., due to not enough data memory freed)? Does the watchdog timer triggers a timeout response (e.g., reboot) ...
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Why did GDDR5X implement QDR?
DDR makes complete sense to me: it matches up the transition rate between the data signals and clock, so that twice the data can be sent over a bus without increasing the overall design bandwidth. The ...
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How is a bistable element formed with two inverters and two transistors in a 6T SRAM cell?
I'm trying to figure out how a charge can be stored between two CMOS inverters and two more transistors.
I understand how the inverter works, just with a NMOS and PMOS base connected to a common ...
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How to see by how much a microcontroller program is out of data memory - inside MPLab X IDE
I have a problem that cannot exist. I keep building programs in MPLab that are close or just over my allotted RAM. I really want to see by how much over my RAM ("data memory" - why do they ...
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Microcontroller, Flash EPROM and RAM combination questions
I have chosen a specific microcontroller (MCU) for a project, based on price, package size, and speed. It's the NXP LPC1768FBD100, a 100 MHz ARM-based MCU with 512 KB program memory and 64 KB SRAM.
My ...
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Giving write enable signal externally by DIP switch to FPGA memory
I have designed a simple internal SRAM memory where I initiate the write enable and read enable via DIP switches.
Verilog input wire has been declared in the simple memory read write which connects to ...
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Can I use LPDDR3 memory that is larger than my processor supports?
I am working on a thing that uses a STM32MP157C. Its datasheet says:
The STM32MP157C/F devices embed a controller for external SDRAM which support the following devices
• LPDDR2 or LPDDR3, 16- or 32-...
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Accessing data from a ddr3
I'am working on a new projet where I'm willing to access data from a ram, but the ram's specs is that they work with a frequency up to 667MHz , so I decided to choose an FPGA to work as controller ...
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Using a level triggered latch as a negative edge trigger for negative logic
I am a (relatively) new hobbyist and I am working on a project that uses an old video chip (v9938.) The chip is designed to use old DRAM, with a multiplexed 8 bit address bus, and *RAS and *CAS ...
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VHDL FIFO w/ RAM
I've been tasked with designing a FIFO in VHDL for the block diagram below. I understand the general mechanism of how a simple FIFO works, but I've been struggling with how to connect the address from ...
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I'm designing a 4-bit GPU and I need some suggestion about the RAM for it [closed]
I'm working a 4-bit GPU, the GPU run on 1.023MHz (1023kHz) clock while CPU only run on 127kHz so I need a screen buffer for it when the CPU is working on some instruction. The display I use is a 24 x ...
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Can I use logic inputs higher than Vcc but still in the operating voltage range of the IC?
I'm trying to create a battery-backed-up non-volatile RAM using an SRAM IC (AS6C1008 from Alliance Memory, datasheet).
My idea for separating the backup battery from the main voltage source is to use ...
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Microcontroller and Memory size allocation
Below are two custom made microcontrollers. The only difference between this is memory size.
My question:
Can someone tell me what is their start address and end address? Like, for the first one - ...
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ESP-PSRAM64 Termination Resistors
ESP-PSRAM64 uses a bidirectional QuadSPI interface at up to 133MHz. I am connecting this to an STM32 microcontroller. Normally I would use some series termination resistors at the source (e.g. for a ...
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STM32 How can I run code from ram?
I have this really simple "Hello world" piece of software (project attached), running on a STM32WB55 Nucleo board (basically, it sends "HELLO WORLD\n" via USART1, every 1000 ms).
I ...
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How to accumulate samples coming into a memory block without using another buffer i.e sum with previous corresponding samples?
So I have an 8k memory block in the FPGA. Samples come into it from outside the FPGA, from an ADC that has a source synchronous interface consisting of parallel transfers with a clock from the ADC. ...
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What are my troubleshooting options for Hyperbus RAM?
I have a custom PCB with a STM32H7A3ZI MCU, and a S27KL0642S27KS0642 Hyperbus RAM.
My code, as well as the app note (AN5050) I'm following sets up the RAM for memory mapped access.
I believe I've ...
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How come I can play audio in my ESP8266?
I'm currently messing with the ESP8266Audio Library. I uploaded a sketch to my ESP8266 that uses a HTTP stream of MP3 from the web and plays it using some MP3 decoder. So basically the loop looks like ...
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Enable vendor-disabled hardware on tablet? [closed]
I have a nextbook tablet (one of those cheap things from walmart) that I was looking to try to improve the RAM situation on to breath some new life into it as it apparently only has 1G of it. I ...
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How much memory does the 23LC1024 have?
The Microchip 23LC1024 chip is said to have 1Mbit of memory. Looking at Wikipedia, it says that a Mbit is 10^6 bits. Is that so? I mean, is this decimal Mbit? It doesn't seem reasonable to me..
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Where is the RAM stored on a RISC-V CPU? [closed]
Does RISC-V have any opinion on whether the RAM is stored on the same chip as the CPU (like on ARM devices) or on a separate chip somewhere on the motherboard (like on an x86 desktop)? I assume that ...
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What does High-Impedance mean in digital systems?
I'm currently messing with the Microchip 23LC1024 SPI RAM chip, and trying to read the datasheet to understand how to work with it. I'm not an electronics engineer or something like that, I'm a ...
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How to connect a 23LC1024 to a breadboard?
I just got my 23LC1024-E/ST module, and I realized how tiny it is. How do people work with this? It's obviously not breadboard friendly. Are there RAM modules out there for Arduinos/ESP8266s that are ...
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How prevalent is adoption of IEC and/or IPC standards among the major electronics manufacturers, especially CPU makers like Intel & AMD?
I spent part of the weekend learning about the history of the International Electrotechnical Commission (IEC) and IPC (originally an abbreviation for Institute of Printed Circuits) and their standards....
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Memory in FPGA: buffer to store bytes "sent" by SPI Slave
I asked before what SPI slave is and how the received data could be stored...
SPI slave collect a byte a sent it to FIFO as a temp buffer and the next step is to send the bytes to a memory. I have ...
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Problem of metastability: simulation of dual port ram
i simulate Dual Port Ram Register in VHDL and have some doubts about the metastability problem.
Dual Port Ram has 2 clock signal, one for Port A , the second for Port B. In my simulation I create two ...
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Using BRAM as buffer
I'm trying to implement a buffer for an image processing pipeline and need to load data into BRAM.
I've been following an online tutorial (https://www.youtube.com/watch?v=n35zS__YEFQ) for implementing ...
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tri-state RAM switch
The picture shows the truth table of control operation of a RAM. If you disable the OE pin the output can not come to the bus because of high impedance, now the question is, is the impedance ...
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What does the "In-line" in SIMM and DIMM memory mean?
I've been searching for what exactly the "in-line" part means but I don't get it. Is it the way the chips are positioned, as in a line? If it is, is there another possible configuration?
