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Questions tagged [ram]

RAM is an abbreviation for Random Access Memory. A type of memory in which the information can be accessed from random location.

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iPAQ Backup Battery Connector

I've used an H4155 on and off for about a decade now and every two years or so the backup battery begins to increase in standby voltage and fail. I prefer to replace it just for the sake of it ...
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2answers
405 views

PCB - Ram connectors problem

Currently following an schematic for NanoPI NEO4 to make my own RK3399 board. On their schematic for the K4B4G1646D-BCK0,I noticed for pins DQ1-DQ15 on both chips connect to a randomised list of ...
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120 views

Designing a RAM, using 4x2 chips, with a 8 address capacity

This is a typical exam question, and I've seen some very helpful posts about, but I still have a lot of doubts. Given an integrated circuit of certain dimensions, for this example a 4x2, I have to ...
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68 views

What design differences make ram faster than ssd for read/write [closed]

I understand that RAM is connected directly to the CPU via a high bandwidth bus, and SSD is a peripheral, but my assumption is that there are also electrical design differences (e.g. memory cell ...
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2answers
60 views

Are SSDs true random-access devices?

Since all kinds of flash memories feature different transfer rates according to the kind of operation performed at a given moment (e.g., random access reads versus random access writes, random access ...
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34 views

Low Level Interface/Primitives that Interface with RAM (DDR4)

I am trying to understand how CPU Assembly Instructions interface with the RAM? And how RAM works out those instructions. So for example when CPU says: ...
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1answer
212 views

On AVR-GCC, how can I find out what statically initialized variable is using up my RAM?

The variable does not show up on the MAP file so it is hard to track it down. I'd rather not have to manually search though all the source code looking for static initializers.
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2answers
87 views

Z80 RD and WR to RD/WR?

This may sound like a very stupid question. However, I am new to the Z80 stuff. I am planning on how to connect the Z80 control signals to a SRAM. But the Z80 has seperate RD and WR, while my SRAM has ...
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1answer
28 views

Using narrower DDR RAM than controller

I have some ARM processor that have 72-bit width (8 for ECC) RAM controller. Can I buy eg. two 32bit chips and combine them? If yes then how? Can I buy just one 32bit and pull down rest of data pins ...
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1answer
53 views

use sram as logic analyzer?

So I was thinking of buying a logic analyzer and found that a lot of the cheap ones are good to only a few mhz, and the microcontroller based ones can't have big buffers. So I was wondering if I could ...
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1answer
43 views

Ebedded Linux: Recoverable, battery backed-up RAM (/tmp) [closed]

I hope this is an appropriate place for this question as it involves the use of the kernel. I have an embedded system with a battery backup for the RAM chip. The battery also allows for the MCU to ...
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1answer
88 views

how to access the same RAM module from different modules?

I have a cyclone v gx starter kit. It comes with 4884 bits onchip memory. I want to write a module for accessing the onchip memory. So, I have generated the ram ip reference design from ip catalog ...
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653 views

Is there a lower limit on operating frequency of CMOS SRAM?

I study computer science, and so I am in the deep end here. I have set upon designing a machine which requires RAM. I found a listing for Toshiba's 128KB (8 bit per word) SRAM (TC551001BPL). I intend ...
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50 views

Does building a RAM with more storage lead to decrease in performance? [closed]

Talking about Single channel DDR Ram, If say one RAM module were 4 GB, another 8GB. Is there any performance difference between those two?
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1answer
175 views

Why is there seemingly no delay in a block ram read

I am trying to learn Verilog and was curious why my FPGA's block ram seems to provide the data that I request instantly. I was expecting that there would be some number of clocks that I would need to ...
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5answers
229 views

What to call the cells of memory in a computer or a microcontroller?

I don't know if this is the right forum to post this question, but I thought so because this forum is for educators and I'm a trainer and my question is related to education. I want to do an ...
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1answer
455 views

What is the difference between BRAM and distributed RAM [closed]

I am doing a project on BRAM implementation. What is the difference between Block RAM and Distributed RAM on FPGA in terms of implementation, area, speed etc? Which is better?
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4k views

Why use DDR instead of increasing clock speed?

Why would you want to use DDR ram and read/write on every rising and falling edge of the clock instead of just doubling your clock speed and read/write on just one of either the rising or falling edge?...
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1answer
51 views

SDHC write partial block

Is possible with SDHC microSD card write 32 bytes of data without loading full block o the RAM? SDHC has for some operations fixed block size to 512 so I dont know if it is possible. If possible what ...
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1answer
64 views

Configure microcontroller flash memory as ram?

Is there anyway i can use micro-controllers flash memory as a RAM as i need 150kB of buffer but controller has 32kB of RAM and 512kB of Flash? Also can i use this ram as stack or heap?
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3answers
88 views

How to properly monitor supply voltages

How do you properly monitor supply voltages for digital circuits (microcontrollers, FPGAs, RAM)? (I stumbled upon this question when working on safety critical systems) What I have seen a lot is to ...
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1answer
52 views

how is ddr4 controlled on the laptop

I am a student of electrical engineering and my previous term's project was implementing ddr2 SDRAM with Xilinx FPGA, but I am interested to know which device on the laptop control ddr4 on it? and ...
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1answer
87 views

How to make sure a clocked operation happens just once in Vhdl

title may be a bit confusing but what I try to do is to take data from ram/modify it and put that data back to the ram. I want all of this to happen just for the operation(Brightness/Contrast) time ...
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2answers
122 views

What is read latency in ram summary in VHDL

Hi I am using a single port ram which is constructed using block memory generator in Vivado. When I am reading its summery, something caught my eye. In summary it says total port a read latency: 2 ...
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2answers
105 views

Resetting Ram problem in VHDL

Hello I am making a VHDL project in which I am doing some image processing. Color data of pixels are held in Rom and operations are done on Ram. However, when I try to reset the ram from the rom. It ...
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0answers
43 views

Cannot read from RAM in Vhdl

Hi for some image processing purposes, I must read 12-bit color data of a pixel from Ram and display it on screen through VGA cable. However, my code does not read from Ram and all I see on the ...
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1answer
116 views

Multi driver error in VHDL

Hi I am writing a code for image processing that includes a Ram to/from which data will be written and read. However, I am getting 15 errors like the one below. ...
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2answers
216 views

How to avoid writing to and reading from 2D array at the same time vhdl

Hi for something I work on, I must use an 2D array but I find it dangerious to write to and read from a certain memory location in the array at the same time. How can I control this situation? When ...
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1answer
188 views

Reading from file in every rising edge of the clock in VHDL

Hi I am trying to read data from a file which contains 62500 lines of 12-bit binary numbers in order to instantiate my 2D array(sort of a RAM). However, my problem is that this process happens in one ...
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1answer
852 views

How do I find out at compile time how much of an STM32's Flash memory and dynamic memory (SRAM) is used up?

IF THIS IS A BETTER QUESTION FOR STACK OVERFLOW, CAN AN ADMIN PLEASE MOVE IT? I think I have the answer for Flash memory, but the RAM question still eludes me. Arduino has this super nice feature ...
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1answer
550 views

Replacing Pseudo-SRAM with SRAM

This week I am repairing an old Game Gear, suffering from bad video memory. The original IC is a HM65256BLFP-10T: an asynchronous Pseudo-Static 8-bit 32k-word RAM with an access time of 100ns. I ...
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57 views

Implementing SOP using Mat in ReRam

In ReRam in logic mode, one mat can be configured to implement multiple arbitrary combinational logic functions (e.g. AND, NOR). More complex logic functions can be realized in the Sum-Of-Product form ...
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3answers
125 views

What determines the maximum size of a cpu cache?

Looking at a list of the very latest CPUs, I see several of them with a cache size of 12MB or 8MB - pretty small, when compared to the ever-increasing size of hard drives and ram. It seems to be taken ...
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1answer
153 views

Why does this RAM component have unpredictable behavior in Multisim?

Multisim has a 2k8 RAM component that I was playing around with. Here is how it works. Here is what happens when I simulate this. Let's say I save the value 00000011 to address 00000000. Then, I make ...
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81 views

Why does a 74LS189 RAM chip light-up an LED connected to its re-inverted output when data word is HIGH while a 7489 RAM chip cannot?

I have thought on it a lot and summarizing my confusion here. I have two SN7489N chips whose Ioh is 20uA (not sufficient to light-up an LED). Correct me if I'm wrong that Ioh is the maximum current it ...
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2answers
138 views

I have an SN7489N Memory IC which is not lighting-up an LED whose positive-end is connected to one of the output pins via a 220 Ohms resistor

CHIP Used: SN7489N F 9013 BS [EDIT] I'm willing to light-up an LED at the output of the chip when the data stored is high, just as noted in a 74LS189 chip (and seen in this video : https://youtu.be/...
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3answers
107 views

Why is SDRAM speed independent from the motherboard?

My understanding based on my research says that Synchronous DRAM has its name because it synchronises with a clock on the motherboard. How is it, then, that the speed of the RAM doesn't depend on the ...
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9answers
1k views

EEPROM with high endurance

I am currently working on one embedded project in which I have one counter which will be active all the time. If the power goes down then also I have to store last counter status and load it back in ...
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1answer
376 views

Concatenating from Block RAM in Verilog

I have instantiated a block RAM module using Block Memory Generator segment of the Xilinx IP Core. Alternatively, I have coded my own simple single-port RAM module, much like on page 33 of these ...
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2answers
822 views

What does Burst-size of a SDRAM means? [closed]

I am currently working with real-time image processing in FGPA. I have some timing problems about the classical FFT algorithm. i.e : FFT of one images spends more time than one frame period time. I ...
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2answers
169 views

Associating ROMs and RAMs

Can someone explain to me how to associate smaller RAMs and ROMs to make a bigger one? For example: How do I make a 1024x8 RAM with 512x4 RAM?
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1answer
222 views

Design logic circuit to address 2 x 512 kB RAM and 2x1024 MB RAM with 36 address lines? [closed]

How do you address 2 x 512 kB RAM and 2 x 1024 MB RAM with 40 address lines? Memory is byte addressable, problem is to find out enough address lines to address all 4RAM and designing appropriate ...
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1answer
121 views

Ram USB storage device [closed]

I have been searching for a storage solution that can be written to an infinite amount of times, and RAM comes up every time. So is it possible to connect RAM to a controller and use it like a ...
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2answers
612 views

What is SNM(Static Noise Margin) in SRAM?

I have read multiple papers and articles about it but still, I am not able to understand fully. If you can explain me in layman terms I would be much happy. Thanks.
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3answers
1k views

How many capacitors in single RAM?

Just a simple question, In https://en.wikipedia.org/wiki/Random-access_memory says that each bit of data in RAM/DRAM stored in a single pair of transistor and capacitor in memory cell. So let's ...
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0answers
435 views

VHDL code Reading from entire RAM memory: data repeats every 128 addresses

I am using a Basys 3 FPGA with a memory connected to it and using Vivado 2016.2. My target is to read from 2^21 memory spaces of the RAM and send the data to computer using UART. I am using a MATLAB ...
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3answers
264 views

Using async SRAM in homebrew CPU

I am building a homebrew CPU and have now reached the point of designing the SRAM part. I plan of using a simple 32K x 8bit static RAM (such as the Cyprus CY62256N). My concern is that the part is ...
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1answer
344 views

FATFS copy between Ramdisk(FMC) and SD(SPI) on STM32F4 [closed]

I am trying to solve this problem. I am using FATFS13 on my custom STM32F469 board and I am using the Standard Peripheral library. I have connected 1MB of SRAM over the FMC bus, and an SD card over ...
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1answer
122 views

Byte-addressable RAM as opposed to word-addressable RAM

A couple of months ago I started working on developing my own computer to learn more about its low-level functionality, the design process and the architecture behind it. Although I look at real-world ...
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9answers
13k views

Why execute code from RAM?

I've just come across some macros for my microcontroller compiler to force (or suggest) a function be executed from RAM. https://siliconlabs.github.io/Gecko_SDK_Doc/efr32mg1/html/group__RAMFUNC.html#...