Questions tagged [ram]

RAM is an abbreviation for Random Access Memory. A type of memory in which the information can be accessed from random location.

Filter by
Sorted by
Tagged with
0
votes
1answer
32 views

Unexpected behaviour of data memory in modelsim testbench

I am describing a very simple ram memory in VHDL and observing strange behaviour which I do not understand nor am able to debug. I have similar code written elsewhere and I suspect that rewriting it ...
1
vote
2answers
53 views

FPGA, DDR3 Layout

In my new project I use a FPGA to load some data into a DDR3 RAM. Can I directly connect the I/Os of the RAM with the I/Os of the FPGA? Or do I passive components in between them?
1
vote
4answers
180 views

Global variable - memory allocation

I am in general interested about how compiler and linker handle global variables. Here click it is explained that additional ROM is needed in case variable is initialized and not 0. So wondering, why ...
1
vote
3answers
215 views

What does the 8086 CPU do with the data returned from an address in RAM?

I understand how a CPU works fairly well, but there is this one thing which I've never really gotten the hang of. Say we have an Intel 8086 CPU (16 bits wide registers) which is about to fetch its ...
0
votes
1answer
27 views

Cache comparator usage

Referring to the photo below, in direct-mapping cache design, why we need a comparator to compare between the tag in the address and the tag in the cache? Isn't a valid bit enough?
-1
votes
4answers
146 views

Why is bool type typically 1 byte long?

I was reading: https://www.quora.com/Why-is-the-bool-type-typically-8-bits-long And the answer was: Because it’s the smallest type that has an individual memory address so that you can take a pointer ...
0
votes
2answers
46 views

Is M1 Chip Memory Considered as Registers?

Given the following image of Apple's m1 chip, we can clearly see that RAM is so close to the CPU: does this say that RAM will be much faster when compared to others Macbook models (Since distance is ...
1
vote
2answers
88 views

Is there a proper way in VHDL/Verilog to access block RAM given a multi-hot vector?

I am currently trying to learn how to program in VHDL with the goal of implementing an LDPC decoder in hardware. My understanding is that log-likelihood ratios (LLRs) serve as inputs to the decoder. ...
0
votes
1answer
75 views

Using DDR4 RAM instead of SRAM

Currently I am using the internal BlockRAM from a FPGA to safe the samples I am getting from an ADC with a frequency of 200MHz. In the future, I want to use equivalent time sampling to get a virtual ...
0
votes
0answers
209 views

Why is it easier to implement bytes as 8 bits rather than 9 bits? [duplicate]

From book to book I always find the same sentence. For example: 8 bits is an even power of 2, which makes it somewhat easier to design computer hardware with 8-bit bytes than with 9-bit bytes. ...
0
votes
0answers
28 views

What memory operation gets inferred when read port datawidth is larger than physical BRAM width? Xilinx 7-series + Verilog

From the 7 Series Memory Resources User Guide (page 11): The block RAM in Xilinx® 7 series FPGAs stores up to 36 Kbits of data and can be configured as either two independent 18 Kb RAMs, or one 36 Kb ...
1
vote
0answers
59 views

Capacitors between multiple positive power rails in cpu power system

Many years ago, when I was working in samsung aftermarket supply chain with set top box repairs I had access to basic schematic of one of stb. In a power supply part for powering RAM there were a few ...
0
votes
1answer
73 views

Storing Program Instructions on FPGA

I am creating a basic RISC processing core on a FPGA development board (Nexys A7-100t). I created a RAM block that will be used to store the instructions that my basic processor will execute to run a ...
0
votes
2answers
35 views

Memory Selection and NOT Gate in Embedded System

I'm currently studying Embedded Systems and in the topic of drawing a schematic for the address of a microprocessor (16bits address x 8 bit data (64Kbytes)) with 1 ROM 32Kx8 and 1 RAM 32Kx8, I simply ...
0
votes
0answers
37 views

DRAM, multi-channel, memory access

I'm looking for a way, under any configuration/OS(windows or linux)/programming language you suggest to simultaneously access memory addresses, that are under different channels, meaning the access ...
0
votes
3answers
54 views

Internal and external storage for a FPGA

I want to store at least 2Mbits on a FPGA. What is the normal practice for storing data on a FPGA internally? Also, if I wanted to store 4GBytes externally, how would I go about doing this? Is it ...
-2
votes
1answer
86 views

My understanding of computer hardware architecture

Forgive my above crude diagram. Assume the above is the hardware architecture for a computer/mobile phone or any device which hold a microprocessor. Please let me know whether my understanding is ...
0
votes
0answers
35 views

DDR3, Data Mask Pin-swap within a given byte lane

Is it possible to swap "Data Mask" or "Data Strobe" pins with DQx pins within the same byte lane. In Freescale's "Hardware and Layout Design Considerations for DDR3 SDRAM ...
0
votes
1answer
52 views

Using VHDL integer_vector for a block ram type, how to restrict the integer range?

Trying to simply infer block rams in a design with varying depths and widths. I'd like to have one ram definition since it is going to use a vendor specific attribute and it seems like a good idea to ...
1
vote
1answer
53 views

understanding data semantics and diagram

According to http://www.auto-diagnostics.info/pdf/ford_eectch98.pdf page 10, "The 8361 ROM chip contains 8k bytes of program memory plus 128 bytes of additional RAM." I found two diagrams ...
1
vote
1answer
62 views

How to Simulate VHDL when Using a Vendor's Tool Generated Instantiation Code?

I'm working with a Gowin FPGA and they recommend instantiating block RAM. That sounds great, but how do I simulate that? I would expect there to be a library with the model for the instantiation ...
0
votes
1answer
44 views

How to Use Addresses with Single Port RAM on FPGA

I am trying to understand this example of single port memory where an 8 by 64 bit RAM is created. If I am understanding correctly, the section of code that says "reg [7:0] ram [63:0]" means ...
-1
votes
3answers
75 views

Calculating RAM memory capacity from schematic symbol

Is it possible to calculate the memory capacity of a RAM given its schematic symbol? I made a first guess from an example but seems to be incorrect: If the address bus is 15-bit width, there are a ...
0
votes
0answers
54 views

4 address lines for 1 bit input

I am currently trying to design a 16 nibble RAM on logisim, whereby it takes 4 data input lines. However, what I am having the most trouble with is converting the 4 address lines into a single input, ...
1
vote
2answers
122 views

How is 1 bit transfered from RAM to a 1 bit register?

I've been reading on computer RAM and CPUs. I came to the conclusion that most RAM today use arrays of DRAM while CPU registers and caches use SRAM. 1 bit DRAM is a circuit with one capacitor and 1 ...
0
votes
1answer
52 views

Vivado VHDL BRAM write-read Simulation not reading properly

So im trying to simulate a simple write and read memory program in Vivado design suite. Before implementing a clock in the sensitivity list on the process to write and read, the reading part used to ...
1
vote
1answer
58 views

VHDL Type memory question

My question is very simple i think, but i would be really gratefull if anyone can help me with this. When i want to write in the fpga memory using the classic following line code: ...
0
votes
3answers
69 views

Is this the correct w recognize Opcodes for a DIY 8bit Processor

simulate this circuit – Schematic created using CircuitLab i am starting with designing a 8bit computer and probably turn it into reality , so lets say i start with a 8bit 32kb memory and i want ...
0
votes
0answers
83 views

Can I use a 16bit memory with an 8 bit processor?

The address bus is typically a double octet wide (i.e. 16-bit), due to practical and economical considerations. This implies a direct address space of only 64 kB on most 8-bit processors This quote ...
4
votes
2answers
2k views

How can I access more than 15 addresses of data from my 8 bit incomplete computer?

Last year I started researching upon how computers work, so I started making one, at least on paper last month, but I ran into a serious problem that isn't getting a satisfying answer from any article ...
4
votes
1answer
54 views

Why do DDR RAMs have both xDQ and xDM signals?

DDR2 RAMs have these control signals RAS, CAS - address strobes UDQ, LDQ - byte strobes WE - write enable UDM, LDM - write mask Why do we need UDM and LDM? Can't you write a byte by asserting WE and ...
0
votes
0answers
76 views

Can you desolder and upgrade RAM in Pi boards?

Friendly Electronics has come out with a great small compact but very powerful board. It is called the Nano Pi fire 3. It has 8 cores which is great for programers like myself who want to utilize the ...
1
vote
2answers
73 views

How can I improve my testbench for testing a 1024x4 RAM memory in Verilog

This is a question following on from my previous one "How can I improve my testbench for testing a 1024x4 RAM memory in Verilog". Basically, I have modified the previous solution in an ...
0
votes
1answer
60 views

How to decide when to use flop or RAM based fifo?

Trying to figure out what are the tradeoff like power, size when deciding between using a flop or RAM based fifo ? Any known publications ?
0
votes
1answer
69 views

pseudo dual port RAM in verilog

How to design pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ? Clarification on 'pseudo' dual port - single port RAM (1RW)...
0
votes
1answer
71 views

How Does One Do Block RAM Inference on Altera Cyclone 10 LP FPGA Boards in Verilog [closed]

I have tried to google for this a lot but I can't seem to find anything.
1
vote
1answer
87 views

What can I do to improve my test bench for testing a 64x4 RAM memory in Verilog

What can I do to improve my test bench for testing a 64x4 RAM memory in Verilog to obtain the desired result? I have written a test bench to test a simple 64x4 RAM memory in Verilog and it seems to &...
0
votes
1answer
112 views

Write ADC data to memory and back to DAC (without MCU)

Is there a way that is not too complex way to implement ADC -> SRAM -> DAC data transmission without the usage of the microcontroller? The application is to implement the audio loop of some sort,...
0
votes
1answer
123 views

Why the RAM 23lc1024 is not responding or give error?

I interfaced the 23LC1024 RAM module to atmega328. I have coded using embedded c on avr studio. The program flows like one byte is written to the address 0x000000 and Read data from the address ...
0
votes
1answer
32 views

How to compare VitalDelayType01 to each other?

I have a behavioral model of an external RAM part. This vendor seems to have used some external library functions or procedure they made. It has these functions like: MinDelay (a, b) return c; --where ...
0
votes
2answers
97 views

12-bit homebrew computer?

I'm planning my first homebrew computer. I'd like to perform calculations with 8-bit numbers. My op codes will be 4-bit numbers. I'll be building this on breadboards so I'd like to keep things as ...
0
votes
2answers
76 views

Feasible to capture data to/from a 1970s RAM chip?

I have a 1978 Bally Playboy pinball machine. The processor is a 1Mhz 8-bit microprocessor Motorola 6800. I would like to build a way to extract/watch game state from outside of the machine. The best ...
0
votes
1answer
109 views

Interfacing a RAM chip from a commercial computer with an ARM cpu such as Stm32

I need to interface some sort of RAM with an ARM processor for my embedded project. Around 128 MB to be exact. I found a computer RAM which claims to be DDR and 1 GB. As I only need 128 MB of RAM for ...
0
votes
0answers
34 views

How to calculate RAM size from chip markings and number of chips

I have a RAM with 8 TMS44400DJ chips on it. It says the word length is 1048576, so would it mean times 8 I have 8MB RAM on this module?
3
votes
0answers
111 views

Why DDR4 Specs recommend that Address, Control and Clock buses be referenced to VDD?

Micron's Technical Note TN-40-40: DDR4 Point-to-Point Design Guide, page 19, says (emphasis mine): Timing Budget Suggested practice is to look at the design from a timing budget standpoint to provide ...
0
votes
0answers
53 views

How to output a determined number of characters in VHDL regardless of the input

I´m working on a code VHDL with a RAM memory which purpose is show me the output data in the TeraTerm software. I enter the data via the Arduino COM window (The Arduino MEGA 2560 is connected to an ...
1
vote
0answers
30 views

lowering voltage of high frequency signal

One of the parts I have is RAM (1.5V logic level). The hardware communicating with it, is at a 1.8V logic level. The RAM signals are sent quickly - around 350-450Mhz. So I am pretty sure I can't ...
0
votes
0answers
60 views

Embedded system - copying data from flash to RAM

This question uses some Xilinx-specific terminology. I'm currently working with a Zynq Ultrascale+ MPSoC (CPU + FPGA in same package). I'm using a QSPI flash chip to hold the CPU configuration code, ...
0
votes
1answer
44 views

Is a metallic conductor within an electrostatic field necessarily subject to discharge?

Basically what I'm trying to determine is if the new RAM chips I received in the mail were potentially damaged from static electricity. Late last night, tired and foggy, I built up a considerable ...
3
votes
2answers
238 views

What is the probability of a bit error occurring in modern computers?

What is the probability of a bit error occuring when reading/writing from/to the latest memory technologies (ssd, hdd, ram) in modern computers? If the same terminology is used in this context as in ...

1
2 3 4 5
7