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Questions tagged [ram]

RAM is an abbreviation for Random Access Memory. A type of memory in which the information can be accessed from random location.

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FPGA Block RAM: Does Read Enable being low save power?

I am trying to understand the actual purpose of the read-enable signal on synchronous FPGA Block RAMs. I do not see the actual need of it. But regardless of why it was put there in the first place, ...
quantum231's user avatar
1 vote
1 answer
214 views

What does transfer rate in RAM actually mean? How do you actually measure it?

From what I gather, transfer rate is how many bits you transfer via the bus at once with every clock. So the formula would be: frequency (in MHz) * 2 (because of DDR) * bus width (because I think it's ...
WaveCave's user avatar
0 votes
2 answers
95 views

Is the communication between memory controller and RAM serial?

I used to think that the communication between memory controller and RAM is parallel since we know that a RAM stick has multiple pins, just like this: But then, from Wikipedia article on memory ...
Noob_Guy's user avatar
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4-bit IC to 8-bit RAM module

I'm trying to wire up a RAM module based on the Ben Eater's RAM Module Part 1 video, but there are no available RAM chips where I'm located at so the only IC I have available is a CAT22C10 NVRAM which ...
deltakid0's user avatar
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0 answers
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DDR Data strobe wiring

I have a device that has a unified memory architecture and has four 32bit ddr ram chips totaling 128bit and only has a single data strobe for the whole 32bit address bus on each chip not for each byte ...
Jonathan Brophy's user avatar
2 votes
1 answer
113 views

How to test for stack overflow on an ATtiny85 using an emulator?

I am developing a hobby project using the Arduino IDE and an USBasp programmer to upload my code to the ATtiny85. After programming, I remove the chip from the programmer socket and put it into the ...
PanJanek's user avatar
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0 answers
34 views

Connecting higher density LPDDR3 SDRAM than the ATSAMA5D27C processor supports

I'm designing a Single Board Computer for the first time. The board will have ATSAMA5D27C as its MPU with LPDDR3 SDRAM. The datasheet specifies that the maximum SDRAM it can support is of 4Gb (512 ...
Prabhat Narang's user avatar
1 vote
1 answer
231 views

For DDR4 and DDR5, is tCCD_l timing to be obeyed for accesses in a single row as well?

So I have been trying to learn about DDR4 and DDR5 memories, and it seems that the Column-to-Column delay values (in clock cycles) are different depending on whether consecutive accesses are inter-...
Kraken's user avatar
  • 324
9 votes
2 answers
616 views

What is the theoretical maximum capacity of 72-pin RAM modules?

I'm asking, because the information on Wikipedia is extremely lackluster, perhaps even incorrect. This is my current understanding: A 72-pin module has 12 address pins, 4 CAS, and 4 RAS pins. (For ...
polemon's user avatar
  • 1,097
2 votes
1 answer
50 views

DS1220 vs X2816A

I have a legacy device from 1996 that uses a Dallas DS1220 NV RAM. The battery is shot and the device won't even boot. But if I swap in 6116 RAM chip, it comes up and works but of course won't save ...
Gusser's user avatar
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10 votes
3 answers
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Why do STM32 MCUs divide RAM into SRAM1 and SRAM2?

Why do STM32 MCUs divide RAM into SRAM1 and SRAM2? They seem contiguous, so that I could simply configure my linker to treat both as just one chunk of RAM. Should I do that? If not, how do I tell the ...
SRobertJames's user avatar
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0 votes
1 answer
202 views

MUX in a 4 bit by 3 bit memory

Here is a 3-bit adressable memory with an adress space of 4. My question is why is the book calling the 3 rightmost highlighted circuits MUXes? And what type of MUXes are they? 4:1 MUX? And if it is ...
oabdullae's user avatar
0 votes
1 answer
1k views

Calculate Memory Address

I know this is a simple arithmetic question for many of you, but I can't figure out how to solve this problem. In a uController (this is an example, it doesn't matter which one) SRAM1 has ...
KaleM's user avatar
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0 votes
1 answer
41 views

Ideas about generating images for E-Paper display

I am currently working on a project where I'm using a DA14531 BLE-module to collect data from some sensors and display the collected data on an E-paper display. As the display is quite large (400x300 ...
user294957's user avatar
1 vote
3 answers
128 views

PIC18 Bit-addressable RAM

Given that the PIC18 architecture does not provide any bit-addressable RAM, would it be a sane idea to utilize carefully considered unused bit-addressable SFR's? For example, if my project does not ...
myoutuber's user avatar
0 votes
2 answers
213 views

STM32H750B configuring DMA to transfer from GPIO to RAM

on STM32F769i I used DMA2 triggered by TIM1 to read data from GPIOB port like this so timer1 counted and when it triggered DMA read data in circular mode from GPIOB into my buffer ...
LaCalienta's user avatar
1 vote
1 answer
195 views

NVRAM data is reset to 0 when using NVIC_SystemReset()

I am working on nRF52840 with Mbed5.15. Trying to persist data in NVRAM. In the linker script nRF52840.ld I have something like this: ...
r0n9's user avatar
  • 133
1 vote
1 answer
139 views

How does DDR SDRAM increase the bandwidth without increasing the frequency at which a memory array operates?

I am reading about SDRAM, and how the bandwidth was increased with DDR optimizations. From my understanding DDR can send data at a rising and falling edge, effectively doubling the data being sent. ...
Diogo Landau's user avatar
0 votes
0 answers
119 views

Soldering to data bus of DDR3 ram

Lets say I solder a 2 inch, 30 AWG wire to each data pin on a DDR3 RAM module. Would this damage the RAM module enough to make it useless? Would the added resistance because of the wire cause a ...
suljic's user avatar
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0 answers
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Circuit for Read/Write RAM Control Signals

I have the following architecture of an 8-bit bus / RAM interface where the bus can read from and write to the SRAM: There are two 74LS245 8-bit bi-directional buffers, with there direction input ...
David777's user avatar
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0 votes
1 answer
2k views

How to write the scatter file for Keil uVision to force linker to allocate variables in SRAM?

Development environment I'm working with STM32F427 and I use Keil uVision V5.29 to develop my application. The version of the ArmCLang Compiler, of the Assembler and the linker is 6.131.1. Scatter ...
User051209's user avatar
3 votes
1 answer
238 views

How can I improve this RAM implementation in VHDL?

I'm practicing for a lab exam and I'm trying to solve one from past years. I feel like I'm doing something wrong because I don't have much experience with VHDL. Exam question Write the VHDL code for ...
iknotum's user avatar
  • 33
3 votes
2 answers
175 views

Why does RAM VHDL simulation output unexpectedly always shows zero?

I wrote VHDL to instantiate some RAM (256 bytes) using BRAM on a Digilent BASYS 3 FPGA development board using Vivado design tools. It takes 8 bits as the data input and outputs 8 bits on the output. ...
David777's user avatar
  • 1,555
0 votes
0 answers
323 views

Computer architecture: Count of RAM, ROM and I/O interface addressing

I am trying to work through this question and I appreciate any help or hint. Thank you Problem: A computer system uses RAM chips of size 512x8 and ROM chips of size 256x8. The computer system needs 4k ...
Node.JS's user avatar
  • 101
4 votes
0 answers
147 views

Is there any reference to design a 4*4 bit ram only using transistors

I'm currently doing a project and would like some help. I need to create a 4-bit 4-word RAM using PSPICE. (I'm both new to the PSPICE program and new to the topic of RAM) I currently have successfully ...
Alan Gabriel Reyes's user avatar
0 votes
1 answer
106 views

How are system clock and bus clock frequencies related?

I see a frequency in RAM specs which is different than the frequency of the system clock. Having a separate clock makes sense if RAM can't run at the same frequency, but is there a constraint that its ...
curiousgeorge's user avatar
0 votes
1 answer
216 views

How to allocate a constant array to RAM other than LUTs [closed]

I'm still pretty new to hardware design. Now I need to store a number of constants and then use them as indexes. My first idea is to declare registers, ...
xc wang's user avatar
  • 167
1 vote
0 answers
81 views

How to test DDR3 PC3 / DDR4 PC4 RAM works fine using a micro controller

I am trying to make a device that can test if above mentioned RAMs are working without a problem. Does anyone have a place to read about RAMs and how to test them. Any help would be appriciated.
Wedahitha Yapa's user avatar
0 votes
1 answer
250 views

What happens if malloc() fails in a microcontroller?

What happens if malloc() fails in a microcontroller (e.g., due to not enough data memory freed)? Does the watchdog timer triggers a timeout response (e.g., reboot) ...
chckx592's user avatar
3 votes
1 answer
228 views

Why did GDDR5X implement QDR?

DDR makes complete sense to me: it matches up the transition rate between the data signals and clock, so that twice the data can be sent over a bus without increasing the overall design bandwidth. The ...
Polynomial's user avatar
  • 10.8k
4 votes
2 answers
710 views

How is a bistable element formed with two inverters and two transistors in a 6T SRAM cell?

I'm trying to figure out how a charge can be stored between two CMOS inverters and two more transistors. I understand how the inverter works, just with a NMOS and PMOS base connected to a common ...
itisyeetimetoday's user avatar
1 vote
2 answers
1k views

How to see by how much a microcontroller program is out of data memory - inside MPLab X IDE

I have a problem that cannot exist. I keep building programs in MPLab that are close or just over my allotted RAM. I really want to see by how much over my RAM ("data memory" - why do they ...
Mr Man's user avatar
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0 votes
1 answer
121 views

Microcontroller, Flash EPROM and RAM combination questions

I have chosen a specific microcontroller (MCU) for a project, based on price, package size, and speed. It's the NXP LPC1768FBD100, a 100 MHz ARM-based MCU with 512 KB program memory and 64 KB SRAM. My ...
Elementronics's user avatar
0 votes
0 answers
107 views

Giving write enable signal externally by DIP switch to FPGA memory

I have designed a simple internal SRAM memory where I initiate the write enable and read enable via DIP switches. Verilog input wire has been declared in the simple memory read write which connects to ...
abunickabhi's user avatar
4 votes
0 answers
118 views

Can I use LPDDR3 memory that is larger than my processor supports?

I am working on a thing that uses a STM32MP157C. Its datasheet says: The STM32MP157C/F devices embed a controller for external SDRAM which support the following devices • LPDDR2 or LPDDR3, 16- or 32-...
Emily's user avatar
  • 141
0 votes
1 answer
156 views

Accessing data from a ddr3

I'am working on a new projet where I'm willing to access data from a ram, but the ram's specs is that they work with a frequency up to 667MHz , so I decided to choose an FPGA to work as controller ...
Nedou's user avatar
  • 316
0 votes
1 answer
101 views

Using a level triggered latch as a negative edge trigger for negative logic

I am a (relatively) new hobbyist and I am working on a project that uses an old video chip (v9938.) The chip is designed to use old DRAM, with a multiplexed 8 bit address bus, and *RAS and *CAS ...
user1958698's user avatar
2 votes
1 answer
307 views

VHDL FIFO w/ RAM

I've been tasked with designing a FIFO in VHDL for the block diagram below. I understand the general mechanism of how a simple FIFO works, but I've been struggling with how to connect the address from ...
AyyBotto's user avatar
1 vote
1 answer
136 views

I'm designing a 4-bit GPU and I need some suggestion about the RAM for it [closed]

I'm working a 4-bit GPU, the GPU run on 1.023MHz (1023kHz) clock while CPU only run on 127kHz so I need a screen buffer for it when the CPU is working on some instruction. The display I use is a 24 x ...
Sairext Irkaris's user avatar
2 votes
3 answers
603 views

Can I use logic inputs higher than Vcc but still in the operating voltage range of the IC?

I'm trying to create a battery-backed-up non-volatile RAM using an SRAM IC (AS6C1008 from Alliance Memory, datasheet). My idea for separating the backup battery from the main voltage source is to use ...
FZs's user avatar
  • 143
0 votes
2 answers
532 views

Microcontroller and Memory size allocation

Below are two custom made microcontrollers. The only difference between this is memory size. My question: Can someone tell me what is their start address and end address? Like, for the first one - ...
user avatar
0 votes
1 answer
205 views

ESP-PSRAM64 Termination Resistors

ESP-PSRAM64 uses a bidirectional QuadSPI interface at up to 133MHz. I am connecting this to an STM32 microcontroller. Normally I would use some series termination resistors at the source (e.g. for a ...
user1228123's user avatar
-1 votes
1 answer
2k views

STM32 How can I run code from ram?

I have this really simple "Hello world" piece of software (project attached), running on a STM32WB55 Nucleo board (basically, it sends "HELLO WORLD\n" via USART1, every 1000 ms). I ...
Paul Jon's user avatar
1 vote
1 answer
164 views

How to accumulate samples coming into a memory block without using another buffer i.e sum with previous corresponding samples?

So I have an 8k memory block in the FPGA. Samples come into it from outside the FPGA, from an ADC that has a source synchronous interface consisting of parallel transfers with a clock from the ADC. ...
quantum231's user avatar
1 vote
1 answer
430 views

What are my troubleshooting options for Hyperbus RAM?

I have a custom PCB with a STM32H7A3ZI MCU, and a S27KL0642S27KS0642 Hyperbus RAM. My code, as well as the app note (AN5050) I'm following sets up the RAM for memory mapped access. I believe I've ...
Drew's user avatar
  • 7,119
0 votes
1 answer
410 views

How come I can play audio in my ESP8266?

I'm currently messing with the ESP8266Audio Library. I uploaded a sketch to my ESP8266 that uses a HTTP stream of MP3 from the web and plays it using some MP3 decoder. So basically the loop looks like ...
YoavKlein's user avatar
  • 235
7 votes
1 answer
1k views

Enable vendor-disabled hardware on tablet? [closed]

I have a nextbook tablet (one of those cheap things from walmart) that I was looking to try to improve the RAM situation on to breath some new life into it as it apparently only has 1G of it. I ...
Adam V's user avatar
  • 89
1 vote
1 answer
101 views

How much memory does the 23LC1024 have?

The Microchip 23LC1024 chip is said to have 1Mbit of memory. Looking at Wikipedia, it says that a Mbit is 10^6 bits. Is that so? I mean, is this decimal Mbit? It doesn't seem reasonable to me..
YoavKlein's user avatar
  • 235
1 vote
1 answer
555 views

Where is the RAM stored on a RISC-V CPU? [closed]

Does RISC-V have any opinion on whether the RAM is stored on the same chip as the CPU (like on ARM devices) or on a separate chip somewhere on the motherboard (like on an x86 desktop)? I assume that ...
Aaron Franke's user avatar
3 votes
4 answers
4k views

What does High-Impedance mean in digital systems?

I'm currently messing with the Microchip 23LC1024 SPI RAM chip, and trying to read the datasheet to understand how to work with it. I'm not an electronics engineer or something like that, I'm a ...
YoavKlein's user avatar
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