Questions tagged [ram]
RAM is an abbreviation for Random Access Memory. A type of memory in which the information can be accessed from random location.
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What kinds of memory is used in a Casio HS-8VA vs a TI-84 calculator? [closed]
If I had to guess, I'd assume 4 function calculators only use SRAM because that's what's usually used for CPU caches and the HS-8VA probably only has that. Since TI-84's seem like full computers I ...
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Using BRAM as buffer
I'm trying to implement a buffer for an image processing pipeline and need to load data into BRAM.
I've been following an online tutorial (https://www.youtube.com/watch?v=n35zS__YEFQ) for implementing ...
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Xilinx BRAM outputs wrong values
I am trying to set up an I2C communication between a Xilinx Zynq-7000 SoC-FPGA and an external micro controller. The FPGA is the slave and an external micro controller is the master. The micro ...
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tri-state RAM switch
The picture shows the truth table of control operation of a RAM. If you disable the OE pin the output can not come to the bus because of high impedance, now the question is, is the impedance ...
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What does the “In-line” in SIMM and DIMM memory mean?
I've been searching for what exactly the "in-line" part means but I don't get it. Is it the way the chips are positioned, as in a line? If it is, is there another possible configuration?
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How is a memory location accessed by random access?
This is a comment that I saw in another forum:
Like any other memory storage, it's divided into smaller units. These units can contain data individually or can be treated as a big single block of ...
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Termination resistors for RAM vs drive strength
I'm considering using a RAM IC (S27K HyperRAM from Cypress).
The layout guidelines document suggests adding series resistors "if necessary."
However, the datasheet for the device has a ...
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How do you figure out the decoder inputs for a memory expansion?
How do you know what the two inputs will be for this 2-to-4 decoder? Also, what changes would be made to the circuit if the 2 data lines are not the same?
The original problem:
I drew the circuit, ...
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1answer
108 views
Paging out ROM after boot up
Building a Z80 computer, would like to boot CP/M from ROM and switch the ROM off after initial boot to make whole 64k RAM available for the CPU.
Solution I've got so far is using a flip-flop to ...
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How do I get the number of address lines of 12G * 64?
The example problems I'm seeing in the book gives me nice numbers where the size of the ram can easily fit into a power of 2, but this one doesn't.
The original question:
This is all I have:
I was ...
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Simple CPU with lots of RAM
Chips like the ESP8266 or ESP32 typically only have a couple of hundred kB of RAM. Alternatively, you can buy boards with chips like the NXP i.MX 6, with which you can have gigabytes, but suddenly you'...
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How does radiation produce transient bit errors in DRAM?
Ionizing radiation can produce transient bit errors in volatile RAM. What is the exact mechanism by which this occurs?
E.g., is there a threshold energy level for a single photon or neutron to ...
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Fastest way to search RAM
I want to search RAM for a value, does anyone know which implementation will be the fastest. Im assuming that parallel search will be required.
My implementation would be to use a DeMux for each ...
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36 views
Unexpected behaviour of data memory in modelsim testbench
I am describing a very simple ram memory in VHDL and observing strange behaviour which I do not
understand nor am able to debug. I have similar code written elsewhere and I suspect that rewriting it ...
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FPGA, DDR3 Layout
In my new project I use a FPGA to load some data into a DDR3 RAM.
Can I directly connect the I/Os of the RAM with the I/Os of the FPGA? Or do I passive components in between them?
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Global variable - memory allocation
I am in general interested about how compiler and linker handle global variables. Here click it is explained that additional ROM is needed in case variable is initialized and not 0.
So wondering, why ...
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What does the 8086 CPU do with the data returned from an address in RAM?
I understand how a CPU works fairly well, but there is this one thing which I've never really gotten the hang of.
Say we have an Intel 8086 CPU (16 bits wide registers) which is about to fetch its ...
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1answer
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Cache comparator usage
Referring to the photo below, in direct-mapping cache design, why we need a comparator to compare between the tag in the address and the tag in the cache?
Isn't a valid bit enough?
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Why is bool type typically 1 byte long?
I was reading: https://www.quora.com/Why-is-the-bool-type-typically-8-bits-long
And the answer was:
Because it’s the smallest type that has an individual memory address
so that you can take a pointer ...
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2answers
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Is M1 Chip Memory Considered as Registers?
Given the following image of Apple's m1 chip, we can clearly see that RAM is so close to the CPU:
does this say that RAM will be much faster when compared to others Macbook models (Since distance is ...
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2answers
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Is there a proper way in VHDL/Verilog to access block RAM given a multi-hot vector?
I am currently trying to learn how to program in VHDL with the goal of implementing an LDPC decoder in hardware. My understanding is that log-likelihood ratios (LLRs) serve as inputs to the decoder.
...
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1answer
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Using DDR4 RAM instead of SRAM
Currently I am using the internal BlockRAM from a FPGA to safe the samples I am getting from an ADC with a frequency of 200MHz. In the future, I want to use equivalent time sampling to get a virtual ...
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Why is it easier to implement bytes as 8 bits rather than 9 bits? [duplicate]
From book to book I always find the same sentence. For example:
8 bits is an even power of 2, which makes it somewhat easier to design computer hardware with 8-bit bytes than with 9-bit bytes.
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What memory operation gets inferred when read port datawidth is larger than physical BRAM width? Xilinx 7-series + Verilog
From the 7 Series Memory Resources User Guide (page 11):
The block RAM in Xilinx® 7 series FPGAs stores up to 36 Kbits of data and can be configured as either two independent 18 Kb RAMs, or one 36 Kb ...
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Capacitors between multiple positive power rails in cpu power system
Many years ago, when I was working in samsung aftermarket supply chain with set top box repairs I had access to basic schematic of one of stb. In a power supply part for powering RAM there were a few ...
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Storing Program Instructions on FPGA
I am creating a basic RISC processing core on a FPGA development board (Nexys A7-100t).
I created a RAM block that will be used to store the instructions that my basic processor will execute to run a ...
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2answers
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Memory Selection and NOT Gate in Embedded System
I'm currently studying Embedded Systems and in the topic of drawing a schematic for the address of a microprocessor (16bits address x 8 bit data (64Kbytes)) with 1 ROM 32Kx8 and 1 RAM 32Kx8, I simply ...
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DRAM, multi-channel, memory access
I'm looking for a way, under any configuration/OS(windows or linux)/programming language you suggest to simultaneously access memory addresses, that are under different channels, meaning the access ...
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3answers
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Internal and external storage for a FPGA
I want to store at least 2Mbits on a FPGA. What is the normal practice for storing data on a FPGA internally?
Also, if I wanted to store 4GBytes externally, how would I go about doing this? Is it ...
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My understanding of computer hardware architecture
Forgive my above crude diagram.
Assume the above is the hardware architecture for a computer/mobile phone or any device which hold a microprocessor.
Please let me know whether my understanding is ...
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DDR3, Data Mask Pin-swap within a given byte lane
Is it possible to swap "Data Mask" or "Data Strobe" pins with DQx pins within the same byte lane.
In Freescale's "Hardware and Layout Design Considerations for DDR3 SDRAM ...
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Using VHDL integer_vector for a block ram type, how to restrict the integer range?
Trying to simply infer block rams in a design with varying depths and widths. I'd like to have one ram definition since it is going to use a vendor specific attribute and it seems like a good idea to ...
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understanding data semantics and diagram
According to http://www.auto-diagnostics.info/pdf/ford_eectch98.pdf page 10, "The 8361 ROM chip contains 8k bytes of program memory plus 128 bytes of additional RAM."
I found two diagrams ...
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How to Simulate VHDL when Using a Vendor's Tool Generated Instantiation Code?
I'm working with a Gowin FPGA and they recommend instantiating block RAM. That sounds great, but how do I simulate that? I would expect there to be a library with the model for the instantiation ...
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How to Use Addresses with Single Port RAM on FPGA
I am trying to understand this example of single port memory where an 8 by 64 bit RAM is created. If I am understanding correctly, the section of code that says "reg [7:0] ram [63:0]" means ...
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Calculating RAM memory capacity from schematic symbol
Is it possible to calculate the memory capacity of a RAM given its schematic symbol?
I made a first guess from an example but seems to be incorrect:
If the address bus is 15-bit width, there are a ...
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4 address lines for 1 bit input
I am currently trying to design a 16 nibble RAM on logisim, whereby it takes 4 data input lines.
However, what I am having the most trouble with is converting the 4 address lines into a single input, ...
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2answers
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How is 1 bit transfered from RAM to a 1 bit register?
I've been reading on computer RAM and CPUs. I came to the conclusion that most RAM today use arrays of DRAM while CPU registers and caches use SRAM. 1 bit DRAM is a circuit with one capacitor and 1 ...
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Vivado VHDL BRAM write-read Simulation not reading properly
So im trying to simulate a simple write and read memory program in Vivado design suite.
Before implementing a clock in the sensitivity list on the process to write and read, the reading part used to ...
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VHDL Type memory question
My question is very simple i think, but i would be really gratefull if anyone can help me with this.
When i want to write in the fpga memory using the classic following line code:
...
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3answers
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Is this the correct w recognize Opcodes for a DIY 8bit Processor
simulate this circuit – Schematic created using CircuitLab
i am starting with designing a 8bit computer and probably turn it into reality , so lets say i start with a 8bit 32kb memory and i want ...
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Can I use a 16bit memory with an 8 bit processor?
The address bus is typically a double octet wide (i.e. 16-bit), due to practical and economical considerations. This implies a direct address space of only 64 kB on most 8-bit processors
This quote ...
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How can I access more than 15 addresses of data from my 8 bit incomplete computer?
Last year I started researching upon how computers work, so I started making one, at least on paper last month, but I ran into a serious problem that isn't getting a satisfying answer from any article ...
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1answer
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Why do DDR RAMs have both xDQ and xDM signals?
DDR2 RAMs have these control signals
RAS, CAS - address strobes
UDQ, LDQ - byte strobes
WE - write enable
UDM, LDM - write mask
Why do we need UDM and LDM? Can't you write a byte by asserting WE and ...
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Can you desolder and upgrade RAM in Pi boards?
Friendly Electronics has come out with a great small compact but very powerful board. It is called the Nano Pi fire 3. It has 8 cores which is great for programers like myself who want to utilize the ...
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How can I improve my testbench for testing a 1024x4 RAM memory in Verilog
This is a question following on from my previous one "How can I improve my testbench for testing a 1024x4 RAM memory in Verilog".
Basically, I have modified the previous solution in an ...
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How to decide when to use flop or RAM based fifo?
Trying to figure out what are the tradeoff like power, size when deciding between using a flop or RAM based fifo ? Any known publications ?
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pseudo dual port RAM in verilog
How to design pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ?
Clarification on 'pseudo' dual port - single port RAM (1RW)...
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How Does One Do Block RAM Inference on Altera Cyclone 10 LP FPGA Boards in Verilog [closed]
I have tried to google for this a lot but I can't seem to find anything.
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What can I do to improve my test bench for testing a 64x4 RAM memory in Verilog
What can I do to improve my test bench for testing a 64x4 RAM memory in Verilog to obtain the desired result?
I have written a test bench to test a simple 64x4 RAM memory in Verilog and it seems to &...
