Questions tagged [ram]
RAM is an abbreviation for Random Access Memory. A type of memory in which the information can be accessed from random location.
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RAM keeps giving incompatible widths error in Logisim [closed]
Im using Logisim, and I have to transfer bits from RAM into a universal shift register.
Then from there back into RAM from a serial adder.
However, the RAM output is showing up blue meaning its not ...
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Can I use LPDDR3 memory that is larger than my processor supports?
I am working on a thing that uses a STM32MP157C. Its datasheet says:
The STM32MP157C/F devices embed a controller for external SDRAM which support the following devices
• LPDDR2 or LPDDR3, 16- or 32-...
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Accessing data from a ddr3
I'am working on a new projet where I'm willing to access data from a ram, but the ram's specs is that they work with a frequency up to 667MHz , so I decided to choose an FPGA to work as controller ...
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Using a level triggered latch as a negative edge trigger for negative logic
I am a (relatively) new hobbyist and I am working on a project that uses an old video chip (v9938.) The chip is designed to use old DRAM, with a multiplexed 8 bit address bus, and *RAS and *CAS ...
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VHDL FIFO w/ RAM
I've been tasked with designing a FIFO in VHDL for the block diagram below. I understand the general mechanism of how a simple FIFO works, but I've been struggling with how to connect the address from ...
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I'm designing a 4-bit GPU and I need some suggestion about the RAM for it [closed]
I'm working a 4-bit GPU, the GPU run on 1.023MHz (1023kHz) clock while CPU only run on 127kHz so I need a screen buffer for it when the CPU is working on some instruction. The display I use is a 24 x ...
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Can I use logic inputs higher than Vcc but still in the operating voltage range of the IC?
I'm trying to create a battery-backed-up non-volatile RAM using an SRAM IC (AS6C1008 from Alliance Memory, datasheet).
My idea for separating the backup battery from the main voltage source is to use ...
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Microcontroller and Memory size allocation
Below are two custom made microcontrollers. The only difference between this is memory size.
My question:
Can someone tell me what is their start address and end address? Like, for the first one - ...
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ESP-PSRAM64 Termination Resistors
ESP-PSRAM64 uses a bidirectional QuadSPI interface at up to 133MHz. I am connecting this to an STM32 microcontroller. Normally I would use some series termination resistors at the source (e.g. for a ...
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STM32 How can I run code from ram?
I have this really simple "Hello world" piece of software (project attached), running on a STM32WB55 Nucleo board (basically, it sends "HELLO WORLD\n" via USART1, every 1000 ms).
I ...
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How to accumulate samples coming into a memory block without using another buffer i.e sum with previous corresponding samples?
So I have an 8k memory block in the FPGA. Samples come into it from outside the FPGA, from an ADC that has a source synchronous interface consisting of parallel transfers with a clock from the ADC. ...
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What are my troubleshooting options for Hyperbus RAM?
I have a custom PCB with a STM32H7A3ZI MCU, and a S27KL0642S27KS0642 Hyperbus RAM.
My code, as well as the app note (AN5050) I'm following sets up the RAM for memory mapped access.
I believe I've ...
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How come I can play audio in my ESP8266?
I'm currently messing with the ESP8266Audio Library. I uploaded a sketch to my ESP8266 that uses a HTTP stream of MP3 from the web and plays it using some MP3 decoder. So basically the loop looks like ...
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Enable vendor-disabled hardware on tablet? [closed]
I have a nextbook tablet (one of those cheap things from walmart) that I was looking to try to improve the RAM situation on to breath some new life into it as it apparently only has 1G of it. I ...
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How much memory does the 23LC1024 have?
The Microchip 23LC1024 chip is said to have 1Mbit of memory. Looking at Wikipedia, it says that a Mbit is 10^6 bits. Is that so? I mean, is this decimal Mbit? It doesn't seem reasonable to me..
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Where is the RAM stored on a RISC-V CPU? [closed]
Does RISC-V have any opinion on whether the RAM is stored on the same chip as the CPU (like on ARM devices) or on a separate chip somewhere on the motherboard (like on an x86 desktop)? I assume that ...
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What does High-Impedance mean in digital systems?
I'm currently messing with the Microchip 23LC1024 SPI RAM chip, and trying to read the datasheet to understand how to work with it. I'm not an electronics engineer or something like that, I'm a ...
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How to connect a 23LC1024 to a breadboard?
I just got my 23LC1024-E/ST module, and I realized how tiny it is. How do people work with this? It's obviously not breadboard friendly. Are there RAM modules out there for Arduinos/ESP8266s that are ...
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How prevalent is adoption of IEC and/or IPC standards among the major electronics manufacturers, especially CPU makers like Intel & AMD?
I spent part of the weekend learning about the history of the International Electrotechnical Commission (IEC) and IPC (originally an abbreviation for Institute of Printed Circuits) and their standards....
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Memory in FPGA: buffer to store bytes "sent" by SPI Slave
I asked before what SPI slave is and how the received data could be stored...
SPI slave collect a byte a sent it to FIFO as a temp buffer and the next step is to send the bytes to a memory. I have ...
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Problem of metastability: simulation of dual port ram
i simulate Dual Port Ram Register in VHDL and have some doubts about the metastability problem.
Dual Port Ram has 2 clock signal, one for Port A , the second for Port B. In my simulation I create two ...
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Using BRAM as buffer
I'm trying to implement a buffer for an image processing pipeline and need to load data into BRAM.
I've been following an online tutorial (https://www.youtube.com/watch?v=n35zS__YEFQ) for implementing ...
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tri-state RAM switch
The picture shows the truth table of control operation of a RAM. If you disable the OE pin the output can not come to the bus because of high impedance, now the question is, is the impedance ...
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What does the "In-line" in SIMM and DIMM memory mean?
I've been searching for what exactly the "in-line" part means but I don't get it. Is it the way the chips are positioned, as in a line? If it is, is there another possible configuration?
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How is a memory location accessed by random access?
This is a comment that I saw in another forum:
Like any other memory storage, it's divided into smaller units. These units can contain data individually or can be treated as a big single block of ...
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Termination resistors for RAM vs drive strength
I'm considering using a RAM IC (S27K HyperRAM from Cypress).
The layout guidelines document suggests adding series resistors "if necessary."
However, the datasheet for the device has a ...
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How do you figure out the decoder inputs for a memory expansion?
How do you know what the two inputs will be for this 2-to-4 decoder? Also, what changes would be made to the circuit if the 2 data lines are not the same?
The original problem:
I drew the circuit, ...
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Paging out ROM after boot up
Building a Z80 computer, would like to boot CP/M from ROM and switch the ROM off after initial boot to make whole 64k RAM available for the CPU.
Solution I've got so far is using a flip-flop to ...
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How do I get the number of address lines of 12G * 64?
The example problems I'm seeing in the book gives me nice numbers where the size of the ram can easily fit into a power of 2, but this one doesn't.
The original question:
This is all I have:
I was ...
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Simple CPU with lots of RAM
Chips like the ESP8266 or ESP32 typically only have a couple of hundred kB of RAM. Alternatively, you can buy boards with chips like the NXP i.MX 6, with which you can have gigabytes, but suddenly you'...
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How does radiation produce transient bit errors in DRAM?
Ionizing radiation can produce transient bit errors in volatile RAM. What is the exact mechanism by which this occurs?
E.g., is there a threshold energy level for a single photon or neutron to ...
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Fastest way to search RAM
I want to search RAM for a value, does anyone know which implementation will be the fastest. Im assuming that parallel search will be required.
My implementation would be to use a DeMux for each ...
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Unexpected behaviour of data memory in modelsim testbench
I am describing a very simple ram memory in VHDL and observing strange behaviour which I do not
understand nor am able to debug. I have similar code written elsewhere and I suspect that rewriting it ...
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FPGA, DDR3 Layout
In my new project I use a FPGA to load some data into a DDR3 RAM.
Can I directly connect the I/Os of the RAM with the I/Os of the FPGA? Or do I passive components in between them?
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Global variable - memory allocation
I am in general interested about how compiler and linker handle global variables. Here click it is explained that additional ROM is needed in case variable is initialized and not 0.
So wondering, why ...
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What does the 8086 CPU do with the data returned from an address in RAM?
I understand how a CPU works fairly well, but there is this one thing which I've never really gotten the hang of.
Say we have an Intel 8086 CPU (16 bits wide registers) which is about to fetch its ...
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Cache comparator usage
Referring to the photo below, in direct-mapping cache design, why we need a comparator to compare between the tag in the address and the tag in the cache?
Isn't a valid bit enough?
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Why is bool type typically 1 byte long?
I was reading: https://www.quora.com/Why-is-the-bool-type-typically-8-bits-long
And the answer was:
Because it’s the smallest type that has an individual memory address
so that you can take a pointer ...
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Is M1 Chip Memory Considered as Registers?
Given the following image of Apple's m1 chip, we can clearly see that RAM is so close to the CPU:
does this say that RAM will be much faster when compared to others Macbook models (Since distance is ...
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Is there a proper way in VHDL/Verilog to access block RAM given a multi-hot vector?
I am currently trying to learn how to program in VHDL with the goal of implementing an LDPC decoder in hardware. My understanding is that log-likelihood ratios (LLRs) serve as inputs to the decoder.
...
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Using DDR4 RAM instead of SRAM
Currently I am using the internal BlockRAM from a FPGA to safe the samples I am getting from an ADC with a frequency of 200MHz. In the future, I want to use equivalent time sampling to get a virtual ...
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Why is it easier to implement bytes as 8 bits rather than 9 bits? [duplicate]
From book to book I always find the same sentence. For example:
8 bits is an even power of 2, which makes it somewhat easier to design computer hardware with 8-bit bytes than with 9-bit bytes.
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Capacitors between multiple positive power rails in cpu power system
Many years ago, when I was working in samsung aftermarket supply chain with set top box repairs I had access to basic schematic of one of stb. In a power supply part for powering RAM there were a few ...
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Storing Program Instructions on FPGA
I am creating a basic RISC processing core on a FPGA development board (Nexys A7-100t).
I created a RAM block that will be used to store the instructions that my basic processor will execute to run a ...
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Memory Selection and NOT Gate in Embedded System
I'm currently studying Embedded Systems and in the topic of drawing a schematic for the address of a microprocessor (16bits address x 8 bit data (64Kbytes)) with 1 ROM 32Kx8 and 1 RAM 32Kx8, I simply ...
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DRAM, multi-channel, memory access
I'm looking for a way, under any configuration/OS(windows or linux)/programming language you suggest to simultaneously access memory addresses, that are under different channels, meaning the access ...
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Internal and external storage for a FPGA
I want to store at least 2Mbits on a FPGA. What is the normal practice for storing data on a FPGA internally?
Also, if I wanted to store 4GBytes externally, how would I go about doing this? Is it ...
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My understanding of computer hardware architecture
Forgive my above crude diagram.
Assume the above is the hardware architecture for a computer/mobile phone or any device which hold a microprocessor.
Please let me know whether my understanding is ...
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DDR3, Data Mask Pin-swap within a given byte lane
Is it possible to swap "Data Mask" or "Data Strobe" pins with DQx pins within the same byte lane.
In Freescale's "Hardware and Layout Design Considerations for DDR3 SDRAM ...
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Using VHDL integer_vector for a block ram type, how to restrict the integer range?
Trying to simply infer block rams in a design with varying depths and widths. I'd like to have one ram definition since it is going to use a vendor specific attribute and it seems like a good idea to ...
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