Questions tagged [ram]
RAM is an abbreviation for Random Access Memory. A type of memory in which the information can be accessed from random location.
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Why can't dual port RAM be read out using the Quartus In-System Memory Content Editor?
Here are the screen shots from Quartus;
When I want to instantiate the single port RAM, I get option to assign an instance ID and thus read it using the ISMCE (In-System Memory Content Editor). ...
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0answers
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Dual-die FBGA RAM compatibility with older single-die
I have a small Smart TV running Android 6, which only comes with 512 MB RAM.
On the board close to the CPU are 1 NAND IC and 2x H5TQ4G63CFR which are 4Mb each. I would imagine one is for main memory ...
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1answer
37 views
Does RAM always use a big Mux to ‘read’ from its addresses?
I’ve designed a 64 bit (16 words * 4-Bits at each location) RAM in logic simulation software, using simple registers. I had to create a 16-to-1, 4-bit wide Mux (no mean feat) in order to ‘select’ one ...
2
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1answer
567 views
How can multiple ICs access shared RAM?
I'm trying to build a game console from scratch (as an exercise, not necessarily for practicality).
What I want to do is to have multiple "CPUs", in this case one being the Main CPU and the other one ...
0
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1answer
53 views
Why do we need interleaved memory?
I am trying to understand the DRAM working paradigm. I just read this article about interleaved memory. It says:
Interleaved memory results in contiguous reads (which are common both
in ...
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1answer
53 views
How to free up memory in a CircuitPython board?
I'm using a Feather M0 Express from Adafruit with a DS3231 Precision RTC FeatherWing for a custom clock project that displays time with LEDs.
The clock works as follows:
When the clock gets plugged ...
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1answer
79 views
Thevenin Theorem seems to not work in this 1 bit RAM RC circuit
I have a problem which consist in 1 bit RAM made of 3 MOSFETs. One of the questions is to calculate the maximum voltage that the memory element can receive. I have obtained the result by inspection (...
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2answers
54 views
SRAM: Purpose of Upper and Lower Byte Enable when Data Bus is greater than 8-bits?
What is the point of an upper byte and lower byte enable on an SRAM if the data bus is already 16-bits?
Is it related to multiplexing? I had always assumed that SRAMs were either designed with either ...
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1answer
30 views
What do CT numbers in SO-DIMM RAMs mean? [closed]
Here is a picture from the "crucial" website. I am trying to understand:
What is the difference between buying 2 separate 8GB sticks and one kit of two sticks.
What do the CT numbers mean and why are ...
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0answers
41 views
Addressing the RAM on the DS1302 RTC timer chip with an Arduino
I'm trying to access the RAM of my DS1302 RTC chip. According to the data sheet, I need to clear bit 7 of the control register. The control register can be accessed at address 8Eh.
To test this out, ...
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0answers
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6T SRAM write operation calculations
C: Cut off , L: Linear , S : Saturation
[keep in mind I am teaching this to myself ahead of time]
I understand how to go about finding desired ratio (W/L) for read operation. In the image, M1 would ...
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1answer
47 views
Accessing RAM on TERASIC DE0 Nano
I'm just wondering how to access more than 32Kb on a TERASIC DE0 nano. It is based on an Altera Cyclone IV FPGA. https://www.ti.com/lit/ug/tidu737/tidu737.pdf
It has 32Mb DRAM but there are
12 ...
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0answers
50 views
DDR3 SODIMM slow clock specification
I am considering to design memory controller handling 1GB of the RAM. I did already design controller for Micron's 32MB SDRAM in the past using Cyclone III device.
The new design is for retro ...
0
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3answers
68 views
External Memory IC which increments data on a clock pin
I am searching, with no success, in multiple categories of the external memory IC market for a chip that can do the following:
Store 1MB of data of 16-bit data
This data is stored at specific ...
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7answers
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Can we not simply connect a battery to a RAM to prevent data loss during power cuts?
So, I was just wondering about how volatile memory storage loses data when the power to them is cut off. But can we not solve that problem by using a battery in conjunction with a RAM and a ROM and ...
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1answer
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Cortex M4 memory management suggestions: best data/code placement
I'm trying to implement a rather complex (at least for me!) system on a Cortex M4 mcu: LPC4370. This one has HighSpeed ADC (up to 80Msps), DMA and DSP (Single Instruction Multiple Data) instructions.
...
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1answer
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Is writing in FeRAM memory cell destructive?
I have read that writing in Ferroelectric random access memory is not destructive. But in a WL||PL memory architecture, if I try to write a '0' in a cell and the adjacent cell holds a '1', shouldn't ...
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2answers
61 views
How does a computer address ddr 4 sdram memory?
I want to be able to manual address a 4gb ddr4 memory stick. looking at the datasheet for ddr 4 there are only address pins from A0 to A17 which is 18 bits, 2^18 = 262, 144 address spaces. So how does ...
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3answers
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RAM and Flash structure difference
I am trying to get a better understanding for RAM and Flash and I hope you could help me out with some things.
What I know about Flash (or at least I think to know), is that there are different Flash ...
6
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1answer
201 views
DDR3 Data Errors
I am looking for post layout solutions for DDR3 data errors.
I have a PCB with a FPGA and a 2 banks (2 rank) DDR3 ram setup.
Data errors occur either when the RAM (FPGA is not confirmed, but could ...
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1answer
44 views
Find ROM and RAM in .bin file for micro controller
I use the Arduino IDE to compile some code to a 32-bit ARM Cortex-M3 based microcontroller.
The result of the compilation is <...
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1answer
170 views
What is the point of inverting RAM output?
The 74LS189 is a 4 bit RAM IC. The datasheet specifies that the output of the chip is inverted. Thus, if you put 1011 into address 1, when you read back address 1 ...
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2answers
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DDR UDQS and LDQS into one DQS controller
I have one x16 memory chip () that has two Data Strobe pairs (UDQS and LDQS), on the other hand, I have arm chip (i.MX6 ULZ) that has one Data Strobe pair (DQS). Is there any way of connecting them, I'...
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2answers
57 views
Running code from different storage
So i know this question is being asked almost everyday on thousands of forums, but i am still going to ask that same question but with a different intent.
Question #1:
As an example lets use linux ...
5
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2answers
380 views
Why have apparent memory bitflips in non-ECC memory not increased?
Back in the early 2000s I remember asking about why it was so important that servers use ECC memory. The prevailing wisdom at the time was that systems with lots of RAM would be, statistically, more ...
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4answers
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Why is this clock signal connected to a capacitor to gnd?
I am trying to understand the following circuit:
My problem is to understand why the CLK signal is connected to the capacitor (C7). The bottom side of C7 is connected with a resistor to GND. This ...
0
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1answer
30 views
Can more than one memory device transmit on the data bus at once?
I know that in general only one device can transmit over the bus at once, but if they are all memory devices, can they act as one? I have four 256x8 chips, which I think means that I have 256 cells ...
0
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1answer
271 views
Single Clock FIFO with Single Port RAM
I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...
0
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1answer
147 views
Home-brew cpu ram
I’m trying to build a cpu out of ttl logic chips. I’ve just about got everything finished, however, I’m still working on the ram. I don’t have any suitable ram chips I can use, however, I do have a ...
0
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1answer
68 views
Writing and reading from and to SRAM memory [closed]
im just learning SRAM.
I wanted to ask, consider the 4x4 memory cell array below
If i wanted to select a word line or row, would the row decoder be a 4x1 multiplexer where each wordline is connected ...
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1answer
80 views
How to validate that a function is executing from RAM?
I'm trying to execute a control function as quickly as possible from SRAM on an STM32F3xx using GCC (System Workbench toolchain).
...
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1answer
472 views
RAM Row and Column Decoders
I keep seeing similar diagrams of RAM like this abstract picture of a simplified RAM Layout. So I just arbitrarily selected this picture but my question is about this layout in general. My ...
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3answers
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Why does RAM (any type) access time decrease so slowly?
This article shows that DDR4 SDRAM has approximately 8x more bandwidth DDR1 SDRAM. But the time from setting the column address to when the data is available has only decreased by 10% (13.5ns).
A ...
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1answer
552 views
connect Micron SDRAM to STM32H7 FMC but what should I do with DQM pin?
I plan to connect SDRAM from MICRON MT48LC series ( datasheet. The pin connection diagram is automatic generate by STM32CubeMX ( STM32H743 ). The setting is an 8-bit data bus, a 13-bit address, 4 ...
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2answers
69 views
Better way to selectively enable memory chips
I'm designing a computer using a Z80 CPU. I have one EEPROM chip and two RAM chips, so far. I have to do things like this:
To ensure that this specific RAM chip is only enabled when the 13th and 15th ...
0
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1answer
59 views
iPAQ Backup Battery Connector
I've used an H4155 on and off for about a decade now and every two years or so the backup battery begins to increase in standby voltage and fail. I prefer to replace it just for the sake of it ...
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2answers
569 views
PCB - Ram connectors problem
Currently following an schematic for NanoPI NEO4 to make my own RK3399 board.
On their schematic for the K4B4G1646D-BCK0,I noticed for pins DQ1-DQ15 on both chips connect to a randomised list of ...
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2answers
249 views
Designing a RAM, using 4x2 chips, with a 8 address capacity
This is a typical exam question, and I've seen some very helpful posts about, but I still have a lot of doubts.
Given an integrated circuit of certain dimensions, for this example a 4x2, I have to ...
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2answers
84 views
What design differences make ram faster than ssd for read/write [closed]
I understand that RAM is connected directly to the CPU via a high bandwidth bus, and SSD is a peripheral, but my assumption is that there are also electrical design differences (e.g. memory cell ...
0
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2answers
382 views
Are SSDs true random-access devices?
Since all kinds of flash memories feature different transfer rates according to the kind of operation performed at a given moment (e.g., random access reads versus random access writes, random access ...
0
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1answer
253 views
On AVR-GCC, how can I find out what statically initialized variable is using up my RAM?
The variable does not show up on the MAP file so it is hard to track it down. I'd rather not have to manually search though all the source code looking for static initializers.
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2answers
186 views
Z80 RD and WR to RD/WR?
This may sound like a very stupid question. However, I am new to the Z80 stuff. I am planning on how to connect the Z80 control signals to a SRAM. But the Z80 has seperate RD and WR, while my SRAM has ...
0
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1answer
46 views
Using narrower DDR RAM than controller
I have some ARM processor that have 72-bit width (8 for ECC) RAM controller.
Can I buy eg. two 32bit chips and combine them? If yes then how?
Can I buy just one 32bit and pull down rest of data pins ...
0
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1answer
87 views
use sram as logic analyzer?
So I was thinking of buying a logic analyzer and found that a lot of the cheap ones are good to only a few mhz, and the microcontroller based ones can't have big buffers. So I was wondering if I could ...
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1answer
60 views
Ebedded Linux: Recoverable, battery backed-up RAM (/tmp) [closed]
I hope this is an appropriate place for this question as it involves the use of the kernel.
I have an embedded system with a battery backup for the RAM chip. The battery also allows for the MCU to ...
0
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1answer
339 views
how to access the same RAM module from different modules?
I have a cyclone v gx starter kit. It comes with 4884 bits onchip memory.
I want to write a module for accessing the onchip memory.
So, I have generated the ram ip reference design from ip catalog ...
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3answers
675 views
Is there a lower limit on operating frequency of CMOS SRAM?
I study computer science, and so I am in the deep end here.
I have set upon designing a machine which requires RAM. I found a listing for Toshiba's 128KB (8 bit per word) SRAM (TC551001BPL).
I intend ...
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1answer
76 views
Does building a RAM with more storage lead to decrease in performance? [closed]
Talking about Single channel DDR Ram,
If say one RAM module were 4 GB, another 8GB.
Is there any performance difference between those two?
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1answer
328 views
Why is there seemingly no delay in a block ram read
I am trying to learn Verilog and was curious why my FPGA's block ram seems to provide the data that I request instantly. I was expecting that there would be some number of clocks that I would need to ...
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5answers
393 views
What to call the cells of memory in a computer or a microcontroller?
I don't know if this is the right forum to post this question, but I thought so because this forum is for educators and I'm a trainer and my question is related to education.
I want to do an ...
