Questions tagged [ram]
RAM is an abbreviation for Random Access Memory. A type of memory in which the information can be accessed from random location.
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Why is bool type typically 1 byte long?
I was reading: https://www.quora.com/Why-is-the-bool-type-typically-8-bits-long
And the answer was:
Because it’s the smallest type that has an individual memory address
so that you can take a pointer ...
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Is M1 Chip Memory Considered as Registers?
Given the following image of Apple's m1 chip, we can clearly see that RAM is so close to the CPU:
does this say that RAM will be much faster when compared to others Macbook models (Since distance is ...
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Is there a proper way in VHDL/Verilog to access block RAM given a multi-hot vector?
I am currently trying to learn how to program in VHDL with the goal of implementing an LDPC decoder in hardware. My understanding is that log-likelihood ratios (LLRs) serve as inputs to the decoder.
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Using DDR4 RAM instead of SRAM
Currently I am using the internal BlockRAM from a FPGA to safe the samples I am getting from an ADC with a frequency of 200MHz. In the future, I want to use equivalent time sampling to get a virtual ...
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Why is it easier to implement bytes as 8 bits rather than 9 bits? [duplicate]
From book to book I always find the same sentence. For example:
8 bits is an even power of 2, which makes it somewhat easier to design computer hardware with 8-bit bytes than with 9-bit bytes.
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Capacitors between multiple positive power rails in cpu power system
Many years ago, when I was working in samsung aftermarket supply chain with set top box repairs I had access to basic schematic of one of stb. In a power supply part for powering RAM there were a few ...
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Storing Program Instructions on FPGA
I am creating a basic RISC processing core on a FPGA development board (Nexys A7-100t).
I created a RAM block that will be used to store the instructions that my basic processor will execute to run a ...
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Memory Selection and NOT Gate in Embedded System
I'm currently studying Embedded Systems and in the topic of drawing a schematic for the address of a microprocessor (16bits address x 8 bit data (64Kbytes)) with 1 ROM 32Kx8 and 1 RAM 32Kx8, I simply ...
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DRAM, multi-channel, memory access
I'm looking for a way, under any configuration/OS(windows or linux)/programming language you suggest to simultaneously access memory addresses, that are under different channels, meaning the access ...
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Internal and external storage for a FPGA
I want to store at least 2Mbits on a FPGA. What is the normal practice for storing data on a FPGA internally?
Also, if I wanted to store 4GBytes externally, how would I go about doing this? Is it ...
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My understanding of computer hardware architecture
Forgive my above crude diagram.
Assume the above is the hardware architecture for a computer/mobile phone or any device which hold a microprocessor.
Please let me know whether my understanding is ...
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DDR3, Data Mask Pin-swap within a given byte lane
Is it possible to swap "Data Mask" or "Data Strobe" pins with DQx pins within the same byte lane.
In Freescale's "Hardware and Layout Design Considerations for DDR3 SDRAM ...
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Using VHDL integer_vector for a block ram type, how to restrict the integer range?
Trying to simply infer block rams in a design with varying depths and widths. I'd like to have one ram definition since it is going to use a vendor specific attribute and it seems like a good idea to ...
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understanding data semantics and diagram
According to http://www.auto-diagnostics.info/pdf/ford_eectch98.pdf page 10, "The 8361 ROM chip contains 8k bytes of program memory plus 128 bytes of additional RAM."
I found two diagrams ...
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How to Simulate VHDL when Using a Vendor's Tool Generated Instantiation Code?
I'm working with a Gowin FPGA and they recommend instantiating block RAM. That sounds great, but how do I simulate that? I would expect there to be a library with the model for the instantiation ...
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How to Use Addresses with Single Port RAM on FPGA
I am trying to understand this example of single port memory where an 8 by 64 bit RAM is created. If I am understanding correctly, the section of code that says "reg [7:0] ram [63:0]" means ...
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Calculating RAM memory capacity from schematic symbol
Is it possible to calculate the memory capacity of a RAM given its schematic symbol?
I made a first guess from an example but seems to be incorrect:
If the address bus is 15-bit width, there are a ...
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4 address lines for 1 bit input
I am currently trying to design a 16 nibble RAM on logisim, whereby it takes 4 data input lines.
However, what I am having the most trouble with is converting the 4 address lines into a single input, ...
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How is 1 bit transfered from RAM to a 1 bit register?
I've been reading on computer RAM and CPUs. I came to the conclusion that most RAM today use arrays of DRAM while CPU registers and caches use SRAM. 1 bit DRAM is a circuit with one capacitor and 1 ...
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Vivado VHDL BRAM write-read Simulation not reading properly
So im trying to simulate a simple write and read memory program in Vivado design suite.
Before implementing a clock in the sensitivity list on the process to write and read, the reading part used to ...
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VHDL Type memory question
My question is very simple i think, but i would be really gratefull if anyone can help me with this.
When i want to write in the fpga memory using the classic following line code:
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Is this the correct w recognize Opcodes for a DIY 8bit Processor
simulate this circuit – Schematic created using CircuitLab
i am starting with designing a 8bit computer and probably turn it into reality , so lets say i start with a 8bit 32kb memory and i want ...
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Can I use a 16bit memory with an 8 bit processor?
The address bus is typically a double octet wide (i.e. 16-bit), due to practical and economical considerations. This implies a direct address space of only 64 kB on most 8-bit processors
This quote ...
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How can I access more than 15 addresses of data from my 8 bit incomplete computer?
Last year I started researching upon how computers work, so I started making one, at least on paper last month, but I ran into a serious problem that isn't getting a satisfying answer from any article ...
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Why do DDR RAMs have both xDQ and xDM signals?
DDR2 RAMs have these control signals
RAS, CAS - address strobes
UDQ, LDQ - byte strobes
WE - write enable
UDM, LDM - write mask
Why do we need UDM and LDM? Can't you write a byte by asserting WE and ...
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Can you desolder and upgrade RAM in Pi boards?
Friendly Electronics has come out with a great small compact but very powerful board. It is called the Nano Pi fire 3. It has 8 cores which is great for programers like myself who want to utilize the ...
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How can I improve my testbench for testing a 1024x4 RAM memory in Verilog
This is a question following on from my previous one "How can I improve my testbench for testing a 1024x4 RAM memory in Verilog".
Basically, I have modified the previous solution in an ...
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How to decide when to use flop or RAM based fifo?
Trying to figure out what are the tradeoff like power, size when deciding between using a flop or RAM based fifo ? Any known publications ?
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Pseudo dual port RAM in verilog
How does one design a pseudo dual port RAM using a single port RAM in Verilog ? What are the design considerations? Are there frequency limitations ?
Clarification on 'pseudo dual port - single port ...
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How Does One Do Block RAM Inference on Altera Cyclone 10 LP FPGA Boards in Verilog [closed]
I have tried to google for this a lot but I can't seem to find anything.
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What can I do to improve my test bench for testing a 64x4 RAM memory in Verilog
What can I do to improve my test bench for testing a 64x4 RAM memory in Verilog to obtain the desired result?
I have written a test bench to test a simple 64x4 RAM memory in Verilog and it seems to &...
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Write ADC data to memory and back to DAC (without MCU)
Is there a way that is not too complex way to implement ADC -> SRAM -> DAC data transmission without the usage of the microcontroller?
The application is to implement the audio loop of some sort,...
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Why the RAM 23lc1024 is not responding or give error?
I interfaced the 23LC1024 RAM module to atmega328. I have coded using embedded c on avr studio. The program flows like one byte is written to the address 0x000000 and Read data from the address ...
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How to compare VitalDelayType01 to each other?
I have a behavioral model of an external RAM part. This vendor seems to have used some external library functions or procedure they made.
It has these functions like:
MinDelay (a, b) return c; --where ...
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12-bit homebrew computer?
I'm planning my first homebrew computer. I'd like to perform calculations with 8-bit numbers. My op codes will be 4-bit numbers.
I'll be building this on breadboards so I'd like to keep things as ...
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Feasible to capture data to/from a 1970s RAM chip?
I have a 1978 Bally Playboy pinball machine. The processor is a 1Mhz 8-bit microprocessor Motorola 6800. I would like to build a way to extract/watch game state from outside of the machine. The best ...
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Interfacing a RAM chip from a commercial computer with an ARM cpu such as Stm32
I need to interface some sort of RAM with an ARM processor for my embedded project. Around 128 MB to be exact. I found a computer RAM which claims to be DDR and 1 GB. As I only need 128 MB of RAM for ...
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How to calculate RAM size from chip markings and number of chips
I have a RAM with 8 TMS44400DJ chips on it. It says the word length is 1048576, so would it mean times 8 I have 8MB RAM on this module?
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Why DDR4 Specs recommend that Address, Control and Clock buses be referenced to VDD?
Micron's Technical Note TN-40-40: DDR4 Point-to-Point Design Guide, page 19, says (emphasis mine):
Timing Budget
Suggested practice is to look at the design from a timing budget
standpoint to provide ...
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How to output a determined number of characters in VHDL regardless of the input
I´m working on a code VHDL with a RAM memory which purpose is show me the output data in the TeraTerm software. I enter the data via the Arduino COM window (The Arduino MEGA 2560 is connected to an ...
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lowering voltage of high frequency signal
One of the parts I have is RAM (1.5V logic level).
The hardware communicating with it, is at a 1.8V logic level. The RAM signals are sent quickly - around 350-450Mhz.
So I am pretty sure I can't ...
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Embedded system - copying data from flash to RAM
This question uses some Xilinx-specific terminology.
I'm currently working with a Zynq Ultrascale+ MPSoC (CPU + FPGA in same package). I'm using a QSPI flash chip to hold the CPU configuration code, ...
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Is a metallic conductor within an electrostatic field necessarily subject to discharge?
Basically what I'm trying to determine is if the new RAM chips I received in the mail were potentially damaged from static electricity.
Late last night, tired and foggy, I built up a considerable ...
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What is the probability of a bit error occurring in modern computers?
What is the probability of a bit error occuring when reading/writing from/to the latest memory technologies (ssd, hdd, ram) in modern computers? If the same terminology is used in this context as in ...
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Why does dynamic ram need to be 'refreshed'?
I read this question, but it didn't really answer my question. I also want to preface this question by saying that I'm asking this from the perspective of being a computer science student that took ...
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Access elements randomly in RAM based FIFO VHDL FPGA
The thing is: new data is being generated every "time step" that can be few clock cycles. So I want to store the data generated for few time steps in a "buffer". The data must be stored like in a ...
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Why are bytes 8 bits? (and more)
An 8 bit value can range anything from 0 to 255 in decimal, or 00 to FF in hexadecimal. But why did they choose 8 bits for the byte, out of all of the powers of 2 they could have chosen? Even still, a ...
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How can a 4-bit CPU have 40 instructions?
Currently, I am using Logisim (yes, still Logisim) to build a 4-bit variant of the 8-bit SAP-1 microcomputer. However, I ran into a problem with the instruction register. Let me explain.
The SAP-1 has ...
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Dynamically pushing instructions to SRAM IC
Sorry if this isn't the right place to ask this. Coming from a programming background, and I'm not 100% sure how to read some of these data sheets.
I'm looking at using IC 628512LP-70 CMOS SRAM" (or ...
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FPGA and CPU design: Moving from ideal memory to real RAM blocks
I implemented the single-cycle MIPS design from "Computer Organisation and Design" in Verilog, shown below:
I used my own "ideal" data memory implementation, which asynchronously presents the read ...
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