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32 Bit FileRegister with ALU

Creating a SystemVerilog module called fileRegister which has three 4-bit inputs, and one bit clock, and one bit writeEnable. It should be like figure1 below. I'm ...
Jekolaw's user avatar
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1 vote
1 answer
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What are W1C and R1C register access types?

I drew a diagram for the W1C and R1C register access types for register file/bank. First I am trying to make a register file for different registers. I am using D-FF to store 1-bit data, but I'm ...
P Ksagar's user avatar
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Help with Register File Implementation on Logisim

I'm currently working on an assignment that involves implementing a register file with 2 read ports and 1 write port on Logisim. I've made some progress but I'm struggling with a few questions and ...
mrAnonymous's user avatar
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1 answer
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classic RISC pipeline: Why does memory access stage comes before register file write back?

Here are two confusions: Instruction fetch step provides info on what's the op and in which register the data lies, but how does that data comes into those registers? It seems that once the execution ...
lousycoder's user avatar
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What is the cost of increasing the number of register names?

Increasing the number of registers in a CPU, has the upside that more values can be kept in registers instead of having to spill to stack. It has some downsides, one of which is that more instruction ...
rwallace's user avatar
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How to instantiate module with variables

I declared alu_result as a reg because I need it to be a variable data type for my case statement. But when i do this, I cannot pass it my ...
TheBigBoyOverThere's user avatar
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3 answers
876 views

How do I make a 74LS170 or 74LS670 register file reliably clock in data on the rising edge?

I am getting a little desperate here. I thought I could replace a single 4-bit D-flip-flop register 74LS173 with the 4 x 4-bit register file 74LS170 or 74LS670. But the problem is that it is a level ...
Gunther Schadow's user avatar
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3 answers
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Positive edge detection triggers on negative edge too

I have 74LS170s and 74LS670 register files which have the trouble that they are not edge triggered but like SRAM accept data for the entire duration of the write gate being low. So, I have the ...
Gunther Schadow's user avatar
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Turn a positive clock edge into a negative pulse to make a 74LS170/670 register file synchronous

This is a follow-up o Why did they make the 74x170 (670) register file asychronous, no CLK input?. I want to use that "register file" for my project, but I need to make it behave properly as a ...
Gunther Schadow's user avatar