Questions tagged [rgmii]
Reduced Gigabit Media Independent Interface (RGMII) is a parallel interface from MAC to external PHY that uses DDR I/O to reduce the pin count.
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Marvell Ethernet PHY unstable link status
We are currently testing the copper link from Processor RGMII interface through Marvell 88E1510 Ethernet PHY. The PHY registers shows Cu link as unstable with the link going up and down randomly. Here ...
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2answers
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Impedance/Termination of Marvell PHY
I'm trying to understand the proper way to design a PCB to interface a Xilinx 7-series FPGA with a Marvell 88E1512 Ethernet PHY, without simply copying the design from an existing schematic.
The ...
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1answer
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Ethernet Phy Rx developed in a FPGA to send data to an ethernet Mac
I'm trying to send data from a FPGA to the Ethernet Mac port of a SoC which has the stmmac Synopsys IP.
I'm using the MII protocol at 25MHz for 100Mb/s (4-bit per clock cycle).
I'm sending the ...
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Can I use an Ethernet switch IC without connecting to the mcu?
I'd like to add an unmanaged Ethernet switch IC to a board I am designing, but I have no free RGMII/SGMII/PCIe connection available on my MCU. The goal of this IC is just to save space/hassle (in the ...
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2answers
82 views
IO standard for RGMII interface of ethernet
I'm learning about the RGMII interface of ethernet. Can anybody please tell me What IO standard does the TX and RX line of RGMII interface support? Please help. I'm just a beginner
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1answer
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How to connect CPU with RGMII pins to an LTE module that takes only SGMII signals?
The Hi3519 Hisilicon CPU has RGMII pins. We are trying to connect it to the EC21 LTE Module from Quectel which contains SGMII pins. Would using two Realtek RTL8201F-VB-GG PHY chips with magnetics ...
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1answer
172 views
NIC connection with PHY issue
We have an NIC (computer A) connected to Marvell 88e1116R via Ethernet cable, the Marvell chip is then connected to Xilinx FPGA, the FPGA connected to ADSL Analog front end (AFE), the AFE is connected ...
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1answer
2k views
Does SGMII use MDIO?
I was reading the SGMII specification and the documentation of a Gigabit MII to SGMII converter (see MAX24287). I do not see a MDIO to control the registers of the PHY (Basic Mode Status Register, ...
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1answer
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RGMII - Origin of RGMII and does a standard exist?
I'm implementing an Ethernet system on a Xilinx FPGA, and I've been reading IEEE 802.3-2015, but nowhere have I found mention of RGMII which is the interface to the PHY. After extensive searching, I ...
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1answer
1k views
GMII/RGMII TX_ER signal: guaranteed functionality?
I have a question seeking to clarify EXACTLY what happens during a GMII exchange between MAC and PHY. Specifically, regarding the TX_ER signal.
IEEE 802.3 Section 3:
TX_ER is driven by the ...
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2answers
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RGMII and RMII backwards compatibility
According to Wikipedia:
GMII [...] is backwards compatible with the media-independent interface (MII)
But is RGMII backwards compatible with RMII?
I'm asking this because I'm making a schematic ...
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Can I generate a 90° Clock signal with Xilinx's ODELAY for RGMII?
Some time ago I implemented a GMII interface for my Gigabit Ethernet core. Now I'm trying to do the same with the RGMII protocol. The reference implementation from Xilinx uses IDELAY[|E1|E2] ...
