Questions tagged [rgmii]

Reduced Gigabit Media Independent Interface (RGMII) is a parallel interface from MAC to external PHY that uses DDR I/O to reduce the pin count.

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How to connect CPU with RGMII pins to an LTE module that takes only SGMII signals?

The Hi3519 Hisilicon CPU has RGMII pins. We are trying to connect it to the EC21 LTE Module from Quectel which contains SGMII pins. Would using two Realtek RTL8201F-VB-GG PHY chips with magnetics ...
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NIC connection with PHY issue

We have an NIC (computer A) connected to Marvell 88e1116R via Ethernet cable, the Marvell chip is then connected to Xilinx FPGA, the FPGA connected to ADSL Analog front end (AFE), the AFE is connected ...
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Does SGMII use MDIO?

I was reading the SGMII specification and the documentation of a Gigabit MII to SGMII converter (see MAX24287). I do not see a MDIO to control the registers of the PHY (Basic Mode Status Register, ...
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RGMII - Origin of RGMII and does a standard exist?

I'm implementing an Ethernet system on a Xilinx FPGA, and I've been reading IEEE 802.3-2015, but nowhere have I found mention of RGMII which is the interface to the PHY. After extensive searching, I ...
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GMII/RGMII TX_ER signal: guaranteed functionality?

I have a question seeking to clarify EXACTLY what happens during a GMII exchange between MAC and PHY. Specifically, regarding the TX_ER signal. IEEE 802.3 Section 3: TX_ER is driven by the ...
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RGMII and RMII backwards compatibility

According to Wikipedia: GMII [...] is backwards compatible with the media-independent interface (MII) But is RGMII backwards compatible with RMII? I'm asking this because I'm making a schematic ...
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Can I generate a 90° Clock signal with Xilinx's ODELAY for RGMII?

Some time ago I implemented a GMII interface for my Gigabit Ethernet core. Now I'm trying to do the same with the RGMII protocol. The reference implementation from Xilinx uses IDELAY[|E1|E2] ...