Questions tagged [rgmii]
Reduced Gigabit Media Independent Interface (RGMII) is a parallel interface from MAC to external PHY that uses DDR I/O to reduce the pin count.
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How to define PHY mode and MAC mode between back to back switches
I'm planning to use this Switch IC connected to another another switch ic which is the same part number. When connecting these devices in back to back mode with RGMII interface between then, I need to ...
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Ethernet MAC TO MAC Communication between S32K148_SAMA5D27 Schematic Review
I am doing RMII MAC TO MAC Communication between S32K and SAMA5D27.Please find the attached
schematic file. Could you please review it.
May I know the level shifters directions are correct or not. My ...
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RGMII use RX CLK as TX CLK
I'm looking into the RGMII interface spec and something is unclear to me. The PHY gives my FPGA a 125 MHz clock in 1 GBit mode. I also have to send out a TX clock at 125 MHz. Is it legal to use the RX ...
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Connecting two ethernet ports back to back
Suppose, I am connecting the copper ports of 2 PHYs in back-to-back mode in the same board (using capacitive coupling technique), should the TX pair of one PHY be connected to the Rx pair of the other ...
user220456
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How to use Gigabit Ethernet with MCU?
I am new at ethernet and it comes complex. Trying to use STM32's RMII interface with switch. I just want to see at IT's switch gigabit port. I don't want to transfer data gigabit, it doesn't matter. ...
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Ethernet with STM32
I designed an ethernet microchip with reference (LAN8742A-LAN8742) with MCU STM32F767ZGT6, so I followed some document routing ethernet in PCB I respect all rules. when I put the ethernet there is a ...
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Will RGMII work with a small constant delay in the range of 10~20ns on all signals?
Related to this question.
An RGMII interface transmitting data at 1Gbps runs with a clock rate of 125MHz, and data is clocked out on both edges. Given that, it would appear that any skew between ...
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Smallest lowest cost way to isolate RGMII signals between devices on the same CCA?
I have a single Gigabit Ethernet line coming out of a circuit card. Access to the line will be shared by two CPUs. To facilitate shared access, the CCA will have an Ethernet switch IC.
The switch IC ...
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Can you interface 2 gigabit ethernet ports via one rgmii interface?
Can we use the KSZ9893RNXC from Microchip as the Ethernet PHY chip, and interface the 2 gigabit ports to Allwinner H6, which has only one RGMII interface. Also please note that we are aiming at using ...
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Impedance/Termination of Marvell PHY
I'm trying to understand the proper way to design a PCB to interface a Xilinx 7-series FPGA with a Marvell 88E1512 Ethernet PHY, without simply copying the design from an existing schematic.
The ...
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Ethernet Phy Rx developed in a FPGA to send data to an ethernet Mac
I'm trying to send data from a FPGA to the Ethernet Mac port of a SoC which has the stmmac Synopsys IP.
I'm using the MII protocol at 25MHz for 100Mb/s (4-bit per clock cycle).
I'm sending the ...
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Can I use an Ethernet switch IC without connecting to the mcu?
I'd like to add an unmanaged Ethernet switch IC to a board I am designing, but I have no free RGMII/SGMII/PCIe connection available on my MCU. The goal of this IC is just to save space/hassle (in the ...
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IO standard for RGMII interface of ethernet
I'm learning about the RGMII interface of ethernet. Can anybody please tell me What IO standard does the TX and RX line of RGMII interface support? Please help. I'm just a beginner
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How to connect CPU with RGMII pins to an LTE module that takes only SGMII signals?
The Hi3519 Hisilicon CPU has RGMII pins. We are trying to connect it to the EC21 LTE Module from Quectel which contains SGMII pins. Would using two Realtek RTL8201F-VB-GG PHY chips with magnetics ...
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NIC connection with PHY issue
We have an NIC (computer A) connected to Marvell 88e1116R via Ethernet cable, the Marvell chip is then connected to Xilinx FPGA, the FPGA connected to ADSL Analog front end (AFE), the AFE is connected ...
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Does SGMII use MDIO?
I was reading the SGMII specification and the documentation of a Gigabit MII to SGMII converter (see MAX24287). I do not see a MDIO to control the registers of the PHY (Basic Mode Status Register, ...
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RGMII - Origin of RGMII and does a standard exist?
I'm implementing an Ethernet system on a Xilinx FPGA, and I've been reading IEEE 802.3-2015, but nowhere have I found mention of RGMII which is the interface to the PHY. After extensive searching, I ...
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GMII/RGMII TX_ER signal: guaranteed functionality?
I have a question seeking to clarify EXACTLY what happens during a GMII exchange between MAC and PHY. Specifically, regarding the TX_ER signal.
IEEE 802.3 Section 3:
TX_ER is driven by the ...
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RGMII and RMII backwards compatibility
According to Wikipedia:
GMII [...] is backwards compatible with the media-independent interface (MII)
But is RGMII backwards compatible with RMII?
I'm asking this because I'm making a schematic ...
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Can I generate a 90° Clock signal with Xilinx's ODELAY for RGMII?
Some time ago I implemented a GMII interface for my Gigabit Ethernet core. Now I'm trying to do the same with the RGMII protocol. The reference implementation from Xilinx uses IDELAY[|E1|E2] ...
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