Questions tagged [ripple-counter]

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70 views

4-Bit ripple down counter using negative edge-triggered J-K flip flops

Ok, so as the title says im wanting to build a 4-bit ripple down counter on logisim so that I can find what 15 in binary is along with what 9 in binary is to make a mod-10 ripple down counter. But how ...
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Mod-10 ripple down counter using negative edge-triggered J-K flip flops

I am currently a university student on my first year and one of our practicals in the coming weeks is to build counters on Logic Gate Boards. Apologies if I do say something wrong, as we haven't had ...
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25 views

Mod - 7 Asynchronous/Ripple Down Counter Using J - K negative edge triggered Flip-Flop

I was trying to build the mod-7 asynchronous down counter from negative edge triggered JK flip flops. I am stuck as to how to start with 110 after 000 in the sequence. A circuit diagram related to ...
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51 views

Desiging mod counter

I came across following question The 3 bit ripple counter is to be designed as MOD 4 counter. What should be the architecture of the ‘Logic gate’? A. a 3 bit input AND gate B. a 2 input AND ...
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1answer
82 views

A 4bit counter that goes up and down

I am kinda new to the website, I just came across it after looking for answers for such a long time. I have an assignment that asks to add an input bit to your circuit from the circuit I created that ...
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1answer
500 views

Why ripple counter increments on each 8th pulse

I have connected the ripple counter CD4020 to an Atmega328, which sends a 50ms (low logic level) pulse to the CD4020's input each second and monitors all of its 12 outputs. However instead of ...
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1answer
76 views

Some questions regarding ripple counter and 74HCT

I'm very new to the subject of counters and tried to simulate a four bit ripple counter using a D flip-flop IC 74HCT in LTspice. If the above topology is correct I have some questions regarding this ...
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1answer
148 views

Resettable counter using JK flip

I want to design a binary counter in Cadence that counts pulses in every consecutive 50 nano seconds but i want it to be reset at the end of each 50 ns and shortly - so that it doesn't miss any pulse -...
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38 views

Is this a new type of ripple counter?

Ripple counters have output bits not change states in synchronism. On the other hand, synchronous counters have their bits connected to the same CLK pulse. However, I ran into circuits, which I ...
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1answer
546 views

74190 counter problem

So, I got my 74190 counter shows number like this 9-8-7-6-5-4-3-2-1-0-5-4-3-2-1-0-5-4-3-2-1-0-5-4-3-2-1-0 and so on. My questions: What can I do to change the output count down into 5-4-3-2-1-0-5-4-...
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1answer
67 views

4060 counter hardware question

When i run this circuit on test board i found that when Q3 led on and then turn power off the circuit and turn it on again the Q3 led remains on and it seems the counter contenue counting .what does ...
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1answer
1k views

Active high-active low for preset

In a FF when clear is 0, output is also 0.So what should it be considered as ? Active low or high clear? If it active low doesn't it mean that output should be 1 ?
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3answers
2k views

Propagation delay in asynchronous counter

Are the ripple counters useful in real life? I know, for example, if we set an up counter with 3 FFs, CBA. Followings are the block and the waveform diagram: After the count 001, it will appear 000 (...
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1answer
140 views

Issues with the initial state of a 7447N driver to BCD in a MOD 56 ripple counter

I'm currently doing an assignment for school where I have to construct a MOD-56 BCD ripple counter using JK Flip Flops. This requires 2 BCD displays and 7447N drivers to interpret the bits from the ...
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82 views

Small doubt in asynchronous counter

I was trying to understand the ripple effect in asynchronous counter and I came across this figure:- In all the problems solved in my book, they consider the minimum clock period required for proper ...
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0answers
71 views

Signal decimator/down-sample with lowest propagation delay

I would like to frequency-divide a 10 MHz digital signal by a factor of 8 or 16, with the lowest possible propagation delay. I need a propagation delay that is at most 5-10 ns. The best solution I ...
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1answer
376 views

Propagation delay in asynchronous circuit

Consider the circuit shown below where delay of each flip flop is 10ns and delay of each AND gate is 5ns each. What is the total propagation delay ? My Attempt:- 1) Consider that initial state i.e ...
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2answers
1k views

How to convert this into a down counter?

I have been learning counters and am able to design an asynchronous UP counter with JK flip flops in Multisim, however I am unable to convert it to an asynchronous DOWN counter. My UP counter counts ...
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1answer
1k views

Ripple counter, reset problem (J-K flip flop counter)

I am trying to simulate a decade counter using a ripple counter 4 bits and a NAND gate to reset the 4 J-K flip-flops when it reaches 10 (1010). The thing is it does not reset but goes to 4 (0100) due ...
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2answers
728 views

Having an issue connecting two 4-bit Synchronous Up Down counters

That's a Traffic Light circuit I designed on Multisim. I used 2 74LS191 Counters, 2 74LS47 Decoders, 2 Seven Segment Displays, a 555 timer and a J-K flip-flop as you see. It should count from 29 down ...
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1answer
2k views

Why use JK Flip Flops in syncronous/asyncronous binary counters rather than D flip flops?

Everywhere I encounter either asyncronous (ripple counter) binary counters or syncronous ones, the application uses JK flip flops with the J and K inputs tied together, such as described here: From ...
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2answers
2k views

Can you make an asynchronous counter count in Gray Code?

I will firstly explain my situation and then ask a few question in the clearest way possible. I am a total beginner and thanks for coping with me. The Task: I was given the task of designing a ...
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1answer
1k views

Sequential counter for repeating counting sequence

I'm aware of designing synchronous counter design for a counting sequence where I write the state table with present and next state and then followed by flip flop inputs (filled using the excitation ...
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1answer
200 views

Do all non self starting counters have lock out problem? [closed]

I understand that a self starting counter is one which could start counting from any state but eventually reaches the required count sequence, meaning if a non self starting counter starts from an ...
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1answer
717 views

How many states are possible for this ripple counter?

How many states are possible for this ripple counter ? MY try : If for an instance, I remove the NAND gate, then it works like a down counter. Assume Q2Q1Q0 = 000. Here, Preset is active high. If ...
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2answers
3k views

Does anyone know how to build asynchronous mod 10 down counter using t flip flops?

I know how to build asynchronous down counter , but it starts with F and ends at 0 and a need it to start at 9 and count to 0.The T flip flop has a set and reset and i need to use them so that it can ...
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3answers
428 views

4024 cmos counter not resetting

In my project, this section is faulty. I'm doing a bit-banging operation with shift registers and I'm trying to make shift register data reset after 15 bits are shifted out from the micro controller. ...
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1answer
203 views

Synchronous vs Asynchronous Counters for Periodic Phenomena

Suppose that we have a synchronous 4bit counter A that counts from 0 to 9 synchronized with a clock signal CP. We put an AND gate such that the signal Y = Q3*Q0 is 1 when we count a decade. The signal ...
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1answer
2k views

Minimum No. of JK FlipFlops needed to design a user defined counter

We want to design a synchronous counter that counts the sequence 0−1−0−2−0−3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is : My doubt: We can design ...
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2answers
5k views

what is meant by Divide by N and Modulo(N) in counters?

I am trying to understand counters. Can anyone of you clarify me about terms (Divide by N) and Modulo(N) used in counter? What exactly it means?
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1answer
101 views

How to terminate binary counting using a logic gate

So I am designing a 3-bit asynchronous binary counter which counts up to 11 then repeats using D flip-flops. That much I have done, however I am stuck when it comes to decoding the outputs to stop the ...
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1answer
635 views

Asynchronous Cascaded Counters Problem!

What is the Frequency and Duty cycle and of the waveform at Z (say if input clock frequency is 1.5Khz) My Understanding: Two negative edge triggered MOD 12 counters cascaded and reset when the upper ...
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2answers
915 views

Resetting a counter when it reaches 6, without logic gates

I have a 3 bit ripple counter (using t flip flops) and I want the counter to reset to one when it reaches 7 i.e. the counter counts from 1 to 6. My idea was that I could hook the three outputs from ...
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1answer
141 views

Freq. measurement using pin change interrupt + 4024 counter?

I have an oscillator which I need to measure using an AVR MCU running on an 8MHz Xtal. The output from the oscillator is driving the clock input of a 4024 counter. The freq. range on Q6 (input signal ...
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1answer
2k views

Design up counter in VHDL using generate statement

I need to design an 8 bit up counter in VHDL using T flip flop and generate statement. I know how the counter works, but I am not able to design it in VHDL. The main problem is "using generate ...
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1answer
430 views

Count number of hours elapsed

It's been a long while since I played with circuits, I'd appreciate a sanity check of the following design; I'm trying to count the number of hours since the reset button was last pressed. Ideally it'...
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1answer
87 views

How can I trigger other circuits based on specific values of a 12 bit ripple counter?

I've built quite a few circuits but I've never really designed anything from a "schematics first" approach. Mostly just tinkered with designed and code until I got it right. Now, I want to build a ...
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4answers
11k views

In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth?

In a binary counter design using 4 J-K flip-flops, that counts from 0 to 9, the flip flops are reset when the output from the 2nd flip flop NAND the 4th flipflop equals to 0. Since binary 9 is 1001, ...
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2answers
252 views

Asynchronous counter for DAC input

Is it OK to use an asynchronous counter for DAC input? If I understand it correctly, the output pins on the counter do not change simultaneously with the clock? Does the latency for every higher bit ...
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2answers
1k views

How accurate is a ripple counter (using D flip-flop) in measuring the frequency of a signal?

I have two oscillating signals S1 and S2 whose periods are always different by a very tiny amount (~10-50ps). Can I use a D-flip-flop ripple-counter to measure S1 and S2 individually, and then ...
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2answers
2k views

Issues implementing an up/down counter

I am trying to understand how to implement up/down binary ripple counter. Basically, I have a bunch of D-flipflops, and connect clk of next flipflop to ether Q or Q'. So, if I want to change ...
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3answers
349 views

Binary Counter not synchronous

Can someone help me understand how to do this counter ripple? and what to be use as counter (74ls76 or 74ls193). My problem is to make counter like this [0, 2, 3, 4, 6, 7, 9, 15, 14, 13, 12, 11, 10, 8,...
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1answer
7k views

Ripple counters versus synchronous--pros, cons, and power consumption

Substantial edit--note that David Kessner's answer was written in response to the original posting; view the edit history to see what he was responding to From what I've read of digital design, there ...