Questions tagged [ripple-counter]

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What is wrong with my ripple BCD down counter circuit?

I want to implement a BCD ripple down-counter in Proteus. The following is my circuit. The logic is simple. When the "original" 4-bit binary ripple counter reaches 1111 (15), the 2nd and 3rd ...
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3 answers
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Why does a 4-bit asynchronous counter need exactly 4 flip-flops?

We can get the same result (counting from 0000 to 1111) by removing the last flip-flop (Q3 output) and taking clock line as one of the inputs (i.e Q0 will be from clk itself and rest 3 outputs from 3 ...
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Why is the 14-stage SN74HC4020/CD74HC4020 binary counter missing 2 output pins, leaving 2 bits inaccessible?

I purchased a few SN74HC4020 ICs, which is a 14-stage ripple-carry binary counter. The SN74HC4020 datasheet shows output pins for bit 1 (pin QA) and bits 4-14 (pins QD-QN). So in other words the ...
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3 Bit Counter w/ 7 Segment Display Starts at 111 instead of 000

The goal for this task is to have a 7 segment display output my last name the first two initials of my first name. The output should be FURMANHE with F being the 000 state and 111 being the E state. ...
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What is wrong with my modulo 13 asynchronous up counter?

I'm trying to design a modulo 13 asynchronous up counter with master slave JK flip flops. I connected the NAND gate to clear it when it reaches number 13, as shown in the figure. However, it continues ...
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Trying to understand clock circuit (wall clock, not signaling clock)

First of all, electronics is a new hobby for me. I don't have any formal training, so please be patient with me. Probably like many people, I picked up the interest after playing with Arduinos. I ...
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3 answers
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JK Flip-Flop Counter: How to reset a counter?

I currently have a 3-bit asyncronous counter (built using J-K flip flops) that continuously counts up. However, I am struggling to figure out how to reset the counter to 0 when an input (Reset) is ...
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How exactly does activating CLEAR cause an asynchronous modulus 12 counter to reset?

I'm confused about how Clear manages to reset the counter. The trigger is falling edge. Starting from where the counter is in the image (I'll refer to each JK flip-flop as F1 etc.): At first, we have ...
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Problems with a CD4060BE ripple counter not counting

I have been trying to trace the fault in the circuit in the image below for the last 3 hours and I have exhausted the possibilities. The problem is that the CD4060BE ripple counter is not counting. ...
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2 answers
637 views

What would be the simplest BJT based *linear* ramp generator?

Let's say I have a 74LS161 based counter, and I want an analog ramp generator which will linearly increase until the ripple-carry-output goes back down (so that the ramp goes up the entire time the ...
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Differences between ripple counter (e.g. 74LS161) and CMOS 4040

I have been using the 74LS161 for some tinkering, and then switched to the CD4040 because it had 3 times as many counter stages in the same package size, and I don't need preset for my purpose. Early ...
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3 answers
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Is there a TTL or CMOS shift register chip which has an output pin telling you when it has shifted out all (8) bits?

Quick question, I'm going through 74x and CD4x chips to see if there is a parallel load serial out (left) shift register which would have the convenience of telling you when it is done shifting ...
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How can I determine the max frequency of the clock signal for a 3 bit ripple counter

I can't figure out how to determine the max frequency at which a ripple counter functions properly.
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2 votes
1 answer
170 views

Why do we reset/clear at 1010 (10) when designing a BCD Ripple Counter

Shouldn't we reset at 9, I believe that a decade counter goes as follows '0->1->2->3...->8->9->0" or at least that's how its done for synchronous BCD counters.
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Clearing 4-bit asynchronus counter using T flip-flops doesn't work

I am trying to make a BCD ripple counter that count from 0 to 9 , and I have watched a tutorial on YouTube , I implemented BCD counter as the instructor explained and after the counter reaches the ...
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Poor low frequency response of CD4060 IC

I have a question that involves a CD4060 ripple counter. My project is to design a counting circuit that turns off a relay after two hours. This can be done simply using an Arduino, but no ...
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My counter for my cpu stack alternates between counting up and down

My Counter for my cpu stack is given the up signal at the same time it is given the clock pulse to advance. This happens on the pull from stack instruction so the counter goes back up the stack one ...
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Review of my LED spinner Schematic

After a few months of questions and modifications to my design. I have what I believe to be a LED Spinner that can change the speed of the spinning LED. Before I send this design off to get printed on ...
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2 answers
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4-Bit ripple down counter using negative edge-triggered J-K flip flops

Ok, so as the title says im wanting to build a 4-bit ripple down counter on logisim so that I can find what 15 in binary is along with what 9 in binary is to make a mod-10 ripple down counter. But how ...
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Desiging mod counter

I came across following question The 3 bit ripple counter is to be designed as MOD 4 counter. What should be the architecture of the ‘Logic gate’? A. a 3 bit input AND gate B. a 2 input AND ...
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A 4bit counter that goes up and down

I am kinda new to the website, I just came across it after looking for answers for such a long time. I have an assignment that asks to add an input bit to your circuit from the circuit I created that ...
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3 votes
1 answer
614 views

Why ripple counter increments on each 8th pulse

I have connected the ripple counter CD4020 to an Atmega328, which sends a 50ms (low logic level) pulse to the CD4020's input each second and monitors all of its 12 outputs. However instead of ...
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Some questions regarding ripple counter and 74HCT

I'm very new to the subject of counters and tried to simulate a four bit ripple counter using a D flip-flop IC 74HCT in LTspice. If the above topology is correct I have some questions regarding this ...
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Resettable counter using JK flip

I want to design a binary counter in Cadence that counts pulses in every consecutive 50 nano seconds but i want it to be reset at the end of each 50 ns and shortly - so that it doesn't miss any pulse -...
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Is this a new type of ripple counter?

Ripple counters have output bits not change states in synchronism. On the other hand, synchronous counters have their bits connected to the same CLK pulse. However, I ran into circuits, which I ...
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3 votes
1 answer
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74190 counter problem

So, I got my 74190 counter shows number like this 9-8-7-6-5-4-3-2-1-0-5-4-3-2-1-0-5-4-3-2-1-0-5-4-3-2-1-0 and so on. My questions: What can I do to change the output count down into 5-4-3-2-1-0-5-4-...
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1 vote
1 answer
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4060 counter hardware question

When i run this circuit on test board i found that when Q3 led on and then turn power off the circuit and turn it on again the Q3 led remains on and it seems the counter contenue counting .what does ...
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2 votes
1 answer
4k views

Active high-active low for preset

In a FF when clear is 0, output is also 0.So what should it be considered as ? Active low or high clear? If it active low doesn't it mean that output should be 1 ?
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2 votes
3 answers
4k views

Propagation delay in asynchronous counter

Are the ripple counters useful in real life? I know, for example, if we set an up counter with 3 FFs, CBA. Followings are the block and the waveform diagram: After the count 001, it will appear 000 (...
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1 answer
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Issues with the initial state of a 7447N driver to BCD in a MOD 56 ripple counter

I'm currently doing an assignment for school where I have to construct a MOD-56 BCD ripple counter using JK Flip Flops. This requires 2 BCD displays and 7447N drivers to interpret the bits from the ...
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Small doubt in asynchronous counter

I was trying to understand the ripple effect in asynchronous counter and I came across this figure:- In all the problems solved in my book, they consider the minimum clock period required for proper ...
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Signal decimator/down-sample with lowest propagation delay

I would like to frequency-divide a 10 MHz digital signal by a factor of 8 or 16, with the lowest possible propagation delay. I need a propagation delay that is at most 5-10 ns. The best solution I ...
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1 vote
1 answer
656 views

Propagation delay in asynchronous circuit

Consider the circuit shown below where delay of each flip flop is 10ns and delay of each AND gate is 5ns each. What is the total propagation delay ? My Attempt:- 1) Consider that initial state i.e ...
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How to convert this into a down counter?

I have been learning counters and am able to design an asynchronous UP counter with JK flip flops in Multisim, however I am unable to convert it to an asynchronous DOWN counter. My UP counter counts ...
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4 votes
2 answers
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Ripple counter, reset problem (J-K flip flop counter)

I am trying to simulate a decade counter using a ripple counter 4 bits and a NAND gate to reset the 4 J-K flip-flops when it reaches 10 (1010). The thing is it does not reset but goes to 4 (0100) due ...
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1 vote
2 answers
1k views

Having an issue connecting two 4-bit Synchronous Up Down counters

That's a Traffic Light circuit I designed on Multisim. I used 2 74LS191 Counters, 2 74LS47 Decoders, 2 Seven Segment Displays, a 555 timer and a J-K flip-flop as you see. It should count from 29 down ...
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2 votes
1 answer
3k views

Why use JK Flip Flops in syncronous/asyncronous binary counters rather than D flip flops?

Everywhere I encounter either asyncronous (ripple counter) binary counters or syncronous ones, the application uses JK flip flops with the J and K inputs tied together, such as described here: From ...
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2 answers
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Can you make a ripple counter count in Gray Code?

The Task: I was given the task of designing a decade counter using J-K Flip-Flops. What I immediately thought of was whether I should make it Synchronous or Ripple. And here is where I started getting ...
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Sequential counter for repeating counting sequence

I'm aware of designing synchronous counter design for a counting sequence where I write the state table with present and next state and then followed by flip flop inputs (filled using the excitation ...
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1 answer
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Do all non self starting counters have lock out problem? [closed]

I understand that a self starting counter is one which could start counting from any state but eventually reaches the required count sequence, meaning if a non self starting counter starts from an ...
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How many states are possible for this ripple counter?

How many states are possible for this ripple counter ? MY try : If for an instance, I remove the NAND gate, then it works like a down counter. Assume Q2Q1Q0 = 000. Here, Preset is active high. If ...
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2 answers
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Does anyone know how to build asynchronous mod 10 down counter using t flip flops?

I know how to build asynchronous down counter , but it starts with F and ends at 0 and a need it to start at 9 and count to 0.The T flip flop has a set and reset and i need to use them so that it can ...
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3 answers
666 views

4024 cmos counter not resetting

In my project, this section is faulty. I'm doing a bit-banging operation with shift registers and I'm trying to make shift register data reset after 15 bits are shifted out from the micro controller. ...
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Synchronous vs Asynchronous Counters for Periodic Phenomena

Suppose that we have a synchronous 4bit counter A that counts from 0 to 9 synchronized with a clock signal CP. We put an AND gate such that the signal Y = Q3*Q0 is 1 when we count a decade. The signal ...
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Minimum No. of JK FlipFlops needed to design a user defined counter

We want to design a synchronous counter that counts the sequence 0−1−0−2−0−3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is : My doubt: We can design ...
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2 votes
2 answers
9k views

what is meant by Divide by N and Modulo(N) in counters?

I am trying to understand counters. Can anyone of you clarify me about terms (Divide by N) and Modulo(N) used in counter? What exactly it means?
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1 answer
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How to terminate binary counting using a logic gate

So I am designing a 3-bit asynchronous binary counter which counts up to 11 then repeats using D flip-flops. That much I have done, however I am stuck when it comes to decoding the outputs to stop the ...
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1 answer
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Asynchronous Cascaded Counters Problem!

What is the Frequency and Duty cycle and of the waveform at Z (say if input clock frequency is 1.5Khz) My Understanding: Two negative edge triggered MOD 12 counters cascaded and reset when the upper ...
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Resetting a counter when it reaches 6, without logic gates

I have a 3 bit ripple counter (using t flip flops) and I want the counter to reset to one when it reaches 7 i.e. the counter counts from 1 to 6. My idea was that I could hook the three outputs from ...
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Freq. measurement using pin change interrupt + 4024 counter?

I have an oscillator which I need to measure using an AVR MCU running on an 8MHz Xtal. The output from the oscillator is driving the clock input of a 4024 counter. The freq. range on Q6 (input signal ...
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