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Questions tagged [risc]

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3 votes
1 answer
78 views

Why forward from MEM Stage in a sequence of add instructions that all contain the same register?

I was reading Computer Architecture and Organization 5th edition by Patterson and Hennessy. In Chapter 4, section 4.7 on Data Hazards, I read the following excerpt regarding forwarding from the MEM ...
Juan De Castro's user avatar
0 votes
1 answer
63 views

Storing Data and Instructions in Memory

I have implemented a RiscV32 single cycle processor using Verilog. Now I am trying to upload it to a FPGA (DE2 - 115 board) and check the functioning. But how do I store instructions and data in the ...
KS Hewa's user avatar
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1 vote
0 answers
109 views

Access register values from a PicoBlaze / MicroBlaze soft processor

We are conducting research on the reliability of registers deployed in embedded RISC processors where the focus is to ensure the reliability of their contents during transient faults. To do this we ...
David777's user avatar
  • 1,490
10 votes
7 answers
4k views

How do 16-bit addresses work inside 8-bit data bus processors?

As a project I am building a small 8-bit RISC processor out of discrete ICs. I have 17 instructions and cannot fit all information into instructions that are only one byte, so I have been thinking ...
David777's user avatar
  • 1,490
0 votes
1 answer
594 views

classic RISC pipeline: Why does memory access stage comes before register file write back?

Here are two confusions: Instruction fetch step provides info on what's the op and in which register the data lies, but how does that data comes into those registers? It seems that once the execution ...
lousycoder's user avatar
-1 votes
1 answer
929 views

Is it true that CISC architectures generally consume more power than RISC architectures?

I keep hearing CISC architectures consume more power than RISC architectures. This is said to be the reason for using RISC architectures for low-power applications. I am a skeptic, I think it could be ...
Shashank V M's user avatar
  • 2,331
0 votes
4 answers
409 views

Question about PID control loop timing

For my project I am creating a RISC processing architecture on an FPGA that can perform various basic instructions like adding, multiplying, subtracting, storing and fetching from memory etc. To prove ...
David777's user avatar
  • 1,490