Skip to main content

Questions tagged [rise-time]

Anything related to the rise time of a signal. The rise time is a parameter used to characterize abrupt transitions in a signal waveform. It is usually defined as the time needed by the signal to go from the 10% to the 90% of the level it attains at the end of the transition.

Filter by
Sorted by
Tagged with
0 votes
1 answer
49 views

How can I slow down the rise and fall time of a power MOSFET without adding a delay before the switching begins?

I'm building a simple 5 W HF CW transmitter, where the power to the final stages is controlled by a P-Channel Power MOSFET, whose gate is connected to a key. I added a simple capacitor between the ...
SRobertJames's user avatar
  • 1,135
1 vote
1 answer
43 views

Trying to figure out rise/fall times for different load conditions

I have a device that requires a certain rise/fall time for its input clock. It specs a .7ns rise and fall time with a 20% to 80% measurement at a Cin=6pf. I should note that the spec rise/fall time ...
Matty's user avatar
  • 217
0 votes
0 answers
75 views

Relation between rise and fall times and capacitance

So I'm currently reading the datasheet of the Motorola 68hc000 CPU and I want to be able to estimate how many devices I can plug to the bus directly before I encounter issues. So first things first, ...
Lugaid's user avatar
  • 101
0 votes
1 answer
42 views

Rise time to an input

A device trigger input requires 1 V pulse (can stand up to 6 V) and has 0.5 V threshold voltage. Now if I apply a 5 V pulse with 10 ns rise time, how can I estimate the time it takes a rising edge to ...
cm64's user avatar
  • 2,217
0 votes
2 answers
151 views

Measuring rise time with spectrum analyzer

Is it possible to measure the rise time (range 100ps-1ns) of a square wave signal with a spectrum analyzer (my oscilloscope has 100MHz bandwidth only)? My model is Rigol 3030N (9kHz-3GHz). My idea is ...
piotr's user avatar
  • 292
1 vote
0 answers
70 views

Understanding CLoad of a gate driver and the Cgate of an SiC MOSFET

I have selected an SiC MOSFET (UJ3C120040K3S) for my pulsed power application. My rise and fall time requirements are both 20 nS. My gate drive voltage will be 15 V. Based on the total gate charge ...
power_electronics_engineer's user avatar
0 votes
0 answers
45 views

Slow rise time in power supply

Does power supply slow rise time affect the UVLO start threshold voltage to turn on the IC (tps54316mpwprep)?
Surya Bharathi's user avatar
0 votes
0 answers
43 views

Power Supply rise time and configuration

Reset managment: from HW checklist and datasheet of USB2517 (page 48), is required a rise time for the 3V3 maximum of 400us. In our case it will be above 1ms. In this case, is it necessary to use a ...
user avatar
0 votes
0 answers
40 views

What happens if rise time specification is not met

I have a design where an NXP i.MX8M nano CPU has a KSZ8081RNAIA Ethernet Phy connected. During prototype testing, we found now that the supply voltage rise time provided by the CPU PMIC (NXP PCA9450B) ...
Freshman's user avatar
1 vote
0 answers
118 views

MOSFET Gate Resistor Problem in CHG, DSG pins

I am trying to design a BMS circuit by using BQ77915 . My charge and discharge mosfets are CSD18534KCS. They are only using for switching. The problem is BQ77915 datasheet says for gate resistors of ...
Nafi Can Ereli's user avatar
2 votes
4 answers
169 views

In an RC circuit, how do you explain the fast rise of voltage at a point close to source? (Weak pull up)

In the above figure, the voltage at the intermediate point rises quickly whereas the voltage after R2 is increases slowly ( as governed by the capacitor voltage.) I am not getting the intuitive ...
Dynamic_equilibrium's user avatar
3 votes
2 answers
294 views

Output with programmable rise time

I am tinkering with a device to generate pulses for a measurement setup. No need to buy it: Just wondering how one would implement it. Idea: Device generates a square-wave (Vpp and DC-offset) output ...
ElectronicsStudent's user avatar
3 votes
1 answer
181 views

Will the LVDS signal rise time improve after a counter IC?

I want to improve an LVDS signal's rise and fall time. With a Cyclone III FPGA, the LVDS signal has a 500 ps rise and fall time. If I apply these signals to a counter/divider IC like the SY100EP33VKG ...
Ahmet Atcı's user avatar
1 vote
0 answers
528 views

Are there any published values for GPIO slew rate or rise/fall times on ESP32?

Are there any published values for GPIO slew rate or rise/fall times on ESP32? I had a look at the datasheets and couldn't find any. I also couldn't find any measurements elsewhere. Have Espressif ...
Polynomial's user avatar
  • 10.8k
5 votes
1 answer
1k views

LTspice capacitor bug?

I know that capacitor slows the rise of voltage, but why is this not happening in the LTspice simulation? I got the input voltage at the output instantly.
NBK SOFT's user avatar
  • 107
2 votes
2 answers
407 views

How to speed up rise time on logic shifter?

I am trying to boost a 3.3V data signal to 5V, and I'm using a logic shifter to achieve that. Basically, I'm trying to drive WS2813 LEDs, and the data line needs something close to Vdd (5V) to read ...
MiataMan's user avatar
3 votes
3 answers
495 views

Meaning of time parameters in control theory

I know in control theory there are different time parameters, but I'm not sure why they are used and defined that way, with my main doubts being about rise time; definitions from here: Delay time (td)...
Mauro's user avatar
  • 184
-1 votes
2 answers
173 views

Does time constant or rise time concept apply in transformers as well? [closed]

I am new to electrical engineering. I have made a transformer where I kept one primary and two secondaries, there's an air gap between the primary leg and secondaries on toroidal core, you can watch ...
Yogie's user avatar
  • 129
1 vote
1 answer
456 views

Rise time and fall time of P-Channel FET

I have tied the gate to a 10 kilo-ohm pull-up resistor, as shown below. The FET I am using is the NTD2955T4G. The control signal is a control PCB. The output of the control PCB has a low side switch ...
JoeyB's user avatar
  • 2,389
-1 votes
1 answer
380 views

Ideal op-amp used as a digital buffer: rise time

Vo = Vin, so the rise time for both should be the same, but the capacitor takes some time charging. How can I find the charging time without any other information here?
sheetal's user avatar
1 vote
1 answer
382 views

Long rise time on UART RX line

I'm attempting to replace a controller unit (based on an STM32F1) with my own design (based on ESP32), but I'm stuck at the UART RX (seen from the controller side). The rise time of the signal is too ...
Cyborgium's user avatar
  • 159
5 votes
1 answer
265 views

Unexpected voltage spikes at output of PFET on falling edge

I have the circuit shown below: I want this circuit to switch between 2.5V and 3.6V at the drain of the PFET when I input a square wave into the gate of the PFET. I would expect that this circuit ...
Spydercrawler's user avatar
0 votes
0 answers
540 views

LVDS rise/fall time measurements - confused

In a document I found they mention that the rise/fall times are measured over 20-80% of the signal. They mention that the common mode is 1.2V with a output voltage swing of 350mV. This all makes sense,...
Matty's user avatar
  • 217
5 votes
4 answers
5k views

Root Sum Square

Can anyone in a simple way explain why this formula works. It is the Root Sum of Squares where you square your values then add together then take the square root. It seems to be used quite a lot in ...
Edba's user avatar
  • 167
0 votes
3 answers
492 views

Limiting PWM rise and fall time

We're generating a PWM signal at about 2000 Hz whose rise and fall times we need to limit to about 40 us, so it can pass through ordinary audio stages without distortion / ringing. The PWM signal is 0-...
Jim Mack's user avatar
  • 213
2 votes
1 answer
1k views

Rise time vs Slew Rate

I am using this device which is a LS1046. It list slew rate as 1V/ns to 4V/ns. It is measured over a region of .35XOVDD to .65XOVDD where OVDD is 1.8V So over the range of .63V to 1.17V which is .54V ...
Matty's user avatar
  • 217
2 votes
1 answer
219 views

What determines the rise time of a digital signal?

What are the factors that determine or affect the rise time of a digital signal?
khelms's user avatar
  • 127
0 votes
0 answers
322 views

Using a pull-up resistor and considering rise time for IC input

I have a FPGA based design in which the FPGA is interfaced with several ICs. The I/Os of the FPGA and most of the ICs are 3.3V, except from one where the I/Os are 1.8V. While there is no problem for ...
Mr.Y's user avatar
  • 153
1 vote
3 answers
1k views

Alternative to optocoupler in circuit design

I have designed a circuit that drives a +/- 20 to 30 peak to peak external signal received as an input to 16 different outputs. Another requirement is that I have to be able to switch the state of ...
jaun_dough's user avatar
1 vote
1 answer
120 views

Problem with the fall time of op-amp

I am designing a "simple" current source using an op-amplifier. My question is why is my fall time looking like that: What do I need to reduce the fall time? Here is the schematic:
Nejc Klanjscek's user avatar
0 votes
2 answers
457 views

What rise time should pulse have to have desired pulse width [closed]

I have a question regarding my high speed laser driver. I want to have 10ns width pulse. What rise/fall time I would need to have that I can say I still have 10ns pulse. Is there any percentage that ...
Nejc Klanjscek's user avatar
0 votes
2 answers
219 views

Minimizing pulled open collector output rise time on 74LS09

I have a circuit that calls for one open collector buffer for driving a shared line (/WAIT via Zilog Z80) and one typical AND gate. I've consolidated these into a single 74LS09 open collector quad 2-...
Bit Fracture's user avatar
0 votes
0 answers
71 views

Understanding photodiode modes and practical effect on noise vs response time tradeoffs for audio applications

I am an experimental musician with admittedly very little electronics experience (but I do have a mathematics degree) trying to find a decent photodiode for a project where I send audio signals via ...
robert's user avatar
  • 1
1 vote
2 answers
762 views

Very short rise and fall time with relay

My question is related to the question here. I need very fast rise and fall time (below 2ns) and pulse width of 50ns. Load is 50ohm and voltage is 250V. I have achieved the rise time with a mercury ...
Ismail's user avatar
  • 79
2 votes
1 answer
419 views

Clock line of SDIO bus has worse rise/fall time than rest of bus

I have an ATWILC3000 wifi module connected to a Raspberry Pi Compute Module 3+ over 4-bit SDIO. It's throwing a lot of bus errors at higher frequencies (currently running at 1 MHz for stability when ...
Joe Baker's user avatar
  • 1,723
1 vote
0 answers
306 views

Fast rise time reed relay

I am currently working on a project related that I asked before here. The purpose is to have 2ns rise time 30ns pulse width at 250V (with 50ohm load). Repetition is 30hz. I tried avalanche transistor ...
Ismail's user avatar
  • 79
2 votes
0 answers
285 views

Fast switch rise time techniques

This question is continuation of this question: High Frequency Square Wave Generator I am trying to drive a 400V supply and 50ohm load with an RF MOSFET which has a rise time of 3-4 ns and fall time ...
Ismail's user avatar
  • 79
0 votes
0 answers
171 views

How to calculate the rise time?

The figure shows a modification, from state A to state B, carried out on the cell at the output of circuit (X). In both cases, the voltage at point A is the same. The transistors M1 and M2 keep the ...
Yakeen's user avatar
  • 1
4 votes
0 answers
122 views

Can I calculate minimum rise time of a transmission line if I know the length and the loss tangent?

Overview: I am trying to work out if it's possible to transmit my 1.2Gbps MIPI data down a 600mm long flexible PCB strip. Assuming I have the impedance correct, will the signal still be degraded by ...
Rocketmagnet's user avatar
  • 27.5k
0 votes
2 answers
842 views

Timing specifications in a communication protocol

I am having this I2C EEPROM Chip from Onsemi - CAT24C In table 6, AC Characteristics of the datasheet, only the Minimum time is provided for the SCL clock low and high period. My questions : Not ...
user avatar
1 vote
1 answer
252 views

RC Time Constant simulator

I am trying to write a simple simulation of a Resistor / Capacitor network. I need to calculate the voltage across the capacitor as the input moves up and down. The problem is that there is two ...
Seti Net's user avatar
  • 123
1 vote
3 answers
513 views

CMOS inverter in series

I have the circuit below. Now my question is: why the rise time and fall time measured on Vout are the same as in a circuit using only one inverter gate? I know the propagation delay is the sum of ...
Shortcircuit's user avatar
1 vote
1 answer
563 views

Relationship between harmonic's amplitude and square wave's Tr and Pw

I started reading this TI guide on high speed layout guidelines and had some question on the theory of clock signals (pages 2 and 3). From the image below it's clear that the amplitude of the first ...
Geo's user avatar
  • 754
2 votes
1 answer
604 views

Pullup Rise Time On AVR External Interrupt

Background I am designing a simple lamp dimmer using the Atmel ATTiny441 microcontroller. To this end, I have designed a very basic zero-cross detector which feeds the external interrupt pin (INT0) ...
MysteryMoose's user avatar
1 vote
2 answers
2k views

Op-Amp Unity Gain Frequency

I'm tasked with finding the unity gain frequency of an op-amp using the datasheet specs provided to me (just a homework exercise, not a real op-amp). There is no direct spec given for "Unity Gain ...
Sittin Hawk's user avatar
0 votes
2 answers
388 views

What does fall and rise of clock mean?

Im new to electronics. In fact, I'm a computer scientist looking into embedded systems. I am going through Vol. 1 of Jonathan Valvano's book on embedded systems and got stuck when i read on Gated D ...
GoldenRetriever's user avatar
0 votes
1 answer
570 views

Finding Rise time and Fall time with Slew Rate Specification

I am using this QSPI Flash Memory IC I'm operating the QSPI clock at 48MHz. I am probing the Clock and Data signals in my scope. On Table 54 which is on Page 128, we have Rise time and fall time ...
user avatar
8 votes
1 answer
360 views

How do I calculate rise times for a push pull GPIO with load with hand calculations?

simulate this circuit – Schematic created using CircuitLab This is a simplified example of a push pull GPIO found in most microprocessors, with a load attached. Using the capacitance and ...
Voltage Spike's user avatar
  • 84.8k
3 votes
1 answer
726 views

How to correctly set logical high level on a PS/2 port?

I'm trying to make a keyboard emulator on ATmega16A. I'm currently implementing logical low as output-zero, and, since the host(?) is supposed to pull up the line, I send logical high state as input ...
Ruslan's user avatar
  • 864
0 votes
1 answer
96 views

FRR Measurement

When I try to measure the FRR (time delay in the rising edge of two pulses) between two channels of a GES-2074A GW-Instek digital oscilloscope, it varies depending on the time resolution. First, I ...
Shaz's user avatar
  • 101