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Questions tagged [rtl]

Register Transfer Level (RTL) is a logic design abstraction where digital circuits are described in terms of storage elements (registers) and the combinatorial logic operations that occur between them. RTL is one technique of describing a digital system using hardware description languages such as VHDL and Verilog.

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Creating entity/module containing IP from different vendors

In FPGA design often we need to instantiate vendor specific IP. This could be simple things like Block RAM and DSP. It could be more complex things like FPU IP. The 3rd party IP is directly ...
quantum231's user avatar
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How to Resolve LINT-1 Warning During Synthesis?

I am currently working on the synthesis stage of a hardware design project and encountering a specific warning from the LINT-1. I'm seeking assistance to resolve this issue. Tool: design compiler ...
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Synthesis with Verilog Parameter AUDIO_DW = 32 Results in LINT-1 Warning

I'm working on a Verilog project and encountering a warning during synthesis. When I set the parameter AUDIO_DW = 32, I get a ...
강영완's user avatar
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What is the need for implementing synthesizable linked list module in RTL?

Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs. Given that synthesized hardware has static memory size, what's the ...
HWDesigner's user avatar
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How do I implement a simple axistream by my self bus in VHDL?

I'm working on a design right now but I'm struggling with the axistream bus. I just want to be sure that I'm understanding well how it works. To do so I'm using the uvvm library to do a generator that ...
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Communication between Microblaze and RTL IP core

I have done an ethernet project (Echo) (TCP/IP) using vivado block design and the board used is Artix A7 and MICROBLAZE PROCESSOR WITH AXI_INTERCONNECT. I was able to use AXI_GPIO connected to an led, ...
Yosh Sinjab 's user avatar
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2 answers
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Why am I getting ZZZ output for my Verilog cordic code?

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Generate random numbers in a range with some others excluded

I need to generate random number between 0 and 191. This will fit in 8 bits. Then depending on certain constants being defined or not, certain slices of this range shall be included or excluded. e.g ...
quantum231's user avatar
2 votes
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How to find syntax error in RTL file quickly?

My company uses custom flow that is accessed via makefiles to compile the RTL and testbench code and run the simulation. The simulator cannot be accessed directly to open in GUI. The makefiles submit ...
quantum231's user avatar
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Why does the resistor need to be placed before the junction in an RTL NOT Circuit

I am trying to implement a simple inverter using transistors. I am confused why placing the resistor between the junction and the LED will not work, but placing the resistor before the junction does ...
michael_fortunato's user avatar
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Why the prohibition against blocking statements in FF synthesis?

In most intros to Verilog, it's basically stated as a law that "blocking is for combinational and nonblocking is for sequential". That turns out to be a good rule of thumb because of how ...
EE18's user avatar
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Why can't you mix edge signals with level signals in SystemVerilog for synthesis?

In a number of sources I've come across, it's mentioned that for sensitivity lists which include an "edge", you cannot include other signals in the sensitivity list if you want synthesis to ...
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In SystemVerilog, is the set of operators usable in a continuous assignment smaller than that usable in an always statement?

My question is, essentially, as stated in the title. For what it's worth, it's prompted by a comment made by Stuart Sutherland on page 256 of his RTL Modelling with SystemVerilog: The primary RTL ...
EE18's user avatar
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Is it possible to have a C language model of design in same simulation as the RTL itself and compare their outputs?

Assume that an algorithm exists in C language. It needs to be implemented in VHDL. One way to compare the two is to apply stimulus from file to model using another program or script and then store the ...
gyuunyuu's user avatar
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Ethernet MAC Controller IC design process

I'm from an embedded software background, and I am trying to learn more about chip design. To this end I want to understand what goes into designing and implementing a digital IC like an ethernet ...
NeedToKnow's user avatar
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1 answer
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Is there a way to make the Verilog port declaration based on a macro value?

Basically, what I am trying to achieve is that, There is a macro REG_COUNT. Based on the value inside the macro, the N number registers get initialized. But I also want to create dedicated output ...
Vasant Joseph's user avatar
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Is it possible to pass random values into SystemVerilog module parameter?

I'm trying to pass a random value using $urandom into a parameter for a top-level module in my testbench. But, I get the error: ...
Ronan's user avatar
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What does it mean for a digital logic signal to qualify another signal?

The wishbone specification refers to signals being qualified by other signals: The strobe output [STB_O] indicates a valid data transfer cycle. It is used to qualify various other signals on the ...
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Discrepancy between simulation results and RTL viewer in Quartus II 18.0 for my Verilog code

Here's the Verilog code for my UsedBeforeAssign module: ...
Tokubara's user avatar
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1 answer
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Understanding decode stage of x86 fetch-decode-execute pipeline and its (lack of) register requirements

FDE pipeline has register requirements for the F & D stages: For fetching an instruction from memory, the instruction pointer register points to the memory location of the next instruction to be ...
computegirl314's user avatar
2 votes
2 answers
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Multiplication in VHDL by a fraction

I am trying to multiply a 8-bit number with 5/7 in VHDL language. I wrote 5/7 as a 20-bit binary and stored the multiplication in a 10-bit variable by only taking first 10-bit numbers of the result. ...
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What are W1C and R1C register access types?

I drew a diagram for the W1C and R1C register access types for register file/bank. First I am trying to make a register file for different registers. I am using D-FF to store 1-bit data, but I'm ...
P Ksagar's user avatar
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VHDL: Testbench for ASK modulator

I've been trying to learn VHDL recently and came across the following tutorial for an ASK modulator: https://surf-vhdl.com/implement-digital-ask-modulator-vhdl/ I tried writing a testbench for this ...
user1397215's user avatar
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1 answer
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Mitigating structural hazards in register files in processor pipelines

I am reading about structural hazards in pipelined architecture in processors. In classic RISC pipeline one such hazard is when we write and read simultaneously to same register, which may cause ...
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How to rewrite the following code using a for loop in Verilog?

Is it possible to write the following code using a for loop in Verilog? ...
eldenlord9394's user avatar
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2 answers
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Should HDL code be modified with delays if post-synthesis simulation is not expected?

I'm very interested in but pretty new to hardware development. I have designed a 101 sequence detector using the Verilog language, but I saw a difference in behaviour simulation and post-synthesis ...
xc wang's user avatar
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Performance metrics for a VHDL/Verilog RTL design

Correctness and performance is everything in programming. Verifying it for software is relatively easy because you can "just" run the program and see if it crashes and/or is very slow. ...
Gaslight Deceive Subvert's user avatar
2 votes
1 answer
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Verilog coding guidance for operations in different cycles

I want to do 3 operations in 3 different clock cycles: data in, addition and multiplication, and then repeat. Can anyone give me a Verilog template to implement the above? Something like this ...
eldenlord9394's user avatar
3 votes
1 answer
170 views

Verilog generate block error

I have a CORDIC module that I want to instantiate/generate 8 times, basically, I need 8 blocks of CORDIC. So, I have wrote the following statement block, but I get an error: Error: Syntax error near ...
eldenlord9394's user avatar
3 votes
2 answers
2k views

Reading a file in Verilog

I want to read a file in Verilog that contains both positive and negative numbers. For example, the file contents are: -4 20 28 -52 and so on. Also, after reading ...
blackblade's user avatar
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2 answers
164 views

What is the correct unit to specify throughput of an RTL block? [closed]

There does not seem to be an agreed way to calculate throughput for digital circuit design which is confusing. I am talking about front end design i.e RTL coding. The data rate can be represented as ...
quantum231's user avatar
2 votes
1 answer
708 views

Hardware implementation of Verilog Block & Non-blocking FSM

I'm doing a FSM question from here: https://hdlbits.01xz.net/wiki/Fsm1s I have implemented 2 different FSM using non-blocking and blocking for this question. Non-blocking: ...
Yee Yang Tan's user avatar
2 votes
1 answer
316 views

Why is the number of instances shown in the RTL viewer and technology map (post-fit) different in Quartus Prime Lite?

I am a beginner in using FPGA and Quartus Prime Lite. I created a 32-bit adder using four 8-bit adders. These 8-bit adders were created using eight full adders. I did the design using schematic .BDF ...
kalana sanhinda jayalath's user avatar
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1 answer
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FPGAcontrolling VGA: why does the monitor show a right triangle and not an isosceles one?

I'm trying to draw on a monitor by using an FPGA (SPARTAN 3A) and by considering a monitor with 640x480@60 Hz of resolution. In my code, I would like to start from a certain pixel (320,190) and to ...
sun's user avatar
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1 answer
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RTL to Gate Level Design - Verilog

I have written the following code for sinc3 flter in verilog (Vivado). I need to ask how shall I now convert this RTL design to a logic Gate level design in verilog (add AND, NOR, flip flops, etc.)? ...
Param Khurana's user avatar
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1 answer
1k views

SystemVerilog Mux design with "always_comb and tri state variables"

Here is my code for a mux inside an always_comb block. I'm designing a mux with combinatorial logic where I use the shortened ...
nebuchadnezzar_II's user avatar
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2 answers
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Concatenation with non-blocking assignment

I'm teaching myself Verilog with HDLbits and tackling this problem. According to this post, assignment with the LHS of the expression as a concatenation should work. In practice I've used this many ...
Michael's user avatar
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How to see the conections in a decoder Quartus II web edition

I have a decoder whos 16 bit output is conecting to a one bit input. Acording to my knowldge of the design it would make sense. How can i know which output port of the decoder is conecting to that ...
Daniel Melo Avila's user avatar
1 vote
3 answers
344 views

How to check if all the signals used have been reset in a VHDL process?

I sometimes make mistake when changing VHDL code to add new functionality that, the new signals added into the VHDL process are not reset when the reset state is asserted. This mistake could be quite ...
quantum231's user avatar
4 votes
1 answer
1k views

Is it a good practice to put assertion statements into VHDL RTL code to aid in simulation?

There is something called Assertion based testbenches. I am not aware of what they are or if they are possible in VHDL. But in any case, is it a good practice to sprinkle assertion statements in RTL ...
quantum231's user avatar
1 vote
2 answers
652 views

Techniques to develop software and hardware of a SoC in parallel

Hardware development takes a lot of time to develop. If a company is building a System-on-chip (SoC), the RTL model of the SoC is only available after the RTL integration is complete. This requires ...
Shashank V M's user avatar
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0 votes
1 answer
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Is there any reason why the Design Compiler does not optimize a path which it can optimize in a submodule

I have an issue in timing slack got from Design Compiler (DC.) One path Reg2reg in my submodule just was fine, but that path is found to be longer in the top module. It seems that the path was not ...
Slack's user avatar
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4 votes
1 answer
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When to set defaults for VHDL generics

VHDL generics can have a default value. The rules for how they are overridden in instantiations and declarations seems to be rather complex, so I wanted to ask about the easiest and safest practices ...
P2000's user avatar
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1 vote
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How to hash map known values to smaller data width?

Story: I have an input bus of 17b = 131 072 values. An output bus of 10b = 1024 values. Among all the 131 072, only 20 000 values are used and known in advance. I'd like to map all those 20 000 values ...
None's user avatar
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3 votes
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Fan out of TTL Circuit

In this image When calculating the fan out of the TTL circuit the current in the TTL drive output is 16mA and is divided into the emitters of the load each emitter has 1.6mA because the fan out is 10. ...
Ahmed Redwan's user avatar
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698 views

Are Verilog and VHDL Register Transfer Languages?

I have seen the term Register Transfer Language being used as the expansion of RTL in the context of Hardware Description Languages (HDLs). Specifically over here: https://www.cl.cam.ac.uk/teaching/...
Shashank V M's user avatar
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Place cells certain distance apart using Design compiler (DC)

So as an example for self-learning, I am trying to place two Flip Flops (FFs) at a certain distance apart. Except for these two FFs which must be at a certain distance apart, other cells might occupy ...
zzzz za's user avatar
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1 answer
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How to build large demultiplexers using SystemVerilog?

Note: This question about demultiplexers is similar to but not identical to this question which is about multiplexers. I want to build a fully parameterisable demultiplexer in SystemVerilog. So far, I ...
Shashank V M's user avatar
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How to build large multiplexers using SystemVerilog?

Note: This question about multiplexers is similar to but not identical to this question which is about demultiplexers. I want to build a fully parameterisable multiplexer in SystemVerilog. So far, I ...
Shashank V M's user avatar
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1 vote
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725 views

How do I build and simulate a T Flip-Flop without a reset in SystemVerilog?

I found that I could not get a T Flip-Flop without a reset to simulate in SystemVerilog, but I could get a JK Flip-Flop without a reset to simulate. This is because I can set a JK Flip-Flop to a known ...
Shashank V M's user avatar
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