Questions tagged [rtl]
Register Transfer Level (RTL) is a logic design abstraction where digital circuits are described in terms of storage elements (registers) and the combinatorial logic operations that occur between them. RTL is one technique of describing a digital system using hardware description languages such as VHDL and Verilog.
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Is there a way to make the Verilog port declaration based on a macro value?
Basically, what I am trying to achieve is that,
There is a macro REG_COUNT. Based on the value inside the macro, the N number registers get initialized.
But I also want to create dedicated output ...
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Is it possible to pass random values into SystemVerilog module parameter?
I'm trying to pass a random value using $urandom into a parameter for a top level module in my testbench. I get the error:
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What does it mean for a digital logic signal to qualify another signal?
The wishbone specification refers to signals being qualified by other signals:
The strobe output [STB_O] indicates a valid data transfer cycle. It is used to qualify
various other signals on the ...
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Discrepancy between simulation results and RTL viewer in Quartus II 18.0 for my Verilog code
Here's the Verilog code for my UsedBeforeAssign module:
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Understanding decode stage of x86 fetch-decode-execute pipeline and its (lack of) register requirements
FDE pipeline has register requirements for the F & D stages: For fetching an instruction from memory, the instruction pointer register points to the memory location of the next instruction to be ...
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Multiplication in VHDL by a fraction
I am trying to multiply a 8-bit number with 5/7 in VHDL language. I wrote 5/7 as a 20-bit binary and stored the multiplication in a 10-bit variable by only taking first 10-bit numbers of the result. ...
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What are W1C and R1C register access types?
I drew a diagram for the W1C and R1C register access types for register file/bank. First I am trying to make a register file for different registers. I am using D-FF to store 1-bit data, but I'm ...
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VHDL: Testbench for ASK modulator
I've been trying to learn VHDL recently and came across the following tutorial for an ASK modulator: https://surf-vhdl.com/implement-digital-ask-modulator-vhdl/
I tried writing a testbench for this ...
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How to manage address space data for multiple RTL modules that contain memory mapped slave ports?
A project contains multiple RTL modules with each having one or more memory mapped slave ports. Each module has a set of registers that can be accessed using this. There are read-only registers, those ...
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Rationale for cascading skid buffer
My questions are specifically related to this short article titled "Designing Skid Buffers for Pipelines" from chipmunk.
I understand the basic issue that for the valid/ready handshake to ...
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Mitigating structural hazards in register files in processor pipelines
I am reading about structural hazards in pipelined architecture in processors. In classic RISC pipeline one such hazard is when we write and read simultaneously to same register, which may cause ...
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How to rewrite the following code using a for loop in Verilog?
Is it possible to write the following code using a for loop in Verilog?
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Should HDL code be modified with delays if post-synthesis simulation is not expected?
I'm very interested in but pretty new to hardware development. I have designed a 101 sequence detector using the Verilog language, but I saw a difference in behaviour simulation and post-synthesis ...
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Performance metrics for a VHDL/Verilog RTL design
Correctness and performance is everything in programming. Verifying it for software is relatively easy because you can "just" run the program and see if it crashes and/or is very slow. ...
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Verilog coding guidance for operations in different cycles
I want to do 3 operations in 3 different clock cycles: data in, addition and multiplication, and then repeat. Can anyone give me a Verilog template to implement the above? Something like this ...
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Verilog generate block error
I have a CORDIC module that I want to instantiate/generate 8 times, basically, I need 8 blocks of CORDIC. So, I have wrote the following statement block, but I get an error:
Error: Syntax error near ...
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Reading a file in Verilog
I want to read a file in Verilog that contains both positive and negative numbers. For example, the file contents are:
-4
20
28
-52
and so on.
Also, after reading ...
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What is the correct unit to specify throughput of an RTL block? [closed]
There does not seem to be an agreed way to calculate throughput for digital circuit design which is confusing. I am talking about front end design i.e RTL coding. The data rate can be represented as ...
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Hardware implementation of Verilog Block & Non-blocking FSM
I'm doing a FSM question from here: https://hdlbits.01xz.net/wiki/Fsm1s
I have implemented 2 different FSM using non-blocking and blocking for this question.
Non-blocking:
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Why is the number of instances shown in the RTL viewer and technology map (post-fit) different in Quartus Prime Lite?
I am a beginner in using FPGA and Quartus Prime Lite. I created a 32-bit adder using four 8-bit adders. These 8-bit adders were created using eight full adders.
I did the design using schematic .BDF ...
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FPGAcontrolling VGA: why does the monitor show a right triangle and not an isosceles one?
I'm trying to draw on a monitor by using an FPGA (SPARTAN 3A) and by considering a monitor with 640x480@60 Hz of resolution. In my code, I would like to start from a certain pixel (320,190) and to ...
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RTL to Gate Level Design - Verilog
I have written the following code for sinc3 flter in verilog (Vivado). I need to ask how shall I now convert this RTL design to a logic Gate level design in verilog (add AND, NOR, flip flops, etc.)? ...
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SystemVerilog Mux design with "always_comb and tri state variables"
Here is my code for a mux inside an always_comb block. I'm designing a mux with combinatorial logic where I use the shortened ...
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Concatenation with non-blocking assignment
I'm teaching myself Verilog with HDLbits and tackling this problem. According to this post, assignment with the LHS of the expression as a concatenation should work. In practice I've used this many ...
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How to see the conections in a decoder Quartus II web edition
I have a decoder whos 16 bit output is conecting to a one bit input. Acording to my knowldge of the design it would make sense. How can i know which output port of the decoder is conecting to that ...
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How to check if all the signals used have been reset in a VHDL process?
I sometimes make mistake when changing VHDL code to add new functionality that, the new signals added into the VHDL process are not reset when the reset state is asserted. This mistake could be quite ...
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Is it a good practice to put assertion statements into VHDL RTL code to aid in simulation?
There is something called Assertion based testbenches. I am not aware of what they are or if they are possible in VHDL.
But in any case, is it a good practice to sprinkle assertion statements in RTL ...
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Techniques to develop software and hardware of a SoC in parallel
Hardware development takes a lot of time to develop. If a company is building a System-on-chip (SoC), the RTL model of the SoC is only available after the RTL integration is complete. This requires ...
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Is there any reason why the Design Compiler does not optimize a path which it can optimize in a submodule
I have an issue in timing slack got from Design Compiler (DC.)
One path Reg2reg in my submodule just was fine, but that path is found to be longer in the top module. It seems that the path was not ...
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When to set defaults for VHDL generics
VHDL generics can have a default value.
The rules for how they are overridden in instantiations and declarations seems to be rather complex, so I wanted to ask about the easiest and safest practices ...
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How to hash map known values to smaller data width?
Story:
I have an input bus of 17b = 131 072 values. An output bus of 10b = 1024 values.
Among all the 131 072, only 20 000 values are used and known in advance.
I'd like to map all those 20 000 values ...
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Fan out of TTL Circuit
In this image When calculating the fan out of the TTL circuit
the current in the TTL drive output is 16mA and is divided into the emitters of the load each emitter has 1.6mA because the fan out is 10.
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Are Verilog and VHDL Register Transfer Languages?
I have seen the term Register Transfer Language being used as the expansion of RTL in the context of Hardware Description Languages (HDLs). Specifically over here: https://www.cl.cam.ac.uk/teaching/...
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Place cells certain distance apart using Design compiler (DC)
So as an example for self-learning, I am trying to place two Flip Flops (FFs) at a certain distance apart.
Except for these two FFs which must be at a certain distance apart, other cells might occupy ...
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How to build large demultiplexers using SystemVerilog?
Note: This question about demultiplexers is similar to but not identical to this question which is about multiplexers.
I want to build a fully parameterisable demultiplexer in SystemVerilog. So far, I ...
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How to build large multiplexers using SystemVerilog?
Note: This question about multiplexers
is similar to but not identical to this question which is about demultiplexers.
I want to build a fully parameterisable multiplexer in SystemVerilog. So far, I ...
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How do I build and simulate a T Flip-Flop without a reset in SystemVerilog?
I found that I could not get a T Flip-Flop without a reset to simulate in SystemVerilog, but I could get a JK Flip-Flop without a reset to simulate. This is because I can set a JK Flip-Flop to a known ...
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Unable to simulate a JK Flip-Flop using VHDL dataflow modelling
I want to write code and simulate waveforms for flip flops strictly using dataflow modelling. In this case I'm simulating a jk flip flop with only j,k and clock (no set , reset). It compiles fine, but ...
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Does it make sense to use a clock input for combinational logic?
Today, I came across this problem on QuickSilicon's RTL Hackathon. It was to design an Endian converter.
The requirements were
The output should be available in the same cycle
The module should ...
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How to implement Clock Gating Style RTL into synthesis?
I'm studying to implement a Clock Gating in RTL.
So I've followed as the below
https://www.design-reuse.com/articles/23701/power-analysis-clock-gating-rtl.html
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Test bench when design is pipelined
I have a design with chained modules. Each of them is a pipelined design, so the output in each of them take more than 1 clock cycle. To perform the test bench, I have created so many registered ...
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ALU result is 0, how to fix this?
In system-verilog I am trying to build a small ALU unit which takes a and calculates the negative value of it (-1) in a CPU.
I wrote:
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Is (BC + AD)<<16 equivalent to (BC << 16) + (AD <<16)?
Is the expression (BC + AD)<<16 equivalent to (BC << 16) + (AD <<16)?
From some examples which I tried it seems to be true but not sure at all
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Difference between Gate Instantiation and SystemVerilog operator
Today I learned about & and ! operators.
But I can't understand what is the difference between these two:
A=B & C;
AND(...
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Synopsys Design Compiler: Setting a maximum critical path delay on sequential circuits
I have a couple of designs written in Verilog that I'm trying to synthesize with Synopsys DC Compiler. Specifically, I would like to maintain a 1ns upper bound on my critical path delay (CPD) on my ...
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Unexpected Behavior: i2s L/R clock only works under arbitrary conditions?
I'm new to Verilog (and HDL at all) and working with a Cyclone II EP2C5 Mini Dev Board in Quartus II (version 13sp1 to be compatible with my cheap FPGA).
I use the below two modules (one mostly just a ...
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hardware software co-simulation in HDL simulator
When we simulate (VHDL) RTL designs in a simulation tool like ModelSim or ActiveHDL e.t.c, we can have a complete visibility of all signals and variables in the design. This goes a great deal in ...
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My RTL viewer replaces NAND gates with AND gates with the inversion bubbles
I want it to show this MUX only with 3 NAND gates and an Inverter.
so, I specified NAND gate in the verilog HDL code, but it keeps replacing it with AND gates with inversion bubbles without having a ...
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How to design Gray code synchronous counters of large widths using SystemVerilog?
I want to design a synchronous gray code counter which is 10 bits wide in SystemVerilog. The counter should have an Active HIGH synchronous reset.
I know how to design a 3 bit gray code counter like ...
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How to decide when to use flop or RAM based fifo?
Trying to figure out what are the tradeoff like power, size when deciding between using a flop or RAM based fifo ? Any known publications ?
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