Questions tagged [rtl]

Register Transfer Level (RTL) is a logic design abstraction where digital circuits are described in terms of storage elements (registers) and the combinatorial logic operations that occur between them. RTL is one technique of describing a digital system using hardware description languages such as VHDL and Verilog.

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Hardware implementation of Verilog Block & Non-blocking FSM

I'm doing a FSM question from here: https://hdlbits.01xz.net/wiki/Fsm1s I have implemented 2 different FSM using non-blocking and blocking for this question. Non-blocking: ...
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Why is the number of instances shown in the RTL viewer and technology map (post-fit) different in Quartus Prime Lite?

I am a beginner in using FPGA and Quartus Prime Lite. I created a 32-bit adder using four 8-bit adders. These 8-bit adders were created using eight full adders. I did the design using schematic .BDF ...
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FPGAcontrolling VGA: why does the monitor show a right triangle and not an isosceles one?

I'm trying to draw on a monitor by using an FPGA (SPARTAN 3A) and by considering a monitor with 640x480@60 Hz of resolution. In my code, I would like to start from a certain pixel (320,190) and to ...
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RTL to Gate Level Design - Verilog

I have written the following code for sinc3 flter in verilog (Vivado). I need to ask how shall I now convert this RTL design to a logic Gate level design in verilog (add AND, NOR, flip flops, etc.)? ...
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SystemVerilog Mux design with "always_comb and tri state variables"

Here is my code for a mux inside an always_comb block. I'm designing a mux with combinatorial logic where I use the shortened ...
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Concatenation with non-blocking assignment

I'm teaching myself Verilog with HDLbits and tackling this problem. According to this post, assignment with the LHS of the expression as a concatenation should work. In practice I've used this many ...
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How to see the conections in a decoder Quartus II web edition

I have a decoder whos 16 bit output is conecting to a one bit input. Acording to my knowldge of the design it would make sense. How can i know which output port of the decoder is conecting to that ...
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How to check if all the signals used have been reset in a VHDL process?

I sometimes make mistake when changing VHDL code to add new functionality that, the new signals added into the VHDL process are not reset when the reset state is asserted. This mistake could be quite ...
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Is it a good practice to put assertion statements into VHDL RTL code to aid in simulation?

There is something called Assertion based testbenches. I am not aware of what they are or if they are possible in VHDL. But in any case, is it a good practice to sprinkle assertion statements in RTL ...
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Techniques to develop software and hardware of a SoC in parallel

Hardware development takes a lot of time to develop. If a company is building a System-on-chip (SoC), the RTL model of the SoC is only available after the RTL integration is complete. This requires ...
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Is there any reason why the Design Compiler does not optimize a path which it can optimize in a submodule

I have an issue in timing slack got from Design Compiler (DC.) One path Reg2reg in my submodule just was fine, but that path is found to be longer in the top module. It seems that the path was not ...
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When to set defaults for VHDL generics

VHDL generics can have a default value. The rules for how they are overridden in instantiations and declarations seems to be rather complex, so I wanted to ask about the easiest and safest practices ...
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How to hash map known values to smaller data width?

Story: I have an input bus of 17b = 131 072 values. An output bus of 10b = 1024 values. Among all the 131 072, only 20 000 values are used and known in advance. I'd like to map all those 20 000 values ...
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Fan out of TTL Circuit

In this image When calculating the fan out of the TTL circuit the current in the TTL drive output is 16mA and is divided into the emitters of the load each emitter has 1.6mA because the fan out is 10. ...
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Are Verilog and VHDL Register Transfer Languages?

I have seen the term Register Transfer Language being used as the expansion of RTL in the context of Hardware Description Languages (HDLs). Specifically over here: https://www.cl.cam.ac.uk/teaching/...
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Place cells certain distance apart using Design compiler (DC)

So as an example for self-learning, I am trying to place two Flip Flops (FFs) at a certain distance apart. Except for these two FFs which must be at a certain distance apart, other cells might occupy ...
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How to build large demultiplexers using SystemVerilog?

Note: This question about demultiplexers is similar to but not identical to this question which is about multiplexers. I want to build a fully parameterisable demultiplexer in SystemVerilog. So far, I ...
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How to build large multiplexers using SystemVerilog?

Note: This question about multiplexers is similar to but not identical to this question which is about demultiplexers. I want to build a fully parameterisable multiplexer in SystemVerilog. So far, I ...
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How do I build and simulate a T Flip-Flop without a reset in SystemVerilog?

I found that I could not get a T Flip-Flop without a reset to simulate in SystemVerilog, but I could get a JK Flip-Flop without a reset to simulate. This is because I can set a JK Flip-Flop to a known ...
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Unable to simulate a JK Flip-Flop using VHDL dataflow modelling

I want to write code and simulate waveforms for flip flops strictly using dataflow modelling. In this case I'm simulating a jk flip flop with only j,k and clock (no set , reset). It compiles fine, but ...
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2 answers
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Does it make sense to use a clock input for combinational logic?

Today, I came across this problem on QuickSilicon's RTL Hackathon. It was to design an Endian converter. The requirements were The output should be available in the same cycle The module should ...
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How to implement Clock Gating Style RTL into synthesis?

I'm studying to implement a Clock Gating in RTL. So I've followed as the below https://www.design-reuse.com/articles/23701/power-analysis-clock-gating-rtl.html ...
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Test bench when design is pipelined

I have a design with chained modules. Each of them is a pipelined design, so the output in each of them take more than 1 clock cycle. To perform the test bench, I have created so many registered ...
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ALU result is 0, how to fix this?

In system-verilog I am trying to build a small ALU unit which takes a and calculates the negative value of it (-1) in a CPU. I wrote: ...
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Is (BC + AD)<<16 equivalent to (BC << 16) + (AD <<16)?

Is the expression (BC + AD)<<16 equivalent to (BC << 16) + (AD <<16)? From some examples which I tried it seems to be true but not sure at all
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Difference between Gate Instantiation and SystemVerilog operator

Today I learned about & and ! operators. But I can't understand what is the difference between these two: A=B & C; AND(...
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2 votes
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Synopsys Design Compiler: Setting a maximum critical path delay on sequential circuits

I have a couple of designs written in Verilog that I'm trying to synthesize with Synopsys DC Compiler. Specifically, I would like to maintain a 1ns upper bound on my critical path delay (CPD) on my ...
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1 answer
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Unexpected Behavior: i2s L/R clock only works under arbitrary conditions?

I'm new to Verilog (and HDL at all) and working with a Cyclone II EP2C5 Mini Dev Board in Quartus II (version 13sp1 to be compatible with my cheap FPGA). I use the below two modules (one mostly just a ...
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1 answer
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hardware software co-simulation in HDL simulator

When we simulate (VHDL) RTL designs in a simulation tool like ModelSim or ActiveHDL e.t.c, we can have a complete visibility of all signals and variables in the design. This goes a great deal in ...
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2 votes
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My RTL viewer replaces NAND gates with AND gates with the inversion bubbles

I want it to show this MUX only with 3 NAND gates and an Inverter. so, I specified NAND gate in the verilog HDL code, but it keeps replacing it with AND gates with inversion bubbles without having a ...
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How to design Gray code synchronous counters of large widths using SystemVerilog?

I want to design a synchronous gray code counter which is 10 bits wide in SystemVerilog. The counter should have an Active HIGH synchronous reset. I know how to design a 3 bit gray code counter like ...
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How to decide when to use flop or RAM based fifo?

Trying to figure out what are the tradeoff like power, size when deciding between using a flop or RAM based fifo ? Any known publications ?
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5 answers
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Debounce circuit design in Verilog

I'm trying to design a de-bouncer circuit , which is widely used in digital design . The module that I'm trying to implement is as shown below :- I've written the following Verilog Module :- ...
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3 votes
2 answers
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'1011' Overlapping (Moore) Sequence Detector in Verilog

I'm designing a "1011" overlapping sequence detector, using Moore Model in Verilog . The FSM that I am trying to implement is as shown below :- Verilog Module :- ...
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5 votes
2 answers
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'1011' Overlapping (Mealy) Sequence Detector in Verilog

I'm designing a "1011" overlapping sequence detector,using Mealy Model in Verilog. The FSM that I'm trying to implement is as shown below :- Verilog Module :- ...
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1 vote
2 answers
235 views

(7,4) cyclic code encoder in VHDL

I am trying to write code for a cyclic code encoder in VHDL, but I am not able to visualize how to approach the problem. Right now all I have is an entity and a few diagrams showing my approach as to ...
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systemverilog same function, different simulation

I am actually seeking the root cause why the simulator calculates different results for these signal prova1 and prova2 as in my opinion those are representing the very same function Signal ...
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1 vote
2 answers
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Is it possible to have a register with multiple drivers?

This is just a theoretical question I have. Imagine we have a register (a reg signal in Verilog for example) and two possible inputs that have to write to that register. I am assuming all signals are ...
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FSM modeling when outputs are not simple functions of input and current states

All the two/three process block modeling style(the recommended style) examples for FSM have logic for nextstate that is a function of current state and inputs. The outputs in these examples also take ...
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Is it better to combine logic for two flip flops in a single always block?

I have always used separate always block for infering different flip flops when they dont have much in common. ...
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2 votes
2 answers
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Verilog code to drive a signal high always

I am learning Verilog fundamentals recently. I want to drive a signal always high using reg. I wrote this and it didn't work. ...
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4 answers
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How to avoid big mux in RTL design?

When doing rtl design, mux is always used to select the input of a block/module, for example: ...
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1 vote
1 answer
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What is the difference between a hard module and a softmodule in RTL verilog code?

I understand a Verilog code is made up of modules there are RTL codes where a lot of submodules can be instantiated in the main module. If I assume the main module(the top one) to be the parent and ...
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Is it possible to create a PLL purely in digital design, if so how?

Provided that we want to reduce jitter on an a periodic input signal (square wave between 0 and Vcc) which is only in some 100 of KHz range, one possibility is to create a system purely using RTL code ...
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1 vote
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How to design asynchronous LIFO?

Is it possible to design asynchronous LIFO ( i.e. LIFO with different READ and WRITE clock) In FIFO , we need to change the write address pointer only on wr_clk while in LIFO we need to change the ...
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Respecting setup/hold time in RTL design

This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals. In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
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3 votes
1 answer
1k views

Quartus 10166 error: "Always_comb construct does not infer purely combinational logic"

The error is coming from the second always construct. I have no idea how a latch is inferred since I've specified the output for every possible input state. Any ideas? ...
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SystemVerilog Finite State Machine debugging

I am trying to debug my finite state machine in modelsim and I have no idea what's wrong with the code. It would be helpful to see the state/next_state internal signals in the waveform viewer. Is this ...
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Finite state machine to detect if a number is divisible by 5 if LSB comes first [duplicate]

If MSB comes in first, we can keep track of the remainder for each new bit since the additional bit will either cause the number to be 2x or 2x+1. But if LSB comes in first, how can we come up with ...
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6 votes
1 answer
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High-Level Synthesis (HLS) vs RTL for ASIC flow

I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level ...
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