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Questions tagged [rtl]

Register Transfer Level (RTL) is a logic design abstraction where digital circuits are described in terms of storage elements (registers) and the combinatorial logic operations that occur between them. RTL is one way of describing a system in hardware design languages such as VHDL and Verilog.

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Quartus 10166 error: “Always_comb construct does not infer purely combinational logic”

The error is coming from the second always construct. I have no idea how a latch is inferred since I've specified the output for every possible input state. Any ideas? ...
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2answers
35 views

SystemVerilog Finite State Machine debugging

I am trying to debug my finite state machine in modelsim and I have no idea what's wrong with the code. It would be helpful to see the state/next_state internal signals in the waveform viewer. Is this ...
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72 views

Finite state machine to detect if a number is divisible by 5 if LSB comes first [duplicate]

If MSB comes in first, we can keep track of the remainder for each new bit since the additional bit will either cause the number to be 2x or 2x+1. But if LSB comes in first, how can we come up with ...
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170 views

High-Level Synthesis (HLS) vs RTL for ASIC flow

I'd like to know when it's a good idea to use HLS over RTL (Verilog/VHDL) design if I'm targetting ASIC implementation? Can synthesis tools like Design Compiler convert HLS C/C++ into gate-level ...
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1answer
149 views

Including one module in another module with variable

I need to implement this code to synthesize and do so that xor21 and and21 will work separately. ...
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1answer
47 views

Is there a way to convert BSDL format to synthesizable verilog?

I have a BSDL file for a device for which I need to generate test patterns through an FPGA. I learnt that BSDL is a subset of VHDL but the file looks like it describes the hardware of the DUT. I know ...
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0answers
87 views

How do I give clock constraint for a ring oscillator output?

I have 2 clocks in my design. One slow External clock and one high frequency ring oscillator clock. For external clock I am using the create_clock command to specify timing. The ring oscillator block ...
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1answer
38 views

How does synthesis tool handle the ports either driven by or to a module that is empty(Black Box)?

I have a design that instantiates a Memory and a Ring oscillator which I am excluding from synthesis by making them black boxes.(Not specifying explicitly, but instantiating an empty module with only ...
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5answers
164 views

Will the High-Level Synthesis (HLS) design approach for FPGAs reduce the demand for RTL designers? [closed]

I'm a senior electrical engineering student who's very interested in FPGAs and RTL design. But recently after learning what HLS compilers are capable of I had to consider the possibility that ...
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1answer
752 views

I am designing a VHDL code for memory read and write operation

I am witing a VHDL code to read and write to ram. The code is attached as below, ...
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2answers
2k views

How to send a packet every n clock cycles in verilog?

I am fairly new to Verilog and in general Digital Design. I am working on a project which has a state machine. The module, in a particular state, receives a read request packet from some other module ...
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2answers
119 views

Determine which clock has arrived first

There are two clocks of the same frequency, but one has a phase shift. So we have two clocks, one leading and one lagging. How can we determine which clock has arrived first? One way would be to use ...
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1answer
523 views

Verilog: Instantiation of lpm_dff failed. The design unit was not found

I want to use lpm_dff components in my design. I can compile the code without problem in modelsim, But when i try to simulate my ...
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2answers
183 views

Relation between RTL and Verilog modules

I am taking a digital design course and I didn't get something. RTL design includes datapath and controller, that's ok but what's the relation between these and verilog modules. For example, is ...
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2answers
861 views

Why aren't latch based designs common these days?

Almost every ASIC out there if flip-flop based. In summary, DFF is two latches pushed closely together. While in a latch based design you can "separate" these two latches apart and squeeze logic in-...
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1answer
765 views

Master-Slave D-FF vs Edge triggered: timing issues, simulation shoot-through

There is a thing that bugs me about flipflops: usually, the edge-triggered flops are used, which sample D and update their Q on the posedge, i.e. master latch has inverted clock and slave latch has ...
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2answers
277 views

Clock Domain Crossing: Is it possible to design an architecture from faster to slower domain and slower to faster domain simultaneously?

If I have a design which has read clock and write clock, and I want to make it work for the following scenarios: faster read clock and slower write clock slower read clock and faster write clock Is ...
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1answer
473 views

What is quad 8:1 MUX?

In my assignment i'm asked to show a block diagram for quad 8:1 Multiplexer. But i have no idea what the word quad means in this question. Can someone help me?
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1answer
78 views

Why should we avoid including both blocking and unblocking assignment in same always block?

Nearly all verilog books and blogs strongly suggest not to include blocking and unblocking assignment in same always block. But sometimes I also saw some code that has both blocking and unblocking ...
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2answers
269 views

Implementing gravity in VHDL and VGA.

I am working on a vhdl/fpga project using the vga module. I am trying to make an object fall with an acceleration (gravity). I found an answer on another problem, and it suggest to implement something ...
2
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1answer
4k views

Assigning the different value to parameters in Generate block in Verilog

I want to instantiate a module having parameters using generate block. But I want to assign different values to parameter for different instantiation of the module. For example: This is my module ...
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2answers
2k views

What is application of latch in VLSI design?

I went through the documents stating difference between latch and flip flop. I even came across the scenarios where unintentional latches are created in RTL designs. My doubt is there any real ...
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3answers
90 views

Timing warnings for functional model

I am writing a controller for a low power/mobile DDR module on my FPGA. To allow debugging, I use a functional model written in Verilog. In it, the setup and hold time for some signal is set to 1.5 ns....
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1answer
1k views

How to debug combinational loop warning in Xilinx ISE

I am designing a Binary to BCD converter logic circuit for implementation on Xilinx Spartan 6 FPGA's, and I have a warning during synthesis that looks like this : ...
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2answers
995 views

how to understand xilinx RTL schematics [closed]

I am learning digital logic design with FPGA's, and I am using the Xilinx Spartan6 FPGA. I am able to successfully able to simulate my design correctly, but the design does not work properly, when I ...
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1answer
64 views

register transfer

I am trying to understand RTL(Register-Transfer level) systems and in particular the implementation of the control subsystem by means of sequential execution graphs. I don't understand how to ...
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1answer
201 views

Some question about RTL Design and VHDL

I have some question almost uncorrelated, so I'll enureamted it, hope you can help me: 1) I'm studing RTL Design, and the question is at level of data path, arithmetic unit ecc. I don't understand ...
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1answer
67 views

Common way of describing a “double-sided wait”

Is there a commonly used name to describe a "double-sided wait" data transfer protocol? This is a uni-directional scheme in which data is transferred on the clock edge if both the sender and the ...
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0answers
332 views

Mealy vs. Moore implications for timing closure

I am developing a pipeline block for inclusion in an ASIC. I want to decide between designing the block as a Mealy machine or as a Moore machine. Does this choice have implications for timing ...
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2answers
160 views

Can a flip flop possibly work at over 800MHz? [closed]

As I know, the setup time is at least required time for data to become stable at the input of a FF before the sensitive clock edge. Hold time is the required time for data to remain stable after the ...
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1answer
220 views

What guarantees that RTL inverter is in triode region when the input is high?

in this inverter my instructor says that if Vin is high, we need M to be in triode to have low voltage in the output. now I understand this but I don't know guarantees that it will be in triode. why ...
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1answer
5k views

Using generate to create module ports in systemverilog

Hi I am trying to do something like this ...
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1answer
479 views

removing inout from port arrays

This question is in the context of using verilog/systemverilog for synthesizable RTL. I have some vector signals that are going across module boundaries that are currently defined as inout ports. The ...
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1answer
188 views

how to interpret the RTL report after synthesis in Xilinx?

I did verilog code of a circuit. It was simulating well and giving output correct after Simulation. Now i did synthesis, the RTL schematic after synthesis showing some green and red box. Is it ...
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2answers
2k views

How to find high fanout nets?

In the timing report of a synthesis with Synopsys VCS, a warning states: Warning: Design contains 8 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these ...
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1answer
76 views

How can module TB trap $fatal from module A

I have an RTL simulation where module TB is the testbench for module A. Module A generates $fatal when it meets some condition it doesnt like. Module TB generates/collects transactions to/from A. Is ...
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2answers
101 views

How to power a large RTL project?

I saw this yesterday, and I have been thinking about this: How is all that powered without losing any voltage or power over parts of the project? Would the battery just end up having more energy ...
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1answer
123 views

Can diodes be used as an OR gate when I use RTL for other gates?

I have been using RTL (Resistor-Transistor Logic) to build things like NOT gates, or any other types of logic. If diodes control the flow by letting electricity only flow one way, then could I use two ...
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2answers
211 views

Help me fix my logic circuit

I'm trying to learn more about electronics. So to do that I decided to implement boolean logic gates in a circuit simulator. So far I have made NOT, AND, NOR and a S-R latch. I wanted to try connect ...
7
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1answer
13k views

What is the ideal resistance for a 2N3904 base resistor value when using RTL logic?

I have a ton of 2N3904 transistors and would like to use them for my RTL logic project. Based on what I could figure out on the web, and the parts I had, I've gotten logic gates to work quite well ...
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2answers
226 views

Is it possible to move VHDL code from the top level of a design to a subcomponent, without changing the underlying logic?

Suppose I have a component, called Top_Level, that has a bunch of registers that it uses. There are some subcomponents that perform some combinational logic using the registers. There is also a ...
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0answers
49 views

Change CatapultC RTL naming scheme

I hope someone is familiar with Catapult - available tags make it seem unlikely. My issue is that I have two blocks (as seen in Quartus) being worked on independently, separate RTL. Unfortunately, ...
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1answer
530 views

Prevent Design Compiler from using certain cell types

I am building an RTL design using Synopsys DC and the GTECH library that comes along with it. It is generated using FD1, FD2, FD4 components. I would like to build the design without the FD2, FD4 ...
4
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3answers
314 views

Any benefits from implementing CSA versus just using multiplication symbol when synthesizing?

I am synthesizing some multiplication units in Verilog and I was wondering if you generally get better results in terms of area/power savings if you implement your own CSA using Booth Encoding when ...
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2answers
22k views

How to choose between Mealy and Moore state machine

I know the basic differences between Mealy and Moore FSM (Finite state machine). What I want to understand is the following: Pros and cons of using Mealy over Moore and vice versa In which situation ...
9
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2answers
8k views

How is a VHDL variable synthesized by synthesis tools

I know two ways in which a VHDL variable is synthesized by synthesis tool: Variable synthesized as Combinational logic Variable synthesized as a Latch unintentionally (when an uninitialized variable ...
11
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2answers
25k views

Difference between If-else and Case statement in VHDL

I want to understand how different constructs in VHDL code are synthesized in RTL. Can anyone tell me the difference between If-Else construct and Case statement constructs of a process in VHDL in ...
24
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2answers
42k views

RTL vs HDL? Whats the difference

What is the main difference between RTL and HDL? To be honest I searched / googled it yet people are divided in their opinions. I remember one saying that HDL is the computer language used to describe ...