Questions tagged [sample-and-hold]
Anything related to sample and hold (S/H) circuits. S/H circuits are analog circuits whose purpose is that of sampling the instantaneous value of an analog signal and store that value for a predefined period of time. They are sort of analog memory circuits, and they are often employed as the first stage of analog to digital converter systems.
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Sharing sensor analog output with multiple ADC for digitization
I am using a pressure sensor, MPVZ4006GW6U, and I have an unique requirement where by I need to share this sensor's output with multiple ADC (say ADC128 from TI) for digitization. Each ADC is ...
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26 views
LTspice peak detector analysis: Time step too small
I made a peak detector with a test file in LTspice.
Here is the diagram:
When running the test file, I ran into this an error message:
Time step too small; time = 0.011, timestep = 1.26068e-017: ...
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53 views
Sample and hold & analog shift register
I have this circuit (see first picture.) it's an analog shift register where instead LF386 I use LF398H. This circuit must provide an hyperchaotic behavior for initial conditions x1(0) = l, x2(O) = O....
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Why is the signal at X getting distorted at the input of the mixer (node “X” as shown in figure)
If the signal at X is different from the signal at Y or the pure sine (transient difference) at Y gets distorted at the X, then the sample and hold operation of the input sine wave is not happening ...
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51 views
How to compare Matlab/Theory <=> Cadence: Switched-cap. Integrator: Mag & Phase
I tried to compare the simple switched-capacitor integrator below, between Cadence and Matlab (at the end acting as a simple loop-filter for a delta-sigma). I am stuck now on the point of how to ...
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176 views
Specification of TL07X op-amp, and its hold circuit
I'm using a "TL07xx low-noise FET-input operational amplifier."
I would like to get an amplification of 100 ~ 300 by configuring the feedback loop; a feedback capacitor or resistor for a ...
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54 views
Switched capacitor sample and hold circuit as as mixer
I am trying to find out how important the "hold " level in a sample and hold down-conversion mixer is.
If the level is decreased, will it lead to any loss?
Out of these three subfigures, ...
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141 views
Saving a voltage with ONLY analog components. Best idea?
I am challenging myself to create an analog voltage storage device.
I came up with some ideas and I would like some inputs on what is bests and maybe new ones.
Ideally, I could store a voltage in a ...
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36 views
Significant Oscillation/Instability at Output of AD783JQ Sample and Hold
I am currently working with an AD783JQ sample and hold chip and am trying to characterize its functionality and familiarize myself with its operation before applying it to my project. I believed that ...
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1answer
129 views
Peak hold circuit
I'm testing my peak hold circuit with both LTspice and real one.
When inputting a pulse of 500 mV, LTspice gives 800 mV (green one in upper left) as peak hold. However, real circuit, which is designed ...
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1answer
181 views
Calculate number of ADC clock cycles required for sample time
I'm working with a micro, which has a 12-bit ADC. I am using this ADC to sample a 125Hz signal, with a duty cycle that ranges from 0-100.
On the rising edge of that PWM signal, the ADC will collect a ...
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64 views
Why computers can be modeled as sample and hold system
I was reading digital control system from book by Norman S.Nise and in book it is written that
"computers can be modeled as a sample and hold system "
Isn't computer is discrete time system ...
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46 views
Conditional analog sample and hold (analog override?) - circuit suggestion request
Preamble: I have a LED driven by an opamp-based constant current source (CCS). It works fine, I can set up current required and it is reasonably stable. The problem is, that LED forward voltage drops ...
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3answers
242 views
DAC multiplexer glitch
UPDATE 20th May:
Swapped the analog output regulator for an AZ1117-EH based on Peter Smith's suggestion, removed C1306, so now the 3.3VA output should be ok at least based on the datasheet. However, ...
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1answer
402 views
Sample and hold circuit giving distorted output
I'm making a sample-and-hold circuit for a 3 bit Flash/Parallel ADC and to allow the conversion to have enough time to happen I want to maintain the input voltage steady for the duration the ...
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1answer
167 views
How do these diodes prevent opamp from saturation?
I cannot understand how the clamping diodes prevent opamp from saturation when the switch/FET is off in the following sample-and-hold circuit:
I only know that if the negative feed back of an opamp ...
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40 views
Data path in logic circuit
In the fig below is the path from CLK of 1st FF to Output(DataOut1) a valid data path. If so why is it not shown? Is it because its just the combination of PATH2 and PATH3?
Thanks.
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Buffer requirements for S/H circuits
I am trying to solve question 11.10 which is taken from 2001 GATE IN paper.
So I think the answer is (a) because the input buffer which faces the analog input needs a higher slew rate in order to ...
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1answer
194 views
Bypass Gate-to-trigger-converter via switching jack
Goal
I like to trigger a LF398 Sample-and-Hold IC via a 3.5mm Jack (modular synthesizer). The desired behaviour would be:
if a cable is plugged in, incoming signals will be converted to short ...
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1answer
79 views
Digital sample and hold synced with a CLK
So I though this should be pretty straightforward, but apparently it's not.
Supposed we have a digital async input signal and a CLK. I want to sample the given input signal on every rising (or ...
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2answers
145 views
Create a pulse that is active from ~0.3 to 0.4 times the clock period
I'm sorry if the phrasing is somewhat weird, but the question is hard to articulate. I've created an IC Sample-and-Hold where I have a hold capacitor at the output. I want to charge this capacitor ...
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723 views
Acquisition time of sample & hold circuit
What determines the acquisition time of a sample and hold circuit?
For example if I had wanted to design a circuit that samples at every 0.1 second intervals what would limit and affect the desired ...
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1answer
234 views
Why is my Sample and Hold circuit not working
I have two of these circuits on a board which are both behaving identically. ie. neither is holding a sampled voltage but rather just passing the input directly to the output (indicated as with the ...
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1answer
107 views
What will it happened when capacitance is almost the same as parasitic capacitance
I make a sample and hold (IC design),and it is combined with transmission gate and a 550fF capacitor,and my classmate told me that my capacitor is too small,almost the same as the parasitic ...
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42 views
What kind of wave should i feed the input of sample and hold,which is in the sar adc
There is sample and hold in the sar adc,but i am not sure that i should feed a ramp wave or sine wave to the sample and hold?
Are there any relations to sar adc output and sample and hold input wave?
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How to achieve analog zero-drift sample and hold for hours?
This so-called "zero drift" opamp droops .001V/sec, at temp 85C with a 1 uF cap. If I'm reading the spec correctly, that's 3.6V/hour!
http://www.ti.com/lit/ds/symlink/lf398-n.pdf
Is there a method ...
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2answers
69 views
The output change when i connect it with the other circuit
Two symbols are the same sample and hold,so Theoretically their ouput should be the same,but as we see,when i connect it with a comparator,the output of sample and hold totally change.
Why?How do i ...
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1answer
209 views
The output buffer of sample and hold
I saw some sample and hold circuits from the Internet,and i find there will be a buffer in the output,so i want to ask what does that buffer do for the sample and hold,can i use two stage amplifier as ...
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1answer
67 views
Analog to digital controller-Sampling rate
One method to design a controller for a digital control system is to first design it in the s domain and then convert it. However, choosing a suitable sampling period is important.
In most problems ...
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1answer
574 views
How can I change the reference voltage and resolution of SAMPLE and HOLD block in LTSpice?
I have a question about LTSpice.
I put a Sample & Hold block in a sheet to quantize a continuous sine signal like below:
But the resolution is not desired. I have a 16-Bit ADC with a 1v reference ...
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2answers
85 views
Measuring pulses, options for accumulate samples after trigger
I have a circuit that amplifies pulses and the goal is to measure them with a MCU's ADC in lowest possible power. The pulses width are about 100uS and I am interested about their peak amplitude.
Now ...
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1answer
11k views
Track vs Sample and hold
This is the output of both track and hold and sample and hold.
But when I searched for its circuit I am getting the circuit I have shown below for both. So my question is if the circuit for sample ...
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405 views
Sampling analog signal at 100khz with raspberry pi
I want to sample a ultrasonic wave at 100 Ksps. Currently i am using Raspberry pi and an external adc communicating with each other vis I2S at 96Khz. Since raspberry pi cannot support higher speed ...
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2answers
853 views
Sample & Hold circuit not working for negative half cycle
I have made a Sample & Hold circuit using Multisim but after simulating oscilloscope showing sampled version of input waveform for positive half cycles only. I have used MOSFET as a switch with ...
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1answer
89 views
PSRR - Testing Fixture
I have to design a PSRR test fixture with a 2.4KHz signal imposed on a dc power supply. I can do it using a bias tee at rf but the size of the components at audio confound me. The application is a ...
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2answers
233 views
Output of Sample and Hold Circuit
I'm having a bit of a problem figuring out how this sample and hold circuit works.
I am to calculate \$V_\text{out}\$ if (a) \$A\$ is infinite and if (b) \$A\$ is finite. \$A\$ is the open-loop gain ...
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4answers
3k views
High Frequency (16 Mhz-48 MHz) Peak Hold/Envelope Detector Circuit?
I'm trying to make a peak hold circuit for a very high frequency bandpass filter that needs to be able to operate at 16 Mhz, 40 Mhz, and 48 Mhz.
I've singled out the peak hold part of my overall ...
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1answer
579 views
holding nano second pulse amplitude for measuring its amplitude [closed]
My design problem demands me to read the amplitude level of a 10ns pulse, for which I am trying to find multiple techniques that may be helpful.
input parameters:
...
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1answer
306 views
How do I prolong the reed switch output time
I put a reed switch ( https://en.wikipedia.org/wiki/Reed_switch ) on the handle of a measuring wheel (perambulator). The reed switch will be activated up to around 20 times per second (every 50 ms). ...
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2answers
2k views
Sample and Hold Circuit Capacitor Value
I am simulating a basic sample and hold circuit in TI TINA. The op amp is TI TLV333.
The parameters are:
Vin - 1Hz - DC:150mV - Amplitude:1.3mV
Switching frequency:100Hz
The following two plots ...
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1answer
888 views
How does this sample and hold circuit work?
What role does the 30k resistor play in the LF398?
How would that resistor eliminate any offsets introduced by the op-amps in a circuit like this one:
On this ...
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3answers
880 views
ADC undersampling AND oversampling
I need to accurately measure a narrow band signal (of about 200Hz) centered in a part of spectrum that is many times its band (at about 20kHz). I have only a 12 bit ADC that is relatively fast (5 MSPS)...
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1answer
71 views
multilevel storage elements
I've been experimenting with three-valued logic (yeah, I know) and have had quite a bit of success by using voltage comparators to implement the combinatorial logic. All 27 1-input gates and many ...
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3answers
10k views
Exactly what is the role of the zero-order hold in a hybrid analog/digital sampled-data system?
I'll admit, I am asking this question rhetorically. I am curious what answers will come back out of this.
If you choose to answer this, make sure you understand the Shannon-Nyquist sampling theorem ...
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1answer
935 views
BJT sample and hold circuit for 50 MHz clock
I've designed a sample and hold circuit (as shown in the snapshot of the circuit attached) but i'm having slew rate problems, if I try to adjust the slew rate (by adjusting the capapacitor and ...
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165 views
ADC input enable register
For a Hcs129s12 micro-controller ADC (please see the image) , the sample-and-hold stage accepts analog signals from the input multiplexer and stores them as a charge on the sample capacitor. The ...
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1answer
501 views
ADC conversion timing
Why the conversion time of an ADC is calculated as: number of bits in resolution+number of programmed sample clocks+2/(ADC clock frequency) ? As far as I know for the successive approximation A/D ...
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2answers
682 views
Auto Zero Circuit on AD625 datasheet
The datasheet for the AD625 instrumentation amplifier shows an example circuit with 'Auto Zero' (Figure 36), below. In this circuit an op-amp AD711 is being used to give an offset voltage to zero the ...
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2answers
430 views
Inherent sample and hold in a comparator?
I have been reading up why a flash ADC does not (theoretically) need a sample and hold circuit. I have learned that this is because the comparators have an inherent sample and hold property, but I can ...
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277 views
Resampling with MSB operation
I'm new to verilog and HDL, so please be patient with me.
In a code, I have an input variable clk, two input 16 bit samples, that are stored into ...
