Questions tagged [sample-and-hold]

Anything related to sample and hold (S/H) circuits. S/H circuits are analog circuits whose purpose is that of sampling the instantaneous value of an analog signal and store that value for a predefined period of time. They are sort of analog memory circuits, and they are often employed as the first stage of analog to digital converter systems.

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How to reduce sample and hold circuit drift

I've built a sample and hold circuit on LTSpice, and the output will drift up at a rate of ~100mV/s. Is there an obvious way to reduce this? Is this a function of the FET / opamp used? The obvious ...
Duncan Wither's user avatar
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Sample-and-hold circuit that samples the difference but uses a single-ended opmap

The circuit below shows two things: How to sample a single-ended voltage into a capacitor. How, using a buffer, the voltage can be read by the next stage without affecting the voltage stored in the ...
Leonhard Euler's user avatar
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2 answers
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Resettable integrator resetting to the negative rail not ground

I've recently built a resettable integrator board which uses a low-drift JFET op-amp and a sample and hold chip. The sample and hold amplifier datasheet showed a resettable integrator configuration ...
sam.schimanski's user avatar
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36 views

Relation between rise and fall times and capacitance

So I'm currently reading the datasheet of the Motorola 68hc000 CPU and I want to be able to estimate how many devices I can plug to the bus directly before I encounter issues. So first things first, ...
Lugaid's user avatar
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3 answers
166 views

Analog signal change detection

I'm attempting to monitor a voltage value for any change. I'd like to have a single digital output go high for some duration if the voltage changes at all with a minimum sensitivity of around 0.1 V. ...
ElectronTrafficCop's user avatar
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Unexpected behavior S/H and ADC simulation

I am trying to simulate a primitive ADC consisting of sample-and-hold circuit on the left, unity-gain buffer to minimize drifting in the middle and flash converter on the right. The lack of decoder is ...
KK JKL's user avatar
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2 votes
2 answers
233 views

What is the true measurement duration for each sample made by a DAQ?

When a data acquisition system digitizer (DAQ,) or analog-to-digital converter (ADC) samples a continuous signal, how can one estimate the true measurement duration of the sampling action? By true ...
higgy's user avatar
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3 answers
588 views

Hold violation in clock divider in an FPGA

I have a Verilog design for a Basys 3 in which I display a number increasing by 1 each half second in a 7 segment display. I'm running the timing analysis in Vivado, and I get a hold time violation ...
Martel's user avatar
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Slow ADC to take samples of a fast-changing signal

The context is more or less as follows (this relates to a research project in early stages, so I cannot disclose all the details): I have a signal with potentially very high slew-rate, in the order of ...
Cal-linux's user avatar
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Matlab: spectrum analyzer does not display the output from "Sample and hold block"

I try to use the Sample and Hold function, to show its output on the spectrum analyzer. But it gives me this error "Spectrum cannot be displayed for continuous or infinite sample times", ...
Christianidis Vasilis's user avatar
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Sample and Hold -- Lower Voltage Ignoring Sample Signal

I've built the following sample-and-hold circuit on a breadboard: When I input a larger voltage than is currently stored across C1, the circuit works perfectly; it waits for the Sample signal, at ...
Fluffy the Togekiss's user avatar
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The input buffer of a Sample and Hold

In a Sample and Hold circuit, I know that the buffer amplifier after the capacitor keeps the capacitor from discharging because of its high impedance and causes the output voltage to be equal to the ...
cb_ann's user avatar
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Why this sample and hold circuit does not hold right

I try to test this circuit and I get the following behaviour: a. with MOSFET gate floating the voltage at the input propagates to the output with some delay. b. with 12V on MOSFET gate the voltage at ...
John Am's user avatar
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2 votes
3 answers
226 views

Why is voltage across sampling capacitor going below 0V

I am trying to design a sample and hold circuit for a project, but I am not understanding some of the results for my current simulation. When my control signal (V1) is turned off, the voltage over the ...
uhhhhhhhelp's user avatar
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2 answers
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What is the difference between sampling time and sampling interval and sampling rate?

I understand that ADC sampling time is the ADC clock cycles for which the sample and hold capacitor is charged up to the channel input voltage. This is a configurable parameter and its value ranges ...
Vishwesh GM's user avatar
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1 answer
222 views

Sharing sensor analog output with multiple ADC for digitization

I am using a pressure sensor, MPVZ4006GW6U, and I have an unique requirement where by I need to share this sensor's output with multiple ADC (say ADC128 from TI) for digitization. Each ADC is ...
V V Rao's user avatar
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LTspice peak detector analysis: Time step too small

I made a peak detector with a test file in LTspice. Here is the diagram: When running the test file, I ran into this an error message: Time step too small; time = 0.011, timestep = 1.26068e-017: ...
Josh's user avatar
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Sample and hold & analog shift register

I have this circuit (see first picture.) it's an analog shift register where instead LF386 I use LF398H. This circuit must provide an hyperchaotic behavior for initial conditions x1(0) = l, x2(O) = O....
Julien's user avatar
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3 votes
1 answer
249 views

How to compare Matlab/Theory <=> Cadence: Switched-cap. Integrator: Mag & Phase

I tried to compare the simple switched-capacitor integrator below, between Cadence and Matlab (at the end acting as a simple loop-filter for a delta-sigma). I am stuck now on the point of how to ...
bernd2700's user avatar
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Switched capacitor sample and hold circuit as as mixer

I am trying to find out how important the "hold " level in a sample and hold down-conversion mixer is. If the level is decreased, will it lead to any loss? Out of these three subfigures, ...
RakeshR6's user avatar
1 vote
2 answers
437 views

Saving a voltage with ONLY analog components. Best idea?

I am challenging myself to create an analog voltage storage device. I came up with some ideas and I would like some inputs on what is bests and maybe new ones. Ideally, I could store a voltage in a ...
Markhaus's user avatar
2 votes
1 answer
378 views

Peak hold circuit

I'm testing my peak hold circuit with both LTspice and real one. When inputting a pulse of 500 mV, LTspice gives 800 mV (green one in upper left) as peak hold. However, real circuit, which is designed ...
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1 vote
1 answer
1k views

Calculate number of ADC clock cycles required for sample time

I'm working with a micro, which has a 12-bit ADC. I am using this ADC to sample a 125Hz signal, with a duty cycle that ranges from 0-100. On the rising edge of that PWM signal, the ADC will collect a ...
Birts's user avatar
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Why computers can be modeled as sample and hold system

I was reading digital control system from book by Norman S.Nise and in book it is written that "computers can be modeled as a sample and hold system " Isn't computer is discrete time system ...
user215805's user avatar
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Conditional analog sample and hold (analog override?) - circuit suggestion request

Preamble: I have a LED driven by an opamp-based constant current source (CCS). It works fine, I can set up current required and it is reasonably stable. The problem is, that LED forward voltage drops ...
stiebrs's user avatar
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4 votes
3 answers
436 views

DAC multiplexer glitch

UPDATE 20th May: Swapped the analog output regulator for an AZ1117-EH based on Peter Smith's suggestion, removed C1306, so now the 3.3VA output should be ok at least based on the datasheet. However, ...
Timo's user avatar
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2 votes
1 answer
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Sample and hold circuit giving distorted output

I'm making a sample-and-hold circuit for a 3 bit Flash/Parallel ADC and to allow the conversion to have enough time to happen I want to maintain the input voltage steady for the duration the ...
choco_squirell's user avatar
2 votes
1 answer
282 views

How do these diodes prevent opamp from saturation?

I cannot understand how the clamping diodes prevent opamp from saturation when the switch/FET is off in the following sample-and-hold circuit: I only know that if the negative feed back of an opamp ...
user1999's user avatar
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1 vote
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Data path in logic circuit

In the fig below is the path from CLK of 1st FF to Output(DataOut1) a valid data path. If so why is it not shown? Is it because its just the combination of PATH2 and PATH3? Thanks.
user138602's user avatar
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Buffer requirements for S/H circuits

I am trying to solve question 11.10 which is taken from 2001 GATE IN paper. So I think the answer is (a) because the input buffer which faces the analog input needs a higher slew rate in order to ...
Aditya P's user avatar
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1 vote
1 answer
377 views

Bypass Gate-to-trigger-converter via switching jack

Goal I like to trigger a LF398 Sample-and-Hold IC via a 3.5mm Jack (modular synthesizer). The desired behaviour would be: if a cable is plugged in, incoming signals will be converted to short ...
ato's user avatar
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2 votes
1 answer
151 views

Digital sample and hold synced with a CLK

So I though this should be pretty straightforward, but apparently it's not. Supposed we have a digital async input signal and a CLK. I want to sample the given input signal on every rising (or ...
Jano Rajmond's user avatar
1 vote
2 answers
197 views

Create a pulse that is active from ~0.3 to 0.4 times the clock period

I'm sorry if the phrasing is somewhat weird, but the question is hard to articulate. I've created an IC Sample-and-Hold where I have a hold capacitor at the output. I want to charge this capacitor ...
Henrik Klev's user avatar
0 votes
1 answer
930 views

Acquisition time of sample & hold circuit

What determines the acquisition time of a sample and hold circuit? For example if I had wanted to design a circuit that samples at every 0.1 second intervals what would limit and affect the desired ...
user131618's user avatar
2 votes
1 answer
494 views

Why is my Sample and Hold circuit not working

I have two of these circuits on a board which are both behaving identically. ie. neither is holding a sampled voltage but rather just passing the input directly to the output (indicated as with the ...
Sir Cute's user avatar
3 votes
1 answer
121 views

What will it happened when capacitance is almost the same as parasitic capacitance

I make a sample and hold (IC design),and it is combined with transmission gate and a 550fF capacitor,and my classmate told me that my capacitor is too small,almost the same as the parasitic ...
Shine Sun's user avatar
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0 votes
1 answer
71 views

What kind of wave should i feed the input of sample and hold,which is in the sar adc

There is sample and hold in the sar adc,but i am not sure that i should feed a ramp wave or sine wave to the sample and hold? Are there any relations to sar adc output and sample and hold input wave?
Shine Sun's user avatar
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9 votes
7 answers
4k views

How to achieve analog zero-drift sample and hold for hours?

This so-called "zero drift" opamp droops .001V/sec, at temp 85C with a 1 uF cap. If I'm reading the spec correctly, that's 3.6V/hour! http://www.ti.com/lit/ds/symlink/lf398-n.pdf Is there a method ...
Johny Radio's user avatar
-1 votes
2 answers
71 views

The output change when i connect it with the other circuit

Two symbols are the same sample and hold,so Theoretically their ouput should be the same,but as we see,when i connect it with a comparator,the output of sample and hold totally change. Why?How do i ...
Shine Sun's user avatar
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1 vote
1 answer
293 views

The output buffer of sample and hold

I saw some sample and hold circuits from the Internet,and i find there will be a buffer in the output,so i want to ask what does that buffer do for the sample and hold,can i use two stage amplifier as ...
Shine Sun's user avatar
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0 votes
1 answer
79 views

Analog to digital controller-Sampling rate

One method to design a controller for a digital control system is to first design it in the s domain and then convert it. However, choosing a suitable sampling period is important. In most problems ...
John Katsantas's user avatar
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1 answer
983 views

How can I change the reference voltage and resolution of SAMPLE and HOLD block in LTSpice?

I have a question about LTSpice. I put a Sample & Hold block in a sheet to quantize a continuous sine signal like below: But the resolution is not desired. I have a 16-Bit ADC with a 1v reference ...
user avatar
1 vote
2 answers
115 views

Measuring pulses, options for accumulate samples after trigger

I have a circuit that amplifies pulses and the goal is to measure them with a MCU's ADC in lowest possible power. The pulses width are about 100uS and I am interested about their peak amplitude. Now ...
yo3hcv's user avatar
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4 votes
2 answers
16k views

Track vs sample-and-hold

This is the output of both track-and-hold and sample-and-hold. But when I searched for its circuit I am getting the circuit I have shown below for both. So my question is: if the circuit for sample-...
Swap's user avatar
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1 vote
0 answers
558 views

Sampling analog signal at 100 kHz with raspberry pi

I want to sample a ultrasonic wave at 100 ksps. Currently I am using a Raspberry Pi and an external ADC communicating with each other via I2S at 96 kHz. Since the Raspberry Pi cannot support higher ...
 MegaMind's user avatar
3 votes
2 answers
1k views

Sample & Hold circuit not working for negative half cycle

I have made a Sample & Hold circuit using Multisim but after simulating oscilloscope showing sampled version of input waveform for positive half cycles only. I have used MOSFET as a switch with ...
fahad shaikh's user avatar
0 votes
1 answer
125 views

PSRR - Testing Fixture

I have to design a PSRR test fixture with a 2.4KHz signal imposed on a dc power supply. I can do it using a bias tee at rf but the size of the components at audio confound me. The application is a ...
micropt's user avatar
1 vote
2 answers
365 views

Output of Sample and Hold Circuit

I'm having a bit of a problem figuring out how this sample and hold circuit works. I am to calculate \$V_\text{out}\$ if (a) \$A\$ is infinite and if (b) \$A\$ is finite. \$A\$ is the open-loop gain ...
Kristian's user avatar
1 vote
4 answers
4k views

High Frequency (16 Mhz-48 MHz) Peak Hold/Envelope Detector Circuit?

I'm trying to make a peak hold circuit for a very high frequency bandpass filter that needs to be able to operate at 16 Mhz, 40 Mhz, and 48 Mhz. I've singled out the peak hold part of my overall ...
Brydan Rogers's user avatar
-1 votes
1 answer
718 views

holding nano second pulse amplitude for measuring its amplitude [closed]

My design problem demands me to read the amplitude level of a 10ns pulse, for which I am trying to find multiple techniques that may be helpful. input parameters: ...
kakeh's user avatar
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