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Questions tagged [sdc]

Synopsys Design Constraints (SDC) format is an industry standard to constrain integrated circuits for synthesis, timing, area, power etc.

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How to define SDC constraints for two clock domains fed by single source?

Here is a simplified version of my problem. I have two set of registers as shown. They are operated at different times and there is no path between them. They are clocked by a single clock port. The ...
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36 views

SDC constraints for reusable component

I have a simple register based clock divider component I can drop in when I don't have a spare PLL: ...
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23 views

Can I constrain data output to clock output, or just both relative to internal clock?

I have a small test design in an Altera CycloneIV GX, where I'd like to output data synchronous to a gated clock. AN433 gives a lot of examples, but they all define output path constraints relative ...
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61 views

How to write constraint file for the divided clock in Verilog?

I am using FPGA Basys 3 board in my college, having 100MHZ clock frequency, i divided the default clock (clk) by 216 and got ...
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1answer
64 views

How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized ...
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112 views

How to constrain a clock signal out from a multiplexer

How would you constrain this design? ext_clk and clk_in are asynchronous to each other. clk_div is derived by clk_in with double period. clk_out may be driven by either clk_in and ext_clk, ...
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1answer
305 views

how to get the timing report register to register and input to output in STA?

I'm trying to get the timing report of STA. As I know, basically, there are 4 types of timing paths. Input to register Register to register Register to output Input to output Practically, I want to ...
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1answer
2k views

Get_ports vs Get_pins vs Get_nets vs Get_registers

I am doing a design in vhdl for FPGA. I have a top level design which consists of 3 components: clock divider, Module_1 and Module_2. Top level entity has a clock input port. This clock is divided by ...
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715 views

Writing SDC constraints for asynchronous clocks

I am new to SDC constraints, in synchronous clock definition say A and B are synchronous with each other, then we can define create_clock on A port (input) and <...
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1answer
239 views

Constraining synchronous clocks at different frequencies in VHDL

I have a design with a FPGA, a MCU, and other external peripherals connected together over a parallel peripheral bus. The whole system is clocked from two synchronous clocks. The clocks are a 32 Mhz ...
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1answer
55 views

FPGA proper SDC constraint for hsync pulse

I have a design where video data comes in over the altera altlvds_rx lvds receiver. One of the parallel bits that comes out the other side represents H-Sync which will show up for a few clock cycles ...
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1answer
133 views

MT9M001 to FPGA input timing

MT9M001 is a CMOS image sensor. As its output it provides FRAME_VALID, LINE_VALID and DATA. The output signals are synchronized (edge-aligned) by PIXCLK, which is generated by the sensor. The ...
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890 views

FPGA SDC timing constraints, understanding output delay

I'm having a little bit of trouble understanding the timing convention of an SDC command: ...
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1answer
238 views

how do you know the each parameter values of SDC at the first time?

when we do synthesis with SDC. we should be used with SDC. But I want to know what if you are in situation where the synthesis of yours is the first time, also the company does not even did synthesis ...
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How to use simple generated clock in Verilog Code Vivado 2015.2

I am new to FPGAs. I am using an Artix-7 that comes in the Nexys4DDR, and I am programming in Verilog. I want to create a simple D Flip-Flop that will be triggered by a CLK of 50MHz. The CLK in the ...
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1answer
1k views

Understanding timing constraints

I don't want an introductory text on timing constraints, nor an application note, an user manual, a webinar. I read them all, already, many times. The concept behind timing constraints is very easy. ...
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1answer
751 views

How do you constrain input delay for a multidimenionsal input vector?

I am defining SDC input constraints for synthesis of a small module that is part of a larger ASIC design. I plan to run the module through synthesis using Synopsys tools. A few of the inputs to this ...
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1answer
1k views

Question about function set_dont_touch_network

I was trying to debug a script written for synthesis using Synopsys primetime. Can someone explain me what is the function of set_dont_touch_network? I have these ...
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1answer
533 views

Constraining the reset line

I am using Quartus II to compile my Verilog design, and I'm working to properly constrain my signals. I know how to constrain clocks, for example: ...
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4k views

ASIC timing constraints via SDC: How to correctly specify a multiplexed clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...
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1answer
9k views

ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...
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1answer
223 views

Grouping input and output signals with the corresponding clock

In my Verilog design, I have two asynchronous clocks, clk1 and clk2. Associated with each clock is a bunch of inputs and outputs....
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3answers
466 views

Timings constrains for isochronous clocks

In my Verilog design, I have two clocks of the same frequency, but of different phase. At the moment, my timing constraints look like this: ...
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4answers
4k views

timing constraint for bus synchronizer circuits

I've a bus synchronizer circuit for passing a wide register across clock domains. I'll provide a simplified description, omitting asynchronous reset logic. The data is generated on one clock. ...