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Questions tagged [sdram]

SDRAM stands for synchronous dynamic random access memory. Being synchronous it relies on a separate clock signal for moving commands and data to/from the device.

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connect Micron SDRAM to STM32H7 FMC but what should I do with DQM pin?

I plan to connect SDRAM from MICRON MT48LC series ( datasheet. The pin connection diagram is automatic generate by STM32CubeMX ( STM32H743 ). The setting is an 8-bit data bus, a 13-bit address, 4 ...
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How can a 11 bit address bus access 1M memory locations?

According to this datasheet of a SDRAM module it has 2 banks of 524,288 memory locations, but only a 11 bit (\$2^{11}=2,048\$) address bus. How can an address bus with only 11 bits access all those ...
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Strange SDRAM Behaviour

i try to use the SDRAM on my DE0 Board. This is the chip: http://zentel-europe.com/datasheets/A3V64S40GTP_v1.3_Zentel.pdf Basically my driver works. i save the value of an upcounted signal in the ...
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DRAM in a FPGA - Image Sensor design

I am designing the simplest form of a camera: an FPGA that interfaces an image sensor and sends the acquired data to the host device via USB 3.0. There is no processing on the FPGA, it is used for ...
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When do we actually need bank interleaving?

Since common DRAM chips support burst transfer and hardware page size (row size) in a bank is quite large, we can amortize the charging & activating time over bytes in a long burst transfer. I ...
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640 views

STM32H7 with 512MB SDRAM

I'm considering to design an audio processor based on the STM32H7. I want to experiment with MCU-based DSP instead of using a dedicated DSP. I chose this high-end ARM MCU to have ample headroom for ...
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158 views

STM32F429i LTDC + SDRAM Buffer Issue

I have been trying to learn the basics of STM32 LTDC peripheral to drive a 4.3" 480 x 272 LCD using STM32F429IG mcu. I am using the Open429i dev kit by Wavehshare (https://www.waveshare.com/core429i....
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SDRAM: Why CAS latency is configurable

I've seen a couple of very similar questions but the answers don't answer my question: DDR2 CAS Latency - is it fixed to clock-cycles or time? What limits the lower bound of DRAM CAS latency In my ...
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80 views

How to determine phase shift for clock being generated for SDRAM connected to FPGA?

In the reference designs for a few FPGA development boards, I have observed that, there is always a PLL which generates two clocks at the same frequency but not in phase. One clock feeds to the SDRAM ...
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38 views

DRAM write operation

In a typical read operation from a dram chip, all the banks are equipped with sense amplifiers which select one bit from each bank using column multiplexer. But how does write operation takes place? ...
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For the first prototype, how many pieces are necessary? Includes 256BGA, SMA, SDRAM

I'll most likely need to re-run. For the first batch of prototype, what is the safest number? Ordered 10pcs of PCBs and ordered 10x components.
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How to find a design house with dynamic memory device support? [closed]

I am looking for a design house with dynamic memory device support. Design houses, I found on the web, support only analog, mixed-signal, high-voltage designs and so. I found no design house with ...
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DRAM memory organisation

I've been trying to understand the working of DRAM chips but apparently in a lot of confusion. Suppose there are 8 banks in a single chip on a module. Is it only one bit that comes out of a single ...
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What is tDPL in SDRAM timing and how is it violated?

The datasheet describes the tDPL as "Input Data To Precharge" time. However, it does not show it on any timing diagram. With an SDRAM controller I am getting this error: "tDPL violation during ...
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Chip select relation with input capacitance of SDRAM

I am interfacing 4 SDRAM's with MPC8270 processor and there datelines are shared, but processor is selecting particular RAM with help of CS (Chip Select). My question is when one SDRAM is selected ...
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485 views

SDRAM structure for Cortex-M7

I'm looking into designing a custom board based on a Microchip / ATMEL SAM S70 or STM32F7 / STM32H7. The SAMS S70 appears to be the cheapest option and offers roughly the same as the ST competitors. ...
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252 views

STM32F429ZIT6 with SDRAM IS42S16320F Read/Write Issue

I designed a board which is containing two SDRAM (IS42S16320F) and STM32F476ZIT6 MCU (and other components also). I can access the SDRAM but the data is changing independently from the code. My board ...
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Erasing SRAM in STM32L071RZT6 MCU

I am new to MCU programming, I use STM32, C language, IAR IDE, HAL. I need to erase SRAM of the MCU STM32L071RZT6 when the "Erase" button is clicked. How can it be done? Will it cause app crash? Can <...
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209 views

Is designing SDR SDRAM controller a difficult task? [closed]

My book says "Because of many possible modes and options of SDRAM, designing a comprehensiveand robust SDRAM controller is an involved and tedious task". Don't SDR SDRAMs follow some specific standard ...
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195 views

CPU-Multiplier Overclocking causing (silent) data corruption?

There have been a large number of threads regarding CPU overclocking and damage to electrical components in the past. Mostly, however, these questions were directed at how increased voltage and the ...
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99 views

Why is the WL charged at Vccp for DRAM cell?

Qouting from Dynamic random-access memory - Wikipedia Reading or writing a logic one requires the wordline is driven to a voltage greater than the sum of VCC and the access transistor's threshold ...
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273 views

Using a high frequency LPDDR3 RAM with a lower RAM frequency supported Processor

I'm designing a board with Allwinner A64 processor and i'm confused in choosing the proper RAM. the SDRAM controller characteristics of the processor is listed as follows: Compatible with JEDEC ...
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Electrical principle of row hammer glitch

There is a fairly new and exploitable bug happening in some DDR3 DRAMs called the "row hammer" in which it's possible to bit flip memory cells. I understand how the exploit works, but not the ...
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Understanding DDRn SDRAM

So I am basically trying to grasp/confirm my grasp of SDRAM and DDR. So basically I understand that there is going to be some chips each with up to 8 banks (so kinda like 8 chips internally?). For ...
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330 views

How to see the content of the SDRAM in my DE1-SOC while running (JTAG Altera cable)?

I have made a simple design in Quartus Prime, in verilog code, not using megawizard, but directly accessing the pins of the SDRAM. I am saving 2 x 16 bits binary numbers on 3 of the 4 banks of the ...
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211 views

Back-to-Back Full Page Burst Reads from SDRAM

I am designing a microcontroller-based video system, and I am considering using SDRAM (~100MHz) for external frame buffer memory. (My microcontroller has plenty of I/O for the data and address busses ...
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177 views

What makes PC SDRAM so much more expensive than the same capacity in a chip?

I'm picking a SDRAM IC for a custom embedded board and was surprised by the low prices. Was expecting orders of magnitude similar to PC ram of the same capacity. For example H5TC8G63AMR-PBA chip ...
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133 views

Multiple SDRAM modules vs single IC / Latency relevance

I'm designing a board with a ARM Cortex processor (TI Sitara). It needs an external RAM module, and I have never really worked with embedded SDRAM modules in circuit design. Looking at the schematic ...
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108 views

SDRAM timing confusion

I'm looking at this data sheet: T67M-512Mb-Mobile-Lpddr-Sdram (targeting speed grade -75) and trying to understand the timing requirements for performing a read, specifically when to sample the DQ ...
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248 views

SDRAM interfacing problem with lpc4357

I am trying to interface SDRAM - AS4C8M16SA from Alliance, with LPC4357 (LQFP208 package). I'm not familiar with EMC or SDRAM. I got the RAM get initialized. But ,I cannot successfully write beyond 64 ...
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817 views

Difference between VDD-VSS and VDDQ-VSSQ pin pairs for SDRAM ICs

I am referring to Micron MT46V16M16CY-5B IT:M DDR SDRAM. In its datasheet, I see two different set of pins, VDD-VSS and VDDQ-VSSQ. What is the difference between them? The datasheet suggests that ...
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170 views

can high speed memory interfaces like GDDR5 or XDR ever become mainstream?

Given the limited memory on GPUs, I'm wondering why there are no socketed GDDR5 memory modules so that you can install more RAM. The main challenge seems to be maintaining signal integrity since ...
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193 views

Microcontroller and SDRAM

I have a project where i need to run a python script on a microcontroller. The python script is basically a GUI based script using pyQt and the internal ram of a microcontroller isn't enough. After ...
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59 views

How to calculate how much data a Core 2 duo E8 can write to the RAM per second? [closed]

I'd like to know how exactly I could calculate how much data the Core 2 duo E8 can write to the RAM per second, given that it is not overclocked and the RAM is 333MHz-DDR3?
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670 views

DDR4 frequency decrease if populated with more than one module per channel

I'm curious how one particular company Gigabyte ensures its server motherboards to run at the maximum supported memory frequency even when there're two or three DIMMs per channel (of coure we're ...
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Why DRAM costs much more than flash memory?

Comparing prices at a local store, I calculated prices 0.36 USD/GB for SSD NAND flash memory and 5.41 USD/GB for DRAM memory. The difference is 15 times. Why so big difference? Both are semiconductor ...
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Is DQM latency during READ always two cycle and independent from CL in SDR SDRAM?

Reading SDR SDRAM datasheets, i found (and had been surprised) that during READs (with Burst Length >=2) DQM latency is always two cycles. That statement is given explicitly at least in one datasheet ...
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81 views

Is memory bandwidth advertised for DRAM (like 12800 MB/s for PC-12800) ever achievable?

Memory bandwidth for DRAM like DDR3-1600 / PC-12800 is a function (product) of memory frequency (1600 MHz) and memory bus characteristics (width and number of channels). But memory also has timings (...
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2answers
2k views

LTDC data starvation during simultaneous SD-RAM and NOR Flash access with STM32F429 rev 3

Application details: SDRAM is used as the LCD frame buffer. Memory for 2 LCD frame buffers are allocated(double buffering) in SDRAM. LTDC will be always accessing one of the frame buffer in the ...
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1answer
2k views

Loading and displaying on VGA monitor a Background image in DE2-115's SDRAM

I would like to load a background image which I currently have saved as a .bmp into the DE2-115's SDRAM. I would then like to display this background image on a VGA-monitor (640x480). I will then be ...
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1answer
363 views

DRAM - is data pins order important when routing on PCB?

Quick question: I have SDRAM (SDR) and trying to connect it to uC. Can I route data bits from SDRAM to uC in any order? So they aren't connected respectively (d0->d0, d1->d2 ... d15->d15) but in any ...
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1answer
855 views

How does a flip-flop circuit keep it state?

When reading about the difference between SDRAM and SRAM (electronically), I understand that SDRAM requires the dynamically charging of the capacitors to maintain their states. I do not get how SRAM ...
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1answer
1k views

Can this SDRAM be used with STM32F7?

I have STM32F7 (which has a Flexible Memory Controller capable of interfacing SDRAMs) and I want someone to check if it is able to interface this SDRAM - IS42S32800D (http://www.farnell.com/datasheets/...
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Building a SDRAM Controller (VHDL)

I am using the Spartan SP601 Evaluation Board, which includes 1 GB Elpida EDE1116ACBG-8E-E SDRAM. I would like to build a RAM controller, but have no experience in working with RAM before. I largely ...
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Why DDR3 RAS timing have to be greater than RCD + CAS timing?

By definition, tRAS is the minimum delay from when a particular row in a bank is activated, to when it can be closed with a PRE command. I have seen claims numerous times that tRAS should be > tRCD + ...
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147 views

DDR3 bank activation

I've been trying to follow: http://www.anandtech.com/show/3851/everything-you-always-wanted-to-know-about-sdram-memory-but-were-afraid-to-ask/3 On this page, they say: "Following activation, the open ...
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196 views

What are the meanings of the fields of this cache memory?

I have a cache memory simulator with this cache memory shown. The cache size is 64 bytes and the block size is 8 bytes. What is the decomposition into fields? If block size is 8 bytes, then log(2^3)=...
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1k views

Why DIMM has 64 bit data width?

Wikipedia’s definition of DIMM says: Most DIMMs are built using "×4" ("by four") or "×8" ("by eight") memory chips with nine chips per side; "×4" and "×8" refer to the data width of the DRAM chips in ...
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5k views

In an SDRAM how do address rows/columns and rank width and bank width relate to the total memory size?

I have a Micron SDRAM (MT16KTF1G64HZ-8GB). The size of the memory is 8GB. I did some calucaltions and 8GB of data means 2^36 bits capacity. Now when I look in the Micron data sheet, the row address is ...
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805 views

Building a framebuffer

I'm trying to build a framebuffer using an FPGA and an external memory. I have a soft core CPU running on the FPGA as well a small chunk of logic to output signals to an LCD. My goal is to have the ...