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Questions tagged [sdram]

SDRAM stands for synchronous dynamic random access memory. Being synchronous it relies on a separate clock signal for moving commands and data to/from the device.

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Stabilizing ODELAY_VALUE related to IODELAY2 module in Spartan6 SLX9 FPGA Design for SDRAM Interface

I'm working on an FPGA design for the Spartan6 SLX9, which includes a memory controller for off-chip Micron SDRAM. To introduce a delay on the clock signal to the SDRAM relative to the Data/Command ...
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STM32 - LTDC + DMA2D flickering and banding

I'm currently using an STM32H753 with 16bit SDRAM (IS42S16800F) to store an RGB565 buffer, with LTDC driving an 800x480 LCD. I'm using double-buffering, flipping the buffers in the LTDC vsync ...
Triforcer's user avatar
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How are oscilloscopes able to fill DDR SDRAM memory without interruptions from memory refresh?

From the many teardown videos, it is clear that modern oscilloscopes mostly use DDR memory. But this memory needs to be refreshed periodically. Which should interrupt the data stream. I understand ...
Dmitry's user avatar
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What is the DDR4/5 Colum-to-Column access latency for within bank access

Since DDR4, the banks are divided into bank-groups, where Column-to-Column delay (CCD) for accessing in different bank-groups is lower (tCCD_s) than than of accessing bank-to-bank within a bank-group (...
Kraken's user avatar
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3 votes
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SDRAM logic makes noise on ADC readings with FPGA

I am working on a design in which an FGPA reads the output of a 12-bit 40MHz ADC and then stores half of the data on an external SDRAM and the other half on an on-chip BRAM after some averaging. The ...
Farzin's user avatar
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DDR2 SDRAM with the Lattice ECP5

I have a FPGA design that requires some memory. I'd really like to use DDR2 because of cost and speed reasons. I'd be running it at its lowest allowed frequency of 125MHz. Now the ECP5 has some IP ...
dinocroc123's user avatar
7 votes
3 answers
1k views

Decoupling capacitors where VDD/VSS pins are spaced apart

On previous PCBs I've laid out, I've always been able to place decoupling capacitors easily due to VDD/VSS pairs being close together. However, I'm now working on a design that's using a chip (ISSI ...
Triforcer's user avatar
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Implementing DDR In/Out DQ Pin for DDR3 SDRAM on Xilinx Spartan-6 FPGA

I’m currently working on a project that involves interfacing a DDR SDRAM (Micron MT41J128M16) with a Xilinx Spartan-6 FPGA. I have implemented a controller. I’m looking for guidance on how to properly ...
Md.shah's user avatar
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Confused about STM32 FMC pins for SDRAM

Context: I am currently working on a design that is centered around the STM32H723ZGEI6. I chose to opt for 32MB of external RAM via the IS42S16160J SDRAM IC. However, I am having some trouble figuring ...
BlueOyster's user avatar
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Calculating timing constraings for interfacing with sdram

I want to set the set_input_delay and set_output_delay constraints for my design but I'm having trouble to find the values to calculate them. My understanding so far: To calculate the set_output_delay ...
TimSch's user avatar
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SDRAM and I2S on STM32

I am using an STM32F429 discovery board to develop a DSP platform for making some sound effects. I have I2S streaming and passing through, and I have SDRAM configured where I can talk to it and even ...
Adam's user avatar
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FPGA and SDRAM noise impact on ADC input

I'm using an FPGA to get data from an ADC and save them on SDRAM, the SDRAM works with 100 MHz and the ADC works with a 40 MHz clock so I use a clock IPCORE to generate them from my 50 MHz oscillator ...
Md.shah's user avatar
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SDRAM Voltage and pin planner consequences

I have this SDRAM module: According to the docs: am I right that it's the 3,3V version? If yes: what are the consequences of that fact using the Pin Planner? Is it correct that I have to set the I/O ...
TimSch's user avatar
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2 votes
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Understanding "Key Timing Parameters" of SDRAM datasheet

I'm currently trying to understand SDRAMs at the example of the iS42/45S16320d and the DE10-lite board. At the beginning of the sheet you can find a table "Key Timing Parameters" that ...
TimSch's user avatar
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Timing constraints vs. NOP in timing diagram of IS42S16320D SDRAM

I'm working with an FPGA that works at 50MHz and the IS42S16320D SDRAM. The datasheet of the RAM assumes a clock of at least 100MHz. Given the following timing diagram: The $t_RCD$ is 18ns which ...
TimSch's user avatar
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Difference between burst and no burst for I/O on the same row

I'm currently working on SDRAM in general and the IS42S16320D in particular. My understandings until now: Before reading or writing to another row you have to precharge row A and activate row B You ...
TimSch's user avatar
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Why is there a tRRD in DDR3? There does not seem to be a resource conflict between different banks

In DDR3, bank activation is specific to the Bank, for different banks, they all have their own sense amp and do not seem to affect each other, so why would there be tRRD?
LurenAA's user avatar
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Occasional Data Corruption in the external SDRAM in STM32F429

I run an application with stm32f429zg using freertos. An external 8Mb SDRAM from winbond (W9864G6KH-6) is used with fmc protocol. I set timing settings in stm32cubemx based on the sdram datasheet ...
ElectroBehrad's user avatar
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1 answer
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How does DDR SDRAM increase the bandwidth without increasing the frequency at which a memory array operates?

I am reading about SDRAM, and how the bandwidth was increased with DDR optimizations. From my understanding DDR can send data at a rising and falling edge, effectively doubling the data being sent. ...
Diogo Landau's user avatar
4 votes
1 answer
147 views

Debuging verilog SDRAM controller

I've been working on a project that involves the creation of a SDRAM Controller in verilog for an Altera DE2 prototyping board. Despite reading the documentation for the memory chip on the board, ...
bieux's user avatar
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STM32H750IBK6 SDRAM FMC CLK maximum frequency

In the STM32H750IBK6 REV V, what is the maximum FMC_CLK to run SDRAM? The datasheet has two different values (for the rev V and rev Y IC revisions). What is the safe area of operating FMC CLK with ...
Sagar Sagare's user avatar
3 votes
0 answers
47 views

How to verify if SDRAM alternative is a direct drop in replacement?

I'm trying to verify whether the two SDRAM chips are complete drop in replacements of each other. I've verified the footprint, electrical characteristics and various timing parameters (namely CL, tRCD,...
goofson's user avatar
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3 votes
1 answer
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In DRAM, why does the precharge operation come after the activate operation and not vice-versa?

Precharging sets the bit line voltage is set to Vdd/2. To read from a dynamic memory cell, the bit line voltage must be near Vdd/2 for the sense amplifier to amplify the data value correctly. Since ...
jayded-bee's user avatar
5 votes
1 answer
1k views

Is my understanding of DRAM memory array topology in relation to "rows" and "columns" correct?

Assume a x16 DDR SDRAM module with 2b banks, which are made of 2r rows, which are further composed of 2c columns, where each column is 2w bits "tall". Assume that the interface is burst-...
jayded-bee's user avatar
1 vote
1 answer
198 views

DDR4/DDR3 CK and CK# speed ans CLK speek

I am reading the DDR4 specification from Micron but cannot get around one thing: When you buy RAM and it says DDR4-3200MHz, does it refer to the speed of CK and CK# pins? I think this is not referring ...
Weijie Chen's user avatar
1 vote
0 answers
58 views

How to address 4x SDRAM chips with only two CS signals exposed on edge connector?

I'm trying to build a system to test memory modules built around 512 Mbit SDRAM chips by reading/writing to chips individually. As you can see in the attached schematic, CS0 and CS1 are shared between ...
Embedded Music's user avatar
1 vote
1 answer
202 views

Streaming image data to SD card using 8-bit data width SDRAM and DCMI peripheral on STM32F446ZCH6

I am currently working on an application involving streaming 480p/720p video from an OV5640 camera to an SD card (using SDIO) but I am afraid that the 128Kb of available SRAM are not enough. Given the ...
Kozma's user avatar
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2 votes
2 answers
597 views

FPGA to SDRAM communication

I am working with a DE0-nano board, on which is a Cyclone IV EP4CE22F17C6 FPGA, connected to an ISSI IS42S16160G-7TLI 16Mx16 SDRAM chip. In order to setup the communication between the FPGA, I've ...
Jambon's user avatar
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13 votes
1 answer
2k views

Why was full page bursting removed when we moved to DDR

I'm interfacing with SDRAM on an FPGA and full page bursts are a godsend for streaming data. It's seems to be much, much more handy then a fixed burst size. I know it was removed when we moved to DDR. ...
John Smith's user avatar
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80 views

For SDRAM, how to tell how many ranks supported in each channel?

This is from Wiki: As an example, take an i945 memory controller with four Kingston KHX6400D2/1G memory modules, where each module has a capacity of 1 GiB. Kingston describes each module as composed ...
neoserdes's user avatar
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158 views

For HBM memory READ operation, why odd bytes driven earlier than even bytes?

As the valid data coming out at the same time, why odd bytes data I/O are driven "D" 1 CK earlier? thanks!
neoserdes's user avatar
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1 answer
133 views

What is the definition of power down in HBM memory?

Reading the datasheets, it says data still needs to be maintained during power down and thus controller can't keep a channel in power down longer than the defined refresh requirement of the DRAM. ...
neoserdes's user avatar
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Help needed with determining PCB trace termination for µC/SDRAM interface

I am trying to figure out whether I need termination resistors for my PCB routing between a µ-Controller and an SDRAM (IS42S32800J-6BLI) that I plan to clock at 166 MHz. According to Table 72 of ST's ...
Hansel's user avatar
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1 answer
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LPDDR on separate replaceable modules / boards - possible? drawbacks?

I've read that LPDDR is more efficient in active states and times more energy efficient than DDR in inactive states, e.g. in Performance vs power in off-chip DDR SDRAM, there is a mentioning of ...
Martian2020's user avatar
0 votes
1 answer
387 views

How is a read of SDRAM done?

A SDRAM module is divided into chips. And those chips into banks. Banks can have different row and column lengths. When reading a given address, I feed the address to the memory specifying the address ...
Franks's user avatar
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1 answer
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Why SDRAM1 and SDRAM2 have the same pins on STM32

can someone please help me, why do when i use SDRAM1 and then add SDRAM2 the data and address pins are the same but only the chip enalbe. does this mean that all pins even the Data pins DQ can be ...
Majdgh's user avatar
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2 votes
1 answer
214 views

How does Asynchronous DRAM perform self-timing

The original question was deemed lack of focus. This post is specifically about dram chip. When DRAM controller talks to an asynchronous DRAM, how does DRAM itself know when a write is completed and ...
Oliver Young's user avatar
0 votes
1 answer
110 views

Why would adding header cables solve any problems?

I was trying to debug an FPGA to external SDRAM connection and I found that connecting cables to the pins of the address bus fixes the interface in some way. I want to know how/why. Things I'm pretty ...
fertilebean's user avatar
2 votes
1 answer
236 views

DDR3 DQS "preamble"

I'm building a small testbench for a DDR3 memory controller and would like to verify that my unterstanding of DQS and DQ sampling points is correct. The line state before the transmission is undefined ...
Simon Richter's user avatar
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1 answer
179 views

SDRAM full page burst mode stoping

I'm working on an SDRAM controller to handle a frame buffer. I want to know, Is it possible to terminate a full-page burst mode by a PRECHARGE command? Although a <...
HamidReza's user avatar
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1 answer
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Why is CAS latency mostly recognized in DRAM timing?

From what I know, it takes roughly these steps to read DRAM data: Enable RAS signal, send the row address Wait for some Time(tRCD), then enable CAS signal, send ...
user239216's user avatar
2 votes
1 answer
261 views

sdr sdram full page burst and auto refresh

I'm designing a simple SDRAM controller for fun and want to implement support for full page bursts. To do this I have been looking at datasheets of a few SDRAM ics that I have laying around on FPGA ...
John Smith's user avatar
1 vote
1 answer
433 views

STM32F469 FMC Memory Mapping Inconsistency

I'm learning ropes with STM32 and everything was going pretty well until... I have STM32F469i-Discovery (Touch DSI 800x480, SDRAM, QSPI Flash etc.) Have ton of docs - datasheets, manuals, PCB ...
Ilya's user avatar
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1 vote
0 answers
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STM32F469 with AS4C4M32S SDRAM only able to write first byte

I have made a custom board that features a STM32F469NI MCU coupled with AS4C4M32S SDRAM. Following are the SDRAM timing and register set information: ...
Ankit Sharma's user avatar
0 votes
2 answers
1k views

Do all SDRAM applications require high-speed routing?

I am a chemistry student and I am beginning to realize that I have fallen into a EE rabbit hole.. I am trying to create a PCB (digital audio delay unit) from a schematic which includes a SDRAM, this ...
J.Doe's user avatar
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1 answer
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Expected SDRAM access speeds?

I would like to get an idea of how fast SDRAM accesses should be. If I have a 32-bit ARM based processor running at 500MHz accessing an SDR sdram device clocked at 166MHz, what sort of read/write ...
Ronnie Shipman's user avatar
1 vote
1 answer
206 views

DDRx JEDEC Standard: Retention Time

Different scientific publications [1,2] mention that DDRx memory has a (data) retention time of 64 ms while on average each cell is refreshed every 7.8 us (tREFI). I want to know where this ...
Patrick's user avatar
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6 votes
4 answers
2k views

Interfacing ADC Output with SDRAM

I am working on a design for a high-speed data acquisition device for a 10-bit ADC signal at 80 Msps. So far, it looks like most MCU boards are too slow to be able to route and store data and keep up ...
scpaulson42's user avatar
1 vote
2 answers
129 views

Do bank/rows/columns based NOR flash memory exist?

SDRAM supports more addresses than their address bus width allows thanks to the bank/row/column scheme it's based on. My question is if there are non volatile parallel memories that are based on the ...
BamsBamx's user avatar
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1 answer
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External SDRAM with Blackfin and FreeRTOS

I have a custom board with Blackfin DSP and External SDRAM 64 MB and FreeRTOS. Reading from SDRAM using task with priority 6. In a test I read about 20000 words. Each word is twice consecutively, some ...
Adam's user avatar
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