Questions tagged [semiconductor-process-technology]
The semiconductor-process-technology tag has no usage guidance.
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Is there a CMOS-based analog compute chip that uses hybrid technology nodes? (e.g. 14 nm for digital part such as SRAM and 28 nm for analog part)
In CMOS-based analog computing, there always are mixture of analog and digital parts.
For example, the computation is performed in analog domain and the storage of on-chip data in performed in digital ...
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Why do JFET use buried channels?
All sketches of JFET construction that provide an actual 3D impression suggest that the channel is buried, e.g. here.
I imagine that the formation of such a channel geometry requires at least two ...
- 19.6k
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Suggested Configuration of Sputtering System?
hopefully this is in the right section, a lot of electrical engineers work in semiconductors. I have an old hummer II desktop sputter coater I am trying to make use of. The documentation of something ...
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Calculating oxide thickness from Dry/Wet oxidation of <100> Silicon
I have an assignment question which I have completed but the answer does not look correct to me and I am trying to figure out where it is going wrong.
The question is as follows :
A lightly doped <...
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How does one manufacture a P-N junction?
When I read a physics textbook about a P-N junction, it will tell me that you connect a p-doped semiconductor to an n-doped semiconductor, and you form a depletion region.
However, from what I know ...
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Custom semiconductor processes with 3rd party foundry
There's foundries with established processes which give you a process kit to simulate things like transistors etc.
But suppose someone wanted to develop a custom imaging sensor which requires ...
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What are the ways in which semiconductor-grade neon is critical for manufacturing?
This is a question about material use specifically in semiconductor manufacturing.
CNN's Ukraine halts half of world's neon output for chips, clouding outlook begins:
Ukraine's two leading suppliers ...
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OpenLane .gds file simulation/verification
Is there any way/software to simulate a .gds file.
I know this file is only a geometry file so it doesn't really contain any information about the physical connections between stuff, it only seems to ...
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Ambiguity of the "intrinsic" layer in a PIN diode
I'm having trouble understanding the fundamental makeup of large PIN diodes, specifically those used in radiation detection devices. For example, high purity germanium (HPGe) detectors are often ...
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What is the current state of the art design rule for SiC VLSI? Technological impediments to making a SiC microcontroller for a Venus lander at 460 °C?
A sub-discussion below Is there any demonstrated or even proposed technology that can sterilize a spacecraft with 100% certainty and yet leave it electronically functional? in Space Exploration SE ...
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Why do silicon wafers look rainbow colored?
. Image taken from Can somebody identify this 12" silicon wafer?
So this silicon wafer looks multicolored (and beautiful). But how does it get multicolored like a rainbow? What is the reason for ...
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Is there any specific application for an indirect band gap semiconductor?
I know that direct band gap semiconductors are very attractive for optical emission, and even though indirect band gap are used as well, I keep wondering: is there any technology that specifically ...
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How is the asymmetry of a Schottky diode obtained?
A Schottky diode is constructed with two metal conductors bonded to a doped semiconductor. One of the metal-semiconductor junctions is a Schottky contact, and the other metal-semiconductor junction is ...
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Can drain and source length be smaller than minimum channel length in CMOS technology?
I know the channel width can't be smaller, but what about drain and source? Say, in 0.18u technology, what would be a typical drain/source length?
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Feature 'logo/labels' on cases of self made devices
Not really an electronics question however has something to do with the tech you have used for your own projects. For example, on any consumer device with USB support, Bluetooth, HDMI 2.x etc there is ...
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When Intel / AMD choose their Nanometer Processes, why were the specific numbers, 5, 7, 10, 14, 22, 32, 45, etc chosen?
When looking at the roadmaps for the CPU manufacturing process
https://wccftech.com/intel-expects-launch-10nm-2017/
Semiconductor Process Technology
Year
10 µm
1971
6 µm
1974
3 µm
1977
1.5 µm
...
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Difference between Logic Chip and Memory Chip front-end manufacturing process?
I understand that memory chips like DRAM Chips require a little different set of Front-end setup than logics chips. However, I am not finding anywhere how the actual manufacturing steps differ, ...
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Does frequency scale proportionally?
Suppose that I am working with an FPGA and I synthesize two architectures A and B. A achieves a maximum frequency of 60 MHz on FPGA and B achieves 50 MHz on the same FPGA. Now suppose that I ...
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Is it possible to have a non-integer multiple of minimum length in MOSFET technology?
I need to design an OTA with 0.25 \$\mu m\$ CMOS technology. Can I choose to have a transistor with a channel length of 0.60 \$\mu m\$? I don't know if 0.25 is the resolution of our technology process ...
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What is the actual cmos technology node of China and Russia not licensing major process technology from outside?
There are a number of Russian fabs but from what I can see they are just using liscened technology ie Sitronics using STmicroelectronics at 90nm node or Angstrem-T using AMD see yet in the past there ...
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Are 7nm or 10nm transistors reality or is it just a marketing strategy by processor manufacturers?
Now a days chip manufacturers, like Qualcomm, claim that they have built a 7nm chip. Is 7nm really the size of transistor or is it just a marketing strategy? If 7nm is just for marketing and not the ...
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