# Questions tagged [sequence-detector]

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### Why does it take 2 clock cycles to move to the RESET state in my state machine?

I'm writing a finite sequence encoder in Verilog. Basically, an output Z will be activated if the input W is on for at least four clock cycles, or if its off for at least 4 clock cycles. See the ...
284 views

### Design a sequence detector to detect 1001 or 11

I want to draw a state diagram about the sequence detector circuit. The circuit will generate a logic “1” output is a sequence of 11 or 1001 is received. I have my answer, but I don't know my answer ...
187 views

### FSM sequence detector in Verilog

I'm designing a finite state machine (FSM) to detect the sequence "10001" in Verilog. I'm having a similar problem to that described in this question in that my FSM does not tick when the sequence ...
121 views

### How to verify if all 3 AC phases are in order? [closed]

We have 220V main lines where we currently live and we have a 3-Phase connection. We have an Air conditioning unit that requires 3 phase AC input with the correct phase sequence. If the phase ...
97 views

### Designing a Moore sequence detector

Does anyone know if the circuit design that I've drawn as shown below correct? It is a Moore sequence detector for sequence 1001. Thanks!
1k views

### sequence detection, why use SM?

The accepted way for implementing a sequence detector is with a state machine. why implement a SM when (it seems) any sequence detector can be implemented with logic demonstrated below (ASIC and FPGA) ...
457 views

### '11' sequence detector systemverilog

I wrote a program for a '11' sequence detector to be implemented by both Moore and Mealy machine. The problem statement is for z to be asserted high after x has been high for 2 cycles. I've attached ...
2k views

### Designing a sequence detector(0110)

I asked to design a sequence detector to detect 0110 and when this sequence happend turn it's output to 1 for 2 clock cycles. Here is what I designed: But the problem is it turns the output to 1, ...
265 views

### Sequence Detector with multiple inputs

The question: Design an automaton that receives inputs X0, X1 and produces outputs Z0, Z1. Z0 is 1 If the last two bits of X0 are the complement of the last two received on X1. Z1 is 1 If in the ...
2k views

### How do I implement a sequence generator using a universal shift register?

How can I implement a sequence generator that generates the following sequence 0000 1000 0001 0011 0110 1101 1110 1111 using a universal shift register? The shift register I need to use is the 74LS194 ...
261 views

### What is a recycling counting sequence?

Is there any difference between the name "recycling count sequence" and "count sequence"? I have a digital system book saying that a MOD-12 counter has a recycling count sequence of 0001 through 1100....
698 views

### Correct representation of 1011 mealy state machine?

I have a little confusion i want to detect 1011 in my mealy state machine. the correct graph is shown below. My Confusion is what would happen if i stay at state S3 instead of going to s1 when i get ...
227 views

### Does my Sequence Recognizer detects this pattern?

Question: build a circuit detects the two sequences 0101, and 1010 (maximum possible overlap of 1 bit). The circuit has one input X (received), It also has a active-low asynchronous reset and clock ...
61 views

### Detector of a 1 followed by 1 in a sequence of 0s

I need to design a digital circuit that detects when a sequence of 0s does NOT contain a 1 followed by 1 (or more). Example: 00000000010001000000000 Output: 1 00000011000000010000000 Output: 0 I ...
333 views

### Finite State Machine (FSM) bit sequence detector for a stream of several bits [closed]

Typically, drawing out a FSM is the solution to this problem. However, my question here is its implementation. I thought of two ways but i am not sure if they were correct. typical FSM, truth table ...
2k views

### Sequential counter for repeating counting sequence

I'm aware of designing synchronous counter design for a counting sequence where I write the state table with present and next state and then followed by flip flop inputs (filled using the excitation ...
192 views

### BLDC controller

I have to design a controller for three phase BLDC motor. In BLDC motor, for each hall sensor signal combination we have to to energize two sets of stator phases. But how to correctly identify which ...
724 views

### ASM chart to circuit

is there any systematic way of trasforming an ASM chart to a sequential circuit immediately? I mean, given that the 'State Block' can be represented by a D flip-flop; 'Decision Block' is equivalent to ...
107 views

### Floating Collector

I am working on a project where power to the 5VDC supply to a micro can be interrupted during operation (by user). I need to signify to the micro that it is about to lose power so it can perform ...
6k views

### Moore “01010” sequence detector

My task is to design Moore sequence detector. As my teacher said, my graph is okay. I wrote down next states, and outputs, then decided which flip-flops I'll use. With Karnaugh tables, I miminalized ...
548 views

### how to design a pattern detector state machine in vhdl [closed]

How can I use vhdl to design a sequence detector to find a 32bit sequence with 15 zeros followed by 17 ones by using 2 counters to count ones and zeros that have enable and reset signals. Can anybody ...
400 views

### Designing a Sequence detector

The problem statement is not exactly on synthesizing circuit but in one of the interim steps that I am trying to learn. Problem Statement. 1) In order to design a sequence detector in Verilog (...
852 views

### Designing a State Machine

Question: Design a state machine that would output the sequence 0 1 7 1 and then 1 7 1 1 7 1 and so on. A reset will make the machine go to the which outputs 0? What I've managed to do so far: Since ...