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Questions tagged [sequential-logic]

A digital logic circuit containing feedback, in which outputs depend not only on present values of inputs but also on past values. Sequential logic is used to implement state. Contrast with "combinatorial logic", where outputs depend only on present values of inputs, and there is no feedback.

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32 views

Need help making a counter controlled by a button

I'm trying to simulate a binary counter that is supposed to be activated by a button B, then count until 40, reset and stop until B gets pushed again. If B is pushed while the counter is working it ...
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Preparing custom / arbitrary sequence counter

I know following types of counters: Asynchronous counter Clock input of each flip flop is output of earlier flip flop.[ref] Synchronous counter variant 1: with ANDing for flip flop inputs ...
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Calculate the next state for flip flop sequential circuit

Based on my previous question, i managed to draw out the truth table Inputs for flipflops sequential circruits ...
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Inputs for flipflops sequential circruits

Not very sure if these inputs are correct before i draw my truth table. Too many lines and i am confused. JA = QB = KA = B KA = B DB = D' TC = 0
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Please help! Implement 4-bit Incrementer with two 74LS163 + 74LS74A + XNOR gate(s) + AND gate(s)

The Question Use two 74LS163, one 74LS74A, XNOR gates and AND gate(s) to build a circit that can "add" two given "4-bit binary numbers" A and B. Here is how the circuit computes SUM = A+B (for SUM &...
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Can I make a latch using 2 AND gates, instead of NAND gates?

I have seen that, generally, a simple latch is made using either 2 NAND gates or 2 NOR gates. Can I make a latch using 2 AND gates ?
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D Latch as Transparent latch

I was reading an article over latches and suddenly a line struck me which says "D latches are also known as Transparent latches.". Anyone who can explain me why D latches are known as transparent ...
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Missing contamination delay specification for a component

If IIUC: contamination delay (\$t_{cd}\$) is the time where the signal level on the output of a component starts to change in response to a change on the component's input, while the propagation delay ...
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Trigger based on Time Difference between two sensors / Catch a Miss on sensor

I have two Sensors S1 and S2, S1 is a 24v inductive proximity sensor which i isolated using octocoupler to work at 5v and S2 is a transmissive type phototransistor sensor, both are placed at a fixed ...
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Finite State Machine and Reset Signal

let's consider a certain finite state machine, for instance a Mealy Machine: I was told that it cannot work properly in absence of a reset signal (for the State Register), since we would not know the ...
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Digital Logic Design - Sequential Circuits

The circuit diagram below is in a stable state because of the two inverters. Why and how did it reach a stable state?
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Digital Logic Design [duplicate]

Consider the circuit diagram below. What will happen if at some instant the inverter input is zero?
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Are Verilog if blocks executed sequentially or concurrently?

I'm learning Verilog with some background in VHDL and C. I would like to know if Verilog if blocks are executed concurrently or not, and if this is IDE- or vendor-dependent. For example, are the ...
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JK flip flop PRESET and CLEAR function

I understand that Preset and Clear inputs are asynchronous inputs which means whenever Clock signal is low one of them can immediately set the output to 1 (Preset) or to 0 (Clear) (assuming they are ...
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Setup and hold in flipflops

Usually the data launched at 1st clock edge will be captured at 2nd clock edge. But Is it possible to launch at 1st edge and capture data in same clock edge? The clock to capture flip flop is delayed ...
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D flip-flop sequencer to light three LEDs up sequentially together and then turn them all off

This circuit should turn on three lights sequentially whenever there is a high logic level until all are lit and then turn them all off, restarting the cycle. It seems the following sequencing ...
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Sequential circuit: What does state mean exactly?

I have read some posts like: What is state in a sequential circuit? about explaining what a state is in the sequential logic circuit. But the responses are pretty much the same as those ones in my ...
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Can I do this in Multisim?

Here is sequential circuit I want to simulate in Multisim: Pay attention to AND gates which I labeled with red numbers. Inputs to first gate are X and Q1, to second X and Q2 and to third X and ...
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Priority Encoder with Memory

I am looking for some kind of pin channel selector design for 16 signals, 0-5V. When a specific signal got high, I should get its number (address) over a 4 pins address. No simultaneous highs will ...
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Analysis of Sequential Circuits - Derive the state Equations from the Diagram

How can I derive boolean expression for this diagram? This is my answer: D0 = Cnt ⊕ Z D1 = ZCnt' + ZQ'Cnt + ZCntQ' For D1, I don't know what will be the expression if the input came from ...
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Is there a circuit that outputs high indefinitely once one high is received by the circuit? [duplicate]

Apologies if the question is worded oddly/weirdly, but specifically I have a comparator with an unstable output which I know could be fixed with hysteresis, but I would rather just have some circuit ...
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168 views

Design a T flip flop and draw the asynchronous state diagram

I am supposed to design a T flip flop using logic gates (asynchronous sequential circuit) and also draw the state diagram. I don't really understand why the output doesn't change from 0 to 1 when ...
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Using 2 Data Flip Flops to create an up counter from 0 to 3 and repeats

I've done most of the legwork. I've got this design working using 2 set reset(SR) flip flops, but I need to make it using 2 data flips, a.k.a D flip flops. What I did: Note the numbers not in ...
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Problem based on Latches (Sequential Circuits)

I am trying to solve the following question: I want to know: If the truth table for \$ Q_{n+1}\$ and \$\bar Q_{n+1}\$ is correct. I have found out the Reset and \$Q_{n}\$ conditions. However, I see ...
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I’m having trouble solving this digital circuit. Help!

I need to design sequential logic circuit from this state diagram using only 2 D-latches. And this is my attempt: If I put it in the simulator it just gives me error and wont count. I assumed that ...
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Motor Control - Counter design for the control circuit

I want to design a Johnson/ring counter circuit for control of my sr motor. Until now I have got this information, which I have tabulated in the following waveforms I am attaching for the reference:- ...
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How does an RS-latch work in the presence of propagation delays?

I've long wondered how an RS-latch can work, given the existence of propagation delays. If the nor-gates have non-zero propagation delays (aka gate delays), wouldn't it need to be the case that: The ...