Questions tagged [sequential-logic]

A digital logic circuit containing feedback, in which outputs depend not only on present values of inputs but also on past values. Sequential logic is used to implement state. Contrast with "combinatorial logic", where outputs depend only on present values of inputs, and there is no feedback.

Filter by
Sorted by
Tagged with
0 votes
1 answer
82 views

Why does my sequential circuit keep getting one wrong bit at the final state

I have an assignment to design a sequential circuit using T Flip-Flops that travels through the following states (0010, 1001, 0011, 0001, 0100 then repeats again.) I am designing this circuit using ...
user avatar
1 vote
0 answers
45 views

The same Minterm Twice in a sequental D flip flop

So my professor gave me a question that I have to search the answer for, it's a sequential D flip flop circuit with this sequence. I have searched far and wide and still don't understand how to solve ...
user avatar
-2 votes
1 answer
103 views

What does this circuit do? (flip flop) [closed]

I am trying to understand a circuit which does two arithmetic operations of 5-bit words in 2 cycles: Q = 2*Q - A (one cycle) Q = 11*Q (two cycles) What does this part do? This is the whole circuit:
user avatar
-1 votes
1 answer
86 views

How do Sequential circuits exactly work?

Currently I am trying to learn more about computer architecture. I seem to understand the concept of sequential circuits but there is one thing I cant understand and I cannot find any info on it Lets ...
user avatar
  • 3
4 votes
2 answers
231 views

How can I output a sequence of bits using only simple discrete components?

My degree had given me some electrical engineering basics, and I like to keep studying it in my spare time. I would like to achieve something with electronics, which is why I am asking here instead of ...
user avatar
  • 311
13 votes
3 answers
2k views

In FPGAs, is it safe to execute non-blocking assignments like `b <= a; a <= 0;` in the same clock cycle?

I have a piece of code in Verilog which needs to assign the value of shift register to an output register when the shifting has finished, and I want to reset the value of the shift register in the ...
user avatar
  • 965
2 votes
1 answer
91 views

Hold time constraint equation

I am trying to understand the equation for hold time in the Digital Design and Computer Architecture book: https://www.sciencedirect.com/topics/computer-science/hold-time-constraint Hold time ...
user avatar
0 votes
2 answers
159 views

Digital logic/sequential circuit to produce one pulse for every 5 clock pulses

I'm working on a problem where I'm trying to design a digital logic circuit (sequential circuit?) to produce output Y given input A: So the goal is to produce one pulse for every 5 input pulses. What ...
user avatar
  • 3
0 votes
2 answers
59 views

Write Boolean equations for Q and Q' of clocked SR latch

I am not an EE student but a CS student, so I may not have in depth knowledge regarding the specific of latches, flip flop. The answer to this question was: ...
user avatar
0 votes
3 answers
394 views

Why does a 4-bit asynchronous counter need exactly 4 flip-flops?

We can get the same result (counting from 0000 to 1111) by removing the last flip-flop (Q3 output) and taking clock line as one of the inputs (i.e Q0 will be from clk itself and rest 3 outputs from 3 ...
user avatar
  • 13
0 votes
1 answer
66 views

Sequential synchronous circuit exercise

I need some help in understanding an exercise. Here I have a State Diagram (Moore Machine), and the exercise asks me to write the table of transitions between states and machine outputs. I can ...
user avatar
  • 1
0 votes
1 answer
51 views

Active high SR latch when input changes from (1,0) to (0,1)

If we do analysis like in the below diagram i.e from S side, then I got outputs Qn+1=0 and (Qn+1)'=0. But it is not supposed to happen according to state table( i.e actually Qn+1=1 and (Qn+1)'=0 must ...
user avatar
0 votes
1 answer
70 views

sequential synchronous circuit

I'm learning about sequential synchronous circuits, and I was trying to do an exercise, but I'm not going as I expected. The exercise is about Elaborate the excitation equation of flip-flops; Write ...
user avatar
  • 61
0 votes
1 answer
452 views

Why Tcd and Tpd is different in combinational ckt?

In book Harris & Harris , there is a statement that Contamination delay \$T_{cd}\$, and Propagation delay \$T_{pd}\$ are different due to following reasons: Different rising and falling delays, ...
user avatar
0 votes
0 answers
36 views

Counting no. of clock cycles

This question was asked in GATE 2021. Here I am finding it difficult to "manage" propagation delay of XOR gate. Solving it using timing diagram takes a lot of time and rough space. Is there ...
user avatar
3 votes
1 answer
130 views

Question on timing diagram of a SR Latch with different gate delays

Below is the verilog code that I wrote to implement a simple SR Latch. Note that I assumed different gate delays for the same NOR gate. (#10, ...
user avatar
0 votes
2 answers
118 views

Why is my Verilog code for Mealy-type sequential circuit not working?

I am supposed to write code for a circuit which outputs (z) 1 whenever the 2-bit input (x) is either 00 or 11 for two consecutive clock cycles. I feel like I'm close, but I can't figure out where I'm ...
user avatar
0 votes
1 answer
57 views

2 momentary button into 1 persistence output with clk pulse

I'm making a binary input button pair with one or "1" and the other for "0" and load this input into a shift register so I need to have from these 2 buttons a persistent line for ...
user avatar
1 vote
1 answer
197 views

Power strip with individual time delays for each socket

I am to purchase a power strip that has programmable time delays for each socket. What I would like to happen is once the power strip receives power, the first socket from the strip counts down from 2 ...
user avatar
-1 votes
1 answer
692 views

Unable to simulate a JK Flip-Flop using VHDL dataflow modelling

I want to write code and simulate waveforms for flip flops strictly using dataflow modelling. In this case I'm simulating a jk flip flop with only j,k and clock (no set , reset). It compiles fine, but ...
user avatar
2 votes
2 answers
81 views

Having trouble constructing this sequential circuit

I am to construct a sequential digital logic Moore circuit for the back lights of a car based on the following information: We have input: x2, x1, x0, I decided to make x0 simulate the right turn ...
user avatar
  • 23
0 votes
1 answer
44 views

Sequence diagram, having hard time to understand how to interperet question

I have to construct a sequential circuit: We have input x0 and x1 If the following sequence is done, then we want to open a lock, represented by lighting up an LED: x0 = 0, x1 = 0 x0 = 1, x1 = 0 x0 = ...
user avatar
  • 23
0 votes
1 answer
68 views

Digital downcounter not resetting

I have a digital down counter which is supposed to count from 9 to 0 and then it goes back to 9 (bottom) but it only goes back from 9 to 8 and then back to 9 and I don't understand how it works. Note ...
user avatar
8 votes
4 answers
3k views

Why can't I make flip-flops in logic simulators?

I've been playing with a few logic simulators and don't understand why flip-flops are not working. I'm trying to implement a T flip-flop with NAND gates: All the simulators I've tried give the same ...
user avatar
  • 191
1 vote
0 answers
205 views

how to design multiple sequence recognizer

Question : Design a state diagram for a sequence detector that give output 1 once either 1010 or 0101 is detected (Mealy machine) this is my state diagram, but i am having trouble to detect 1010 ...
user avatar
1 vote
1 answer
975 views

Is this Mealy representation correct for 011?

I am practicing on moore and mealy machine sequence detectors and I want to make sure if the mealy 011 sequence detector is correct.
user avatar
  • 109
1 vote
1 answer
55 views

Trouble Storing Information in D Flip Flop

So I'm really not understanding how to store bits in flip flops and have them enable for to change on a condition. Here's the general setup that I'm trying to do but it just doesn't seem to work.
user avatar
9 votes
3 answers
2k views

How is the Q and Q' determined the first time in JK flip flop?

My background is in Computer Science, and this is my first time posting in electronics SE. This is a circuit diagram of JK flip flop. I don't understand how it works at the beginning, when the ...
user avatar
  • 91
0 votes
2 answers
229 views

Why are transparent latches discouraged / encouraged in digital design?

I have come across material per review from my past encounters with digital sequential logic and I wanted to pose a specific and hopefully general question for the community to help shed some light. I ...
user avatar
  • 139
0 votes
1 answer
554 views

Verilog code for this question

The question in my textbook was: Design and implement a Serial 2’s Complementer with a Shift Register and a flip–flop. The binary number is shifted out from one side and it’s 2’s complement shifted ...
user avatar
1 vote
1 answer
251 views

Increment Input on Clock Cycle

I have an 8-bit input and my goal is to increment the input on each clock cycle. The new value will then be saved into a register to be used to search memory. Say, for example, the input is currently ...
user avatar
  • 11
5 votes
2 answers
270 views

Does combinational and sequential logic correspond to some mathematical logic systems?

Is it correct that the functionalities of digital circuits are divided into combinational logic and sequential logic? Is combinational logic the same thing as propositional logic in mathematical ...
user avatar
  • 349
0 votes
2 answers
2k views

D Flip Flop design using multiplexer

I was trying to implement a simple D Flip Flop using 2 multiplexers. Are there any errors in design? Do you have any other suggestions about design? Thanks. Update: As you'd recognise I've not ...
user avatar
  • 299
0 votes
2 answers
1k views

How to design Gray code synchronous counters of large widths using SystemVerilog?

I want to design a synchronous gray code counter which is 10 bits wide in SystemVerilog. The counter should have an Active HIGH synchronous reset. I know how to design a 3 bit gray code counter like ...
user avatar
  • 2,411
0 votes
2 answers
60 views

Flip-flop with numbered inputs

On page 3 of the datasheet for the SN74LS597 IC, I have found the following diagram: Notice that the flip-flops have some numbered inputs (1D and C1, 2D and C2, C3 and 3S/3R) and some simple inputs (...
user avatar
  • 103
-2 votes
1 answer
87 views

Why do some flip flops have control inputs? In what ways do they differ from the normal inputs such as J and K?

I'm currently studying sequential circuits and came across this question. Can't figute out the answer. Can somebody help?
user avatar
  • 1
0 votes
1 answer
53 views

Query on Edge triggered D-flipflop using SR-latches

When clk is 0 and during this time let us assume d is 0 this drives r and rbar to be 1. Isn't this a forbidden case of SR latch?? After this state if clk and d becomes 1 at the same time wont it cause ...
user avatar
  • 1
3 votes
1 answer
326 views

Flip-flop feedback timing problem

So this is my first question here. I am reading this book, "Digital Electronics & Computer Design - By M.M. Mano". While I was reading the Sequential logic and flip-flops, I found this: ...
user avatar
  • 133
1 vote
4 answers
683 views

Frequency divider circuit of a factor of arbitrary number

We know that using T-Flip Flops in a cascaded manner(something like ripple counter) allows us to divide the clock frequency by a factor of \$2^{n}\$ where \$n\$ stands for the number of flip-flops. ...
user avatar
  • 13
0 votes
2 answers
141 views

Why would you set the reset at the input state of FSM to 1?

I am trying to find the answers online but without any luck. The FSM is a moore machine and there is a reset that is set to 1. What is the function of a reset? Thanks
user avatar
0 votes
1 answer
100 views

Question On Logic Gates

In a small railway station, there are three platforms, #1, #2, #3. Up and down trains can enter in platform number #2 and #3, but platform #1 is only devoted to up trains. Design a logic circuit using ...
user avatar
2 votes
2 answers
684 views

How to know if a verilog code is sequential or combinational?

How to know if this piece of code is for a sequential or a combinational circuit?
user avatar
  • 123
1 vote
0 answers
102 views

Build a T flip-flop with enable and reset using only a JK flip-flop (without enable or reset) and some necessary logic gates

Can someone help me to check whether my answer is correct or wrong, because I am confused with some of the condition of enable and reset. I am confused if the enable is low and the reset is high, ...
user avatar
1 vote
2 answers
532 views

Confusion about when a JK flip flop is triggered

I started learning about latches and flip flops recently, and my understanding is that edge-triggered devices like flip flops ignore their inputs until the clock signal transitions from low to high or ...
user avatar
1 vote
2 answers
301 views

Basys 3 FPGA sequential circuit reset remotely?

Since the COVID-19 pandemic, I'm teaching Verilog lab online. I let each student remotely connect to a computer having Xilinx Vivado installed, a Basys 3 board connected and powered on, and a camera ...
user avatar
0 votes
1 answer
67 views

Having trouble with deriving the state diagram for an exam problem

The Problem: Derive the state diagram for a circuit that takes one input, A and gives out one output X, X is to be one, if and only if it detects a sequence "101" in A. Understanding The problem: if ...
user avatar
  • 297
0 votes
3 answers
98 views

For SR timing diagrams, does a bubble on the output of Q' indicate that it is the same as Q?

I understand that with flip flops when there is a bubble on the clock it means the clock cycle is in terms of the falling edge, but when there is a bubble on the output Q' isn't this inverting Q twice,...
user avatar
1 vote
1 answer
546 views

3-Stage Shift Register using Blocking assignment in Verilog - Differences among simulators

Simulation of a 3-stage shift register using blocking assignment statement in Verilog gives different simulation results across simulators: The RTL code is as follows: ...
user avatar
1 vote
1 answer
55 views

Need help making a counter controlled by a button

I'm trying to simulate a binary counter that is supposed to be activated by a button B, then count until 40, reset and stop until B gets pushed again. If B is pushed while the counter is working it ...
user avatar
1 vote
0 answers
91 views

Preparing custom / arbitrary sequence counter

I know following types of counters: Asynchronous counter Clock input of each flip flop is output of earlier flip flop.[ref] Synchronous counter variant 1: with ANDing for flip flop inputs ...
user avatar
  • 227