Questions tagged [sequential-logic]
A digital logic circuit containing feedback, in which outputs depend not only on present values of inputs but also on past values. Sequential logic is used to implement state. Contrast with "combinatorial logic", where outputs depend only on present values of inputs, and there is no feedback.
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Sequential diode and capacitor - low vs high capacitance
Here is my circuit:
Diode and capacitor
When I set capacitor to 1F I get the following voltage graph:
When I set capacitor to 1pF I get the following voltage graph:
Why do I get this totally ...
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How to draw a sequential logic circuit from any given state diagram?
Could someone point out to me a resource to learn how to draw a sequential logic circuit from any given state diagram or could you tell me how to do it? I am a non-native English speaker. So please ...
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Why do I get a null output to this Verilog code?
I'm working on an assignment where I need to implement a sequential circuit with a d-flip-flop, but the output is null, and it doesn't output multiple times like I thought it would.
The output is <...
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Sequential Circuit Design
Here is a simplified version of what I am hoping to do:
I have two switches and a light. Both switches are momentary (spring return) buttons. I want the light to only turn on while the left button is ...
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Do we decide the output of a sequental circuit based on its present state or next state?
Suppose in a sequential circuit, we have an output which is based on the present state and the input, and the input of flip flops are based on the given input. When we change the input the output will ...
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Implementing FSM with Sequential Logic
I am trying to complete Problem 4 of this MIT Computation Structures lab, which requires you to use a circuit simulator called Jade to build a sequential logic circuit that implements the below FSM:
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Why does my sequential circuit keep getting 1111?
I have an assignment to create circuit on this website called Circuitverse
The question was to design 4-bit counter circuit with 1 external input using D flip flops, whereby when input=0, count ...
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In Sequential Circuit, Are Two States Equivalent If Their Next States Are Each Other?
When eliminating redundant states in the state table of a sequential circuit, we need to find equivalent states in the same circuit. In Fundamentals of Logic Design, two states are equivalent if and ...
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Verilog code for JK flip flop (gate level modelling) error in output (x propagation)
I have written Verilog code for a JK flip flop (gate level modelling), and I am getting an error in the output (error means x propagation). Why are my ...
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Propagation Delay of Sequential Logic Circuit
I'm trying to work through the above sequential logic problem from MIT OCW's Computation Structures course. However, I'm having trouble calculating tpd of the Zero output.
I'm a complete novice at ...
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Can you explain what is happening on this oscilloscope? (sequential counter circuit) [closed]
I built an up/down counter circuit and set the frequency on this oscilloscope to 1Hz. Can someone explain what the (blurred sorry) image represents?
Is the blue or the yellow line the clock?
Which is '...
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Trouble with FSM circuit using Schmitt trigger clock
I'm having some trouble with my circuit based on the design below, that I built for the lab. I'm using a Schmitt trigger clock. I built the circuit on a breadboard and connected it to the clock and ...
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Connecting a 7-segment display to a CD4543B decoder
I would like some help connecting a 7-segment display to a CD4543B decoder according to the instructions in the image at the bottom, and get the display to show the expected numbers. How is it ...
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Sequential logic with two inputs
I have a lab assignment that goes like this:
Design a water level controller using a sequential circuit. To control the water level two sensor is to be used (upper and lower). The sensor gives logic ...
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Can a register be considered a sequential circuit?
If you build a 2-bit register with JK flip-flops with the objective to allow storing the bit that was last added, can this be considered a sequential circuit?
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Are there any "Both Rising Edge and Falling Edge Triggered" Shift Register?
I was designing this circuit in Logisim-evolution. In the book, it is mentioned that an n-bit multiplier would require n-clock cycles to work. I think this will be possible only when we have the shift ...
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SR flip-flop with Preset and Clear should not work as described
In the presented flip-flop, suppose the Enable signal is high, the S is low, and R is high. Now we set the Preset low (0) and the Clear high (1). In this condition, we expect Q=1 and Q'=0.
But ...
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How to get a reliable simulation of assignment delay in the always block (Xilinx Vivado)?
I am having trouble with simulation of the nonblocking assignment delay in the always block.
A simple example: assignment of the input ...
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How to pipeline CPU instructions in sequence?
I am designing a 16 bit CPU in Logisim Evolution.
I have already designed single clock cycle instructions.
I have 19 bits to control.
I tried using the register and clock divider circuit to send data ...
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Is Quine–McCluskey algorithm globally optimal or is there a better way for K-Map reduction?
A bit of context...
We are working on a project to convert FA (Finite Automata) to Digital Sequential Circuits and vice-versa.
In this process we came across a step: Reduction of Karnaugh (K-Maps).
...
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How can SR-Latches store data over time?
My understanding is that the storing part of SR-latches boils down to having a wire loop. Ostensibly, the idea is that if there was current in the loop a second ago, there will still be current in the ...
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Why does my sequential circuit keep getting one wrong bit at the final state
I have an assignment to design a sequential circuit using T Flip-Flops that travels through the following states (0010, 1001, 0011, 0001, 0100 then repeats again.) I am designing this circuit using ...
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The same Minterm Twice in a sequental D flip flop
So my professor gave me a question that I have to search the answer for, it's a sequential D flip flop circuit with this sequence.
I have searched far and wide and still don't understand how to solve ...
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What does this circuit do? (flip flop) [closed]
I am trying to understand a circuit which does two arithmetic operations of 5-bit words in 2 cycles:
Q = 2*Q - A (one cycle)
Q = 11*Q (two cycles)
What does this part do?
This is the whole circuit:
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How do Sequential circuits exactly work?
Currently I am trying to learn more about computer architecture. I seem to understand the concept of sequential circuits but there is one thing I cant understand and I cannot find any info on it
Lets ...
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How can I output a sequence of bits using only simple discrete components?
My degree had given me some electrical engineering basics, and I like to keep studying it in my spare time. I would like to achieve something with electronics, which is why I am asking here instead of ...
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In FPGAs, is it safe to execute non-blocking assignments like `b <= a; a <= 0;` in the same clock cycle?
I have a piece of code in Verilog which needs to assign the value of shift register to an output register when the shifting has finished, and I want to reset the value of the shift register in the ...
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Hold time constraint equation
I am trying to understand the equation for hold time in the Digital Design and Computer Architecture book: https://www.sciencedirect.com/topics/computer-science/hold-time-constraint
Hold time ...
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Digital logic/sequential circuit to produce one pulse for every 5 clock pulses
I'm working on a problem where I'm trying to design a digital logic circuit (sequential circuit?) to produce output Y given input A:
So the goal is to produce one pulse for every 5 input pulses.
What ...
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Write Boolean equations for Q and Q' of clocked SR latch
I am not an EE student but a CS student, so I may not have in depth knowledge regarding the specific of latches, flip flop.
The answer to this question was:
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Why does a 4-bit asynchronous counter need exactly 4 flip-flops?
We can get the same result (counting from 0000 to 1111) by removing the last flip-flop (Q3 output) and taking clock line as one of the inputs (i.e Q0 will be from clk itself and rest 3 outputs from 3 ...
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Sequential synchronous circuit exercise
I need some help in understanding an exercise.
Here I have a State Diagram (Moore Machine), and the exercise asks me to write the table of transitions between states and machine outputs.
I can ...
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Active high SR latch when input changes from (1,0) to (0,1)
If we do analysis like in the below diagram i.e from S side, then I got outputs Qn+1=0 and (Qn+1)'=0.
But it is not supposed to happen according to state table( i.e actually Qn+1=1 and (Qn+1)'=0 must ...
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sequential synchronous circuit
I'm learning about sequential synchronous circuits, and I was trying to do an exercise, but I'm not going as I expected.
The exercise is about
Elaborate the excitation equation of flip-flops;
Write ...
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Why Tcd and Tpd is different in combinational ckt?
In book Harris & Harris , there is a statement that Contamination delay \$T_{cd}\$, and Propagation delay \$T_{pd}\$ are different due to following reasons:
Different rising and falling delays,
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Counting no. of clock cycles
This question was asked in GATE 2021. Here I am finding it difficult to "manage" propagation delay of XOR gate. Solving it using timing diagram takes a lot of time and rough space.
Is there ...
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Question on timing diagram of a SR Latch with different gate delays
Below is the verilog code that I wrote to implement a simple SR Latch. Note that I assumed different gate delays for the same NOR gate. (#10, ...
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Why is my Verilog code for Mealy-type sequential circuit not working?
I am supposed to write code for a circuit which outputs (z) 1 whenever the 2-bit input (x) is either 00 or 11 for two consecutive clock cycles. I feel like I'm close, but I can't figure out where I'm ...
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2 momentary button into 1 persistence output with clk pulse
I'm making a binary input button pair with one or "1" and the other for "0" and load this input into a shift register so I need to have from these 2 buttons a persistent line for ...
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Power strip with individual time delays for each socket
I am to purchase a power strip that has programmable time delays for each socket. What I would like to happen is once the power strip receives power, the first socket from the strip counts down from 2 ...
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Unable to simulate a JK Flip-Flop using VHDL dataflow modelling
I want to write code and simulate waveforms for flip flops strictly using dataflow modelling. In this case I'm simulating a jk flip flop with only j,k and clock (no set , reset). It compiles fine, but ...
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Having trouble constructing this sequential circuit
I am to construct a sequential digital logic Moore circuit for the back lights of a car based on the following information:
We have input: x2, x1, x0, I decided to make x0 simulate the right turn ...
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Sequence diagram, having hard time to understand how to interperet question
I have to construct a sequential circuit:
We have input x0 and x1
If the following sequence is done, then we want to open a lock, represented by lighting up an LED:
x0 = 0, x1 = 0
x0 = 1, x1 = 0
x0 = ...
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Digital downcounter not resetting
I have a digital down counter which is supposed to count from 9 to 0 and then it goes back to 9 (bottom) but it only goes back from 9 to 8 and then back to 9 and I don't understand how it works.
Note ...
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Why can't I make flip-flops in logic simulators?
I've been playing with a few logic simulators and don't understand why flip-flops are not working. I'm trying to implement a T flip-flop with NAND gates:
All the simulators I've tried give the same ...
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how to design multiple sequence recognizer
Question : Design a state diagram for a sequence detector that give output 1 once either 1010 or 0101 is detected (Mealy machine)
this is my state diagram, but i am having trouble to detect 1010 ...
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Is this Mealy representation correct for 011?
I am practicing on moore and mealy machine sequence detectors and I want to make sure if the mealy 011 sequence detector is correct.
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Trouble Storing Information in D Flip Flop
So I'm really not understanding how to store bits in flip flops and have them enable for to change on a condition. Here's the general setup that I'm trying to do but it just doesn't seem to work.
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How is the Q and Q' determined the first time in JK flip flop?
My background is in Computer Science, and this is my first time posting in electronics SE.
This is a circuit diagram of JK flip flop.
I don't understand how it works at the beginning, when the ...
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Why are transparent latches discouraged / encouraged in digital design?
I have come across material per review from my past encounters with digital sequential logic and I wanted to pose a specific and hopefully general question for the community to help shed some light.
I ...
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