Skip to main content

Questions tagged [sgmii]

Serial Gigabit Media Independent Interface (SGMII)

Filter by
Sorted by
Tagged with
1 vote
1 answer
25 views

MII to SGMII to connect ETH Switch is it possible?

I want to connect MCU with parallel MII interfaces to switch ICs with SGMII interfaces in this method : The Eth SW support 8xMDI Channel and 4xSERDES(SGMII,USXGMII,5GBASE-X , ETC). I'm afraid that I ...
Knowledge's user avatar
  • 441
2 votes
1 answer
340 views

Can SGMII MAC communicate with 100BASE PHY at 1 Gb/s?

In the DP83TC811S-Q1 SGMII's datasheet it says Because the DP83TC811S-Q1 operates at 100 Mbps, the 1.25 Gbps rate of the SGMII is excessive. The SGMII specification allows for 100 Mbps operation by ...
qand's user avatar
  • 57
0 votes
0 answers
194 views

What is the standard common mode voltage of Media Dependent Interface MDI[0:3]± signals?

I am working on the selection RJ45 connector for MDI interface between PHY and the link-partner. I am planning to use this PHY for my SGMII interface application. From various online readings, I ...
student7's user avatar
  • 319
0 votes
1 answer
1k views

What is the SGMII differential peak to peak voltage?

I am trying to understand the SGMII Driver and Receiver DC specification. Here is the link to SGMII specification - SGMII.pdf I am studying. Table-1: Driver DC specification Table-2: Receiver DC ...
student7's user avatar
  • 319
0 votes
1 answer
1k views

Serial Gigabit Media Independent Interface (SGMII) - 1.25 Gbps vs 1 Gbps?

What is the difference between 1.25 Gbps vs 1 Gbps SGMII signal data rate? My understanding is that 1.25 Gbps is the raw data rate and 1 Gbps is the actual data rate (After removing the headers and ...
student7's user avatar
  • 319
2 votes
1 answer
295 views

What values should be checked for SGMII signal compatibility?

How can I verify the DC electrical compatibility of the SGMII signal between PHY and MAC (within FPGA)? Here is the reference-design that I am working on. Page 40 is using a Marvel PHY that is ...
student7's user avatar
  • 319
1 vote
0 answers
340 views

Connection Ethernet MACs without using a PHY device

I am designing a board that utilizes an NXP LS1046a processor and multiple Kintex Ultrascale FPGAs. The plan is to connect the processors up to the three FPGAs via the 1Gbe links. Since they are all ...
Matty's user avatar
  • 217
1 vote
1 answer
605 views

SGMII Termination - Not understanding recommendation

I am going to be using a processor that has a few SGMII interfaces. From what I understand, these interfaces have LVDS logic levels. I am not use to seeing the termination scheme as recommended below. ...
Matty's user avatar
  • 217
0 votes
0 answers
231 views

Can I use an Ethernet switch IC without connecting to the mcu?

I'd like to add an unmanaged Ethernet switch IC to a board I am designing, but I have no free RGMII/SGMII/PCIe connection available on my MCU. The goal of this IC is just to save space/hassle (in the ...
RH6's user avatar
  • 25
1 vote
1 answer
1k views

sgmii auto negotiation - how long should this take?

I am working with LWIP - and an 1G marvell phy, m88e1111 - connected to a Microsemi SmartFusion 2 FPGA design using 10b8b (aka: TBI) interface. I'm doing something wrong with the auto negotiation and ...
user3696153's user avatar
6 votes
1 answer
6k views

The SERDES/transceiver design inside the Ethernet MAC controller

I'm a little confused about the "SERDES" interface between MAC and PHY chip, and I drew some figures to illustrate the connections which confuse me as shown below. The MAC controllers in 3 figures are ...
Nobody's user avatar
  • 681
1 vote
1 answer
925 views

How to connect CPU with RGMII pins to an LTE module that takes only SGMII signals?

The Hi3519 Hisilicon CPU has RGMII pins. We are trying to connect it to the EC21 LTE Module from Quectel which contains SGMII pins. Would using two Realtek RTL8201F-VB-GG PHY chips with magnetics ...
k051819's user avatar
  • 41
3 votes
1 answer
833 views

Broadcom Ethernet PHY link-up issue

We are using BCM5482SA2KFBG PHY for ethernet link in SGMII mode by selecting INTSEL = 2'b10. The PHY was supposed to establish a link upon power up using Autonegotitation without any management ...
Sudarshan shenoy's user avatar
1 vote
1 answer
582 views

SGMII to 100BASE-FX

I need to connect seventh port (SGMII) of KSZ9477S switch to AFBR5803AQZ optical transceiver (It's 100 Mbps). I wanted to use PHY with SGMII interface and fiber mode (VSC8658XHJ), but it's too ...
Andy's user avatar
  • 355
0 votes
1 answer
3k views

Purpose of QSGMII

I do not understand the purpose of QSGMII. QSGMII is supposed to combine 4 SGMII signals from 4 MACs into 1 QSGMII signal at 5 GHz. However, there is no Ethernet standard that works at 4 (or 5) GHz. ...
pierre123's user avatar
1 vote
1 answer
958 views

SGMII, MDIO and link training

I am reading this document : https://www.nxp.com/webapp/Download?colCode=AN3869 I got this link from NXP support, but I did not get a precise answer to my questiosn and I would like to be sure : The ...
pierre123's user avatar
1 vote
1 answer
3k views

Does SGMII use MDIO?

I was reading the SGMII specification and the documentation of a Gigabit MII to SGMII converter (see MAX24287). I do not see a MDIO to control the registers of the PHY (Basic Mode Status Register, ...
pierre123's user avatar
0 votes
1 answer
842 views

Does SGMII contain MDIO?

When connecting a NIC (Intel I210-IS) to an gigabit ethernet switch with integrated PHYs (Marvell 88E6176) using the SGMII interface, I came across the following question: Since SGMII is a serialized ...
Simon's user avatar
  • 695