Questions tagged [signal-integrity]

Questions regarding how to properly ensure Signal Integrity, protection from noise, shielding, proper pcb layout.

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61 views

Determining cause of QSPI FLASH output glitches

I am testing a QSPI NOR FLASH device on a board I designed. It's datasheet is here. Although it is working, I am seeing some glitches on the FLASH SDO (Serial Data Output) line. All other signals are ...
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77 views

Connecting FPGA to a device's RAM data bus distorts signal - how to fix it?

In short, I am trying to read data from a RAM's data bus via a FPGA. But the more lines from the bus I connect to the FPGA, the more distorted the signal become. In more detailed, I have a FON2100 1 ...
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1answer
31 views

How to protect the signal quality of LVDT input and output?

I am designing a 6 wire LVDT. I need to know how to protect the signal quality of both the primary excitation input and secondary coil outputs inside the LVDT, and inside the device in which the LVDT ...
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850 views

Why application notes advise series resistance to be added on clock lines for high-speed interfaces, like SDIO, and not on data lines?

Many application notes (like this one) advise series resistance to be added on the clock line, close to the source. I do understand that this resistance is added there to match the source impedance to ...
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1answer
51 views

Passivity and Causality of PCB channel

We use S parameters to analyze a PCB channel. Once the S parameters are extracted, what I have seen is SI engineers will check the S parameters obtained are passive and casual. I have some questions ...
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34 views

What you mean by ¼ wave resonance

I was learning about VIA modeling with the help of this paper (http://lamsimenterprises.com/Method_of_Modeling_Differential_Vias-mod-Iss2.2-Apr2-12.pdf) I referred to many papers. Everywhere I can see ...
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1answer
41 views

Why is mutual inductance coupling high in a microstrip PCB line?

I am learning about crosstalk on PCBs from the high-speed signal propagation book by Howard Johnson. It says mutual inductance coupling is high in microstrip lines compared to mutual capacitive ...
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2answers
109 views

SPI questions: EMC and signal integrity

I have an SPI line going at a speed of 12Mbit/s on a 2-layer PCB. This is for a product so it needs to pass EMC tests (as well as just work well). Questions: Should I use series resistors for all the ...
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1answer
67 views

How is I2C signal integrity maintained over monitor cables for EDID?

Computer monitors (and other similar display equipment) use the I2C protocol with 5V signal levels to send EDID information to the "host". I2C's typical use case is for short connections on ...
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34 views

Impact of heat on unshielded data cables

How does heat impact the signaling performance of unshielded ribbon/flexible flat cables? Background: I'm modding a camera to improve thermal performance by adding thermal pads between the heatsink ...
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21 views

Does HyperLynx have an impedance calculator for coplanar waveguide?

Does HyperLynx have an impedance calculator for coplanar waveguide like Si8000 does?
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3answers
94 views

Are Ethernet magnetics temperature sensitive

I am using these discrete Ethernet transformers ALT4532M-201-T001. According to the datasheet, they are rated for -40ºC to +85ºC. In general for Ethernet transformers, would I expect to see some ...
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23 views

RLGC extraction from the Asymmetric S-paramter

In the signal integrity of high speed interconnect, in case of extraction of RLGC from S-parameter of it, they assume the S-parameter is symmetric and reciprocal. but in practical case S-parameter of ...
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1answer
62 views

DDR3 logic levels - AC or DC?

In a DDR3 datasheet, I found different voltage levels (AC and DC.) I already know about DC logic levels but I don't know about AC logic levels. What is the difference between the two? Do the AC values ...
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53 views

How can I bridge across a change in differential impedance?

In a design I'm working on, I have a 100Mbps differential signal traveling from a chip on one PCB to a chip on another PCB. For various reasons, I can't make the differential impedance the same on ...
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2answers
97 views

Why do we use S parameters for channel modelling, rather then using Z, Y, h or any other parameter?

For channel modelling in high speed PCBs we always use S parameters. What is the specialty of S parameters for this purpose? Why we are not using Z, Y, h or any other parameter? How do we determine ...
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2answers
90 views

Signal Integrity: rise time or signal frequency, which is more dangerous?

I was watching the below video from Rick Hartley. In this he says more than signal frequency signal rise time is more problematic. A signal with rise time in the range of picoseconds and frequency in ...
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1answer
104 views

S Parameters Channel Modelling Time domain representation of insertion loss

Below is the insertion loss waveform obtained after S parameter of a channel.The waveform is in frequency domain. May I know what is the equivalent time domain waveform and how to obtain it from this ...
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3answers
102 views

Can I use a MOSFET driver as a high current logic voltage shifter

I have been scratching my head on my problem of driving a 800 kHz signal through a 10 meter twisted pair cable (signal+ground) with an abysmal worse case scenario of 1 nF wire capacitance. What I know ...
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2answers
162 views

How to make a 800 kHz digital signal reach 10 meters

I am running some addressable LED strips the SK6812 variant. Because i want to hide the power supply and the controller, the strips and controller is now situated about 10 meters away from each other. ...
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2answers
434 views

Transmission line at DC

Do we need to consider a PCB trace as a transmission line when the Input is a DC signal. As per my knowledge we used to consider PCB trace as a transmission line when length of the trace is more than ...
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0answers
74 views

How important is 'perfectly' phase matching high speed differential lines?

This question is related to Differential pair length matching considering phase. According to Microchip's document Implementation Guidelines for Microchip’s USB 2.0 and USB 3.1 Gen 1 and Gen 2 Hub and ...
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1answer
54 views

long cable capacitance consideration when the output is tri-stated

I have 50 devices that are sending data to one MCU through multiple 3 meter data cables. The data signal lines merge at the MCU location. Only one device will send data at a time at 5 MHz+ data rate. (...
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2answers
71 views

40 MHz clock between 2 ICs

I have an oscillator at 40 MHz which I would like to drive two ICs, 1.8V output. The ICs are in opposite directions so I have opted for star topology of the two clock traces. Trace length for the ...
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57 views

Using a pull-up resistor and considering rise time for IC input

I have a FPGA based design in which the FPGA is interfaced with several ICs. The I/Os of the FPGA and most of the ICs are 3.3V, except from one where the I/Os are 1.8V. While there is no problem for ...
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73 views

MIPI C-PHY Signal Routing

I've been looking for a good, definitive reference example for MIPI C-PHY signal routing and have come up short. Bear in mind that C-PHY uses a set of 3 signals per lane, with multi-level coding ...
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1answer
47 views

What is 'mis-registration' and 'mis-collimation' of television signals?

I was reading about early televisions and television cameras, and I came across these terms with no explanation.... They appear on Google on a few pages, but again I cannot find a definition....
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71 views

TVS diodes routing on USB data lines

I have decided to use bidirectional TVS diodes for ESD protection on the USB data lines. Nevertheless, the pads of the diodes create a discontinuity of the tracks. So, what is the best way to route ...
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1answer
27 views

Wiggling connector receptacle housing causes CAN signal dropout?

I am currently using a 4pin molex Microlock 1.25mm connector that has a CAN connection as well as a power connection. pin 1 = power pin 2 = ground pin 3 = CAN_H pin 4 = CAN_L We recently discovered an ...
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1answer
103 views

Near end crosstalk saturation in a microstrip transmission line

I am referring to a microstrip PCB transmission line. I simulated the crosstalk situation using Hyperlynx. Please see the below circuit: I kept increasing the trace length and measured the crosstalk ...
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26 views

Crosstalk Near END and Far END Waveforms

I was learning the basics of cross talk(https://www.youtube.com/watch?v=5EeQPxRdurk).I am confused about the orientation of near end and far end cross-talk wave form's.Please see the below figure. ...
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51 views

Parallel Termination:FLY-BY Topology

I was simulating fly by topology. I can see that the Rise time and fall time is better for the receiver which is near to the termination resistor. May I know why is it like that.
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1answer
149 views

Why don't we use AC coupling caps for USB 2.0 [closed]

I see we have a requirement for AC caps on USB 3.0 running at 5 Gbps. But why not at USB 2.0 480 Mbps? My question is about why is there need for AC coupling caps on 3.0? Whereas none on USb 2.0 I ...
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229 views

6-Layer Stackup - Where to put the Power Planes?

I have a 6-Layer board (See Design) which is an extension that is connected to a motherboard through a Board to Board Connector. The extension should provide: two USB 3.2 GEN 2 ports, two USB 2.0 ...
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43 views

Use of common choke with more than 2 wires

I've been looking around and I couldn't really get a good answer to this question, not even in Henry Ott's book (so far), so here it goes: What is the best approach when there is the need to place a ...
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1answer
46 views

MUX chips only happy with one of the inputs

I have two MAX4533 quad SPDT chips, all outputs are behaving the same. NOn - a PWM pulse train at 25% generated by an Arduino Mega. NCn - a 5kHz square wave from a AD9833 signal generator. Switching ...
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1answer
102 views

Why there is capacitor in series in high speed designs like SGMII?

Why we are connecting capacitor in series in high speed designs like SGMII. If it is to remove DC voltages, why we are not using on other signals like I2C, SPI and so on. What is the major purpose. ...
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1answer
33 views

Reference layer for stripline / microstrip

I have a question. I read everywhere in manuals that for a stripline (or microstrip), the reference layer can be not only the ground plane, but also the power plane. Actually, I had a couple of ...
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2answers
67 views

Power path around 4 layer PCB

I'm designing a 4 layer PCB (Signal-GND-PWR-Signal) that has power input and motor connectors placed as seen in the picture. In order to avoid thick traces I traced a power path around the PCB ...
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28 views

The accumulative error on the crosstalk items (s23, s14) when cascading multiple 4-port s-parameter

I found there seems existing the accumulative errors on the xtalk items when doing large number of s4p cascading. Here is a brief summary: When it is two port network, ie, s2p, things are much better,...
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21 views

Problems with voltage supply in Altium IBIS simulation

I have a question regarding my project. I am designing high speed output from my microcontroller. Switching times should be around 450 MHz, so I found IBIS model for my microcontroller and line ...
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1answer
203 views

Why route signals orthogonally in adjacent layers?

I am investigating PCB stack-up. Everywhere I have seen it says to route signals on adjacent layers orthogonally to reduce the coupling. I have two questions: How does orthogonal routing reduces the ...
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40 views

What are the required Eye Specifications for SGMII+?

I am performing Signal Integrity Analysis for SGMII+ TX and RX lines operating at a frequency of 2500Mbps. Please let me know the minimum eye specifications such as eye height and eye width required ...
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1answer
72 views

Controlled Impedance Trace-reference plane Placement

I am new to high-speed PCB design. I was studying controlled impedance traces from the internet with the help of various documents. Everywhere it says controlled impedance traces need a reference ...
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1answer
42 views

Differential Pair Mode Conversion [closed]

What is the purpose of using these mode conversions? SCD Input: Differential Output: Common SDC Input: Common Output: Differential
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1answer
183 views

Noise Pick up in High Impedance nodes

I was making a non inverting amplifier,in the first iteration a provided a gain 1000 and at that time I can see the line voltage frequency 50Hz is coming at the output. I reduced the gain and made it ...
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2answers
71 views

Pseudo Periodic Signal

I am reading a research paper Eyer 1999 in which they used these terms so I want to know about them since there is no source on which I can learn about these terms so that's why asking it here, it ...
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1answer
117 views

Parallel Termination in a Transmission Line

Suppose we have a parallel termination like this on a high-speed trace: If the line impedance \$ Z_o \$ and \$R \$ are matched, then there are no reflections from load to cause any ringing at the ...
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1answer
79 views

Termination resistors for RAM vs drive strength

I'm considering using a RAM IC (S27K HyperRAM from Cypress). The layout guidelines document suggests adding series resistors "if necessary." However, the datasheet for the device has a ...
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1answer
81 views

Instrumentation Amp design for breaking ground loops between systems

We're in the midst of designing a device for measuring analog signals and have been testing our initial prototype. We had a single-ended gain stage before the ADC, but due to the connections in the ...

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