Questions tagged [signal-integrity]
Questions regarding how to properly ensure Signal Integrity, protection from noise, shielding, proper pcb layout.
463
questions
0
votes
2
answers
124
views
What is the best way to use 0 ohm resistors for a large number of signals?
I'm fairly new to PCB design, so maybe I start with a basic 0 ohm resistor like this:
I have both output pins (SLEEP & RESET) on the DAC chip. I want to have two options on my PCB, one with 3-pin ...
- 65
2
votes
1
answer
137
views
Simulation of pulse through transmission line with IC load with ringing
There is a pulse going through a transmission line. There is a phenomena where if we put a pulse through a transmission line then after it reaches the IC we can have ringing instead of good pulse.
In ...
- 23
1
vote
1
answer
75
views
Common mode choke placement for good EMC performance
I am interfacing a deserializer with Quectels smart module.
The CSI lines of the deserializer are connected to the CSI lines of smart module.
A common mode choke is placed in between them. The ...
- 1,767
2
votes
1
answer
151
views
Is it a good idea to place SMPS output capacitor close to inductor?
Is it okay to bend the output electrolytic filter capacitor right next to my SMPS inductor?
- 2,079
2
votes
1
answer
296
views
Does "heat" affect signal integrity?
I have a PCB that is having signal integrity issues. This is a four-layer board, the top and bottom layer is signals and power and the inner two layers is a solid ground plane with no breaks in it.
My ...
- 2,079
0
votes
2
answers
76
views
TDM signal conditioning
I'm looking to transmit TDM signals (digital audio) over long-distance cables (around 5 meters). I did some tests with an oscilloscope and the signal is getting too much distortion. I was wondering if ...
- 381
0
votes
0
answers
45
views
Fiber weave effect calculation for a PCB
How can I calculate the angle offset and maximum length?
Here is my stack-up:
You can consider my signal to be routed in layer 3.
Please help in understanding the calculation and concept of it.
- 11
7
votes
5
answers
1k
views
Signal integrity with a gap in the ground plane
I see many people with some knowledge of PCB design, says it is bad practice to run high-speed signals of a "disconnected" ground place adjacent to the signal.
But no one shows practically ...
- 2,079
1
vote
1
answer
78
views
Problems with high frequency SPI
I have what I can best describe as an ASIC (TI's DLPC3420 digital micromirror device controller) communicating with an SPI flash (MX25L1606E).
It first reads a part of the flash at low frequency of ...
- 680
2
votes
0
answers
39
views
Ground isolation in multichannel mixed-signal systems
There are some similar questions to mine but I have a few more specifications on top of them. Therefore, I am not 100% sure whether to ask as an iteration or present my own question on a clean slate. ...
- 121
0
votes
0
answers
53
views
Potential Reasons for Fault on RS-485 Transceiver
I am working with the MAX3441 RS-485 transceiver, but I have run into faults with the three transceivers I have tested, so I am wondering if anyone can shed some insight on potential reasons for the ...
0
votes
0
answers
42
views
MOSI signal losing bandwidth in SPI communication
I am testing the SPI MOSI signal for signal integrity. The length of the PCB trace is 207 mm. Unfortunately, the signal is curved at the rising edge of the cycle. The frequency is 1Mhz. I think it is ...
1
vote
1
answer
45
views
MIPI CSI2 DPHY interface on the long length cable
Now I'm working with MIPI CSI2 DPHY. The situation is the camera and the processor(SoC) are connected using long flex cable(with more than 2 connectors). Due to the MIPI-CSI spec (I ref. from NVIDIA ...
- 13
0
votes
1
answer
63
views
Termination of unused MDI pairs
I'm muxing Ethernet MDI between two PHYs – one of which is 10/100 (2-pair) and the other of which is 1+Gbps (4-pair). A single set of magnetics (4-pair) serves both PHYs via the mux. Does anybody have ...
- 167
0
votes
0
answers
41
views
Poor signal through USB 2.0 Hub IC
I’m using an FE1.1S, using only 2 ports which are connected to a Ublox GPS F9P and another to an STM32.
Connecting it to a computer, the hub and com ports show up just fine and I can connect to them.
...
- 49
1
vote
1
answer
196
views
PCB Bottom layer GND pour some portion not connected to GND plane
Below is the bottom layer of a 4 layer PCB.The stack up is SIG-GND-Power-Signal.
You can see that there is a floating ground whose some portion is not connected to GND plane.
I have shown that in red ...
- 1,767
2
votes
0
answers
36
views
What is the ideal wireless protocol that is best suited for wireless nerve impulse transmission? [closed]
I am working to develop a way to transmit nerve impulses wirelessly (or wired) past a break in the spinal cord. What would be the ideal protocol to effectively relay the signal? Even if the device was ...
2
votes
1
answer
78
views
Programming every other group of two NAND pages Results in Longer Programming Time and Noisy Verification Reads
I'm trying to upgrade the storage in a consumer device by swapping in a larger NAND chip (specifically a Micron MT29F128G08CFABBWP). After modifying the firmware to accept the chip's ID and geometry, ...
- 121
2
votes
1
answer
143
views
MPQ4470-AEC1 Layout guideline clarification
I am using MPQ4470-AEC1 in my design. In the datasheet page no 18 contains the layout guidelines.
I have some questions about guideline no:2 and no:3 .Those guidelines are given below.
Place input ...
- 1,767
0
votes
1
answer
37
views
Ground Relief Gap Design Rule -- Altium
Does anyone know of a way to implement a design rule in altium to check for instances where signals cross over a via relief ground plane gap? Example shown below.
Thanks!
- 172
1
vote
1
answer
59
views
Twisting three signal wires which are carrying a differential signal
I have a driver module came with its differential input signal wires as shown below(red, black, green):
I provide the signal from DAC with diffential outputs.
My question is, since its not twisted ...
- 1,638
0
votes
1
answer
95
views
route on inner or outer layers for SPI clocks signals etc?
What is better for (for example) an SPI clock signal: to be routed on the inner layers (more ground, avoid EMC issue) or on the outer layer? (Avoid changing layers and impedance mismatch and any ...
- 41
0
votes
1
answer
52
views
How to read a TDR report?
This is the report generated from Keysight ADS. I can see the reflections from the vias and layer change (impedance swing) but I couldn't figure out the impedance of the actual traces. Also, why are ...
- 9
0
votes
0
answers
93
views
Trace Width, Length, and Clearance for SATA signals in KiCad PCB Design
I am looking to design a SATA adapter board which interfaces an FPGA LPC FMC connector with a SATA connector. This board will contain the 6 signals (RX+, RX-, TX+, TX-, and Clk+, Clk-) along with ...
- 50
2
votes
1
answer
92
views
Connecting '-' terminal of the power supply to the earth GND
I've already asked a similar question in the past, but I want to make sure I understood things correctly.
Attached is the current lab setup for my chip testing. The green square represents the main ...
- 587
0
votes
5
answers
156
views
Do I need to keep twisted pair ethernet wires consistent down the entire cable?
I have an ethernet cable that is hooked up to a 20 foot long 24 AWG twisted pair cable. The twisted pairs are not twisted to the same wires like in the ethernet cable. Would this be a problem? I ...
14
votes
2
answers
653
views
What is the purpose of the positive feedback in this opamp circuit?
Consider:
Attached schematic is from a broken sampling scope that I have in the lab.
During the reverse engineering the module, I noticed that it uses positive feedback around U2. I understand that ...
- 587
0
votes
0
answers
55
views
USB3.0 Differential Pair Eye Diagram - Transmitter Issues
Used the SI Power Aware analysis on the DP/DM signals for this simulation:
I'm having more issues on my Tx rather than the Rx. I do understand the Rx eye diagram but I'm struggling with the wild ...
- 9
3
votes
1
answer
181
views
Predicting EMI/EMC Issues from Microcontroller AC Spec Rise time fall time
In one of his video Rick Hartley says signals with fast rise time can cause EMI/EMC issues.
I am using FS32K148UJT0VLQT in my design. In my board this controller is working at 5 V supply.
Below image ...
- 1,767
0
votes
4
answers
54
views
Layout guidelines for TCAN1043DRQ1
I am using TCAN1043DRQ1 in my design.
May I know what are the layout guidelines I need to follow.
I checked the datasheet it. It does not say anything about layout guidelines. It tells more about ...
- 1,767
3
votes
1
answer
79
views
Drive strength and termination on a 50MHz multi-card backplane bus
I'm helping someone design a spec for a computing ecosystem based on Z80 and Eurocard. One of the challenges is that we want to support modern Z80 chips clocked at up to 50MHz, which means we have to ...
- 10.6k
0
votes
0
answers
63
views
How power plane acts as a path for the return currents
In some pcb stackup's I can see that the power plane is given as reference to signal layers.
I have some questions regarding this.
May I know in that case how the return current flows.
Assume all my ...
- 1,767
1
vote
2
answers
103
views
Decoupling Capacitor voltage Selection
In my board there are many IC's present and for all these IC's it's manufacturers specified the decoupling capacitors.
When I generated my initial BOM what I observed is 99% of these capacitors are of ...
- 1,767
0
votes
2
answers
240
views
Decoupling capacitor package 0603 vs 0201
I am using microchips SAMA5D27C-D1G-CU.In the reference design all the decupling capacitor package is 0201.
I have the same capacitor with all the specifications suggested by microchip, except package....
- 1,767
5
votes
1
answer
303
views
Does differential impedance matter for USB 2.0 connectors?
On PC motherboards you commonly see 0.100" headers used for USB 2.0 connections, often for a cable running to ports on the front of the PC. Here's an example.
https://www.digikey.com/en/products/...
- 53
1
vote
1
answer
66
views
Ferrite cable core selection best practices for USB 2.0 Full Speed
From signal integrity and best possible EMI suppression perspective should ferrite cable core match the characteristic differential impedance of 90ohms @ 12MHz (for USB 2.0 Full Speed) in order to ...
- 23
0
votes
0
answers
39
views
Multiple inputs for RF/GNSS signal?
What are some ways to support multiple connector types for RF signals without impacting signal quality? For instance, if I wanted to support SMA or MHF1/UFL based antenna.
Below is a picture of an ...
- 49
0
votes
1
answer
87
views
Can these signal traces cause EMI and crosstalk issues?
I have a GND and also a power "plane" pouring on my PCB's top layer.
My signal have to cross between these pourings (around the dotted circle):
Is this considered as a bad practice, and ...
- 947
0
votes
0
answers
47
views
Automotive: VCC and signal filters at each IC?
I'm designing an automotive product (sensors / LTE / GPS / etc). I've taken into account some primary 12V input filtering (TVS, reverse polarity, over-current). Everything works fine on our test ...
- 39
0
votes
0
answers
47
views
How does a via stub cause deterministic jitter?
In a PCB, a via stub is the part of a via that is not used to transport the signal between signal layers. A via stub, as far as I know, can damage signal integrity because of signal reflection: at the ...
- 747
9
votes
3
answers
1k
views
Why are via stubs not avoided?
Via stubs are defined as the part of a via that is not used for signal transmission. Via stubs cause all sorts of problems, but I just don't understand why they happen in the first place.
Can't you ...
- 747
0
votes
0
answers
43
views
Nintendo DS Controller Mod - Daisy Chain issue
This is my first project I've taken on, and honestly it has all gone well until this point and I've learnt so much.
I've gotten permission from the person who designed the PCB, Loopy from 3DSCapture, ...
1
vote
1
answer
52
views
Would more connectors introduce more noise for low-frequency current signal?
General question
When measuring the weak amplitute low-frequency (DC) current signal (in 0.1 - 1 uA) transmitted through FFC cable and connectors to a PCB with transimpedance amplifier (TIA) and ADC, ...
- 133
1
vote
1
answer
80
views
Altium Designer: Is it possible to detect PCB track router over cut in GND plane using DRC?
It is essential that high speed tracks have continuos ground plane with no cuts. This is essential to ensure signal integrity. That being said, can Altium designer use some sort of user defined design ...
- 11.6k
1
vote
1
answer
183
views
PCB via with 50 ohm characteristic impedance
To get specific characteristic impedance on PCB track we have to have carefully controlled distance from GND, PCB track width and track height. OK, clear.
With via the issue is that it is not ...
- 11.6k
2
votes
2
answers
234
views
6 layer PCB stack up and routing strategy
I have a couple of questions about the stack up and routing strategy in a 6 layer PCB.
I'm in the situation where all the important chips are on the top layer, so all the important tracks start and ...
- 778
1
vote
1
answer
210
views
Is PWR plane acceptable as return path for high speed signals instead of GND?
For high speed signals where ωL>>R for the transmission line, the return current becomes concentrated close to the wave guide which is the PCB track. The return path for this current shall be in ...
- 11.6k
2
votes
2
answers
147
views
Optimal 4-layer stack up for high-density board
I have a question about designing a stack up for a 4-layer PCB with a high-density top layer. I know the optimal way to generally do this is to go for either 1 or 2 as these stack ups provide a good ...
1
vote
0
answers
62
views
Altium signal integrity not analyzed
I am new to signal integrity, when I try SI in Altium the model assignments is showing the status as passed and getting the waveforms, when I do Reanalyse design it is showing as not analysed and no ...
- 11
4
votes
3
answers
333
views
PCB Review / Signal Return Path
I'm trying to design better PCB layouts and as for now only work with 2 layers boards.
My question is about the signal return path on this PCB, is the design in the "right" path or I'm doing ...
- 43