Questions tagged [signal-integrity]

Questions regarding how to properly ensure Signal Integrity, protection from noise, shielding, proper pcb layout.

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Eye diagram analyzing for SI analysis

I am performing SI analysis for the GTX transceiver interface. the FPGA that I am using is Xilinx Kintex-7 FPGA. I have received a reference SI analysis report done by customer which has eye width, ...
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1answer
35 views

How to select the correct CM choke?

Say I want to reduce noise on the data line for WS2812B led strips. Is it a viable option to use CM chokes to reduce this noise? According to the docs, WS2812B data speed is 800Kbs. Which I guess ...
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42 views

Why does FPGA PCI Express Tx output have on-chip termination of 100 Ohm?

The Intel Cyclone IV FPGA supports PCI Express (PCIe) generation 1, and the IO standard for the Tx output is PCML at 1.5 V. The Cyclone IV Device Handbook volume 2 page 1-13 describes that the Tx ...
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29 views

Overshoot and undershoot on clock signal missing in high frequency(HyperLynx)

I'm using it for my work in Hyperlynx SI to test high-speed signals. This is a general question but I read somewhere that the simulation in high freq could make a problem to identify some peaks in ...
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26 views

Advice on Noise in Square Input Signal

I am reading the following signal from an open drain output, and trying to read the signal frequency. However, I am getting short spikes in the wave as seen below, and this is messing with the reading ...
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42 views

Conditioning for automotive electronics [closed]

I have a simple application: convert an automotive throttle 0-5V line to 0-2.5V on a circuit near (and feeding into) a fan controller. Very loose maximum frequency is 10Hz. I reduced R1 because the ...
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3answers
50 views

Board to Board Cable Set-up

I've run into a connection between two PCBs, and it's not giving me a warm fuzzy feeling. The master is a carrier board, and the second board is a standalone sensor that communicates over SPI. This ...
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2answers
67 views

Reflection in low frequency conductors (not transmission line)

Is the reflection phenomenon common in RF work with unmatched source/load pairs also present at low frequencies? Or are the wavelengths so much longer than the physical conductor lengths that ...
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37 views

Location of Amplifier for Signal Integrity

Let's say I have a photodiode that outputs a current with respect to incident light on the die. If this photodiode will be located 12 inches or so away from the control board, would it be better for ...
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27 views

Does using a push only plug for and F connector in a coaxial cable decreases the signal or adds noise?

I'm intending to find a replacement cable for my cablemodem unit. The existing cable that the phone company installed is a screw in terminal on both ends of the coaxial cable with one end connected to ...
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2answers
566 views

Effects of test patterns

If I have an 8-bit high-speed interface say at 1GHz talking to memory and I want to do interface testing, I can send patterns like AA/55/00/FF. When I send a pattern like 55 i.e 01010101, every even ...
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1answer
35 views

Signal Integrity with Parallel Switch Control

Please excuse what is likely to be a very basic question, but I am an ME, and this stuff is somewhat magic to me. First, I'll provide a minimal, generic question, and then, for those interested, I'll ...
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1answer
61 views

How to get (with a fixed range and offset) linearly proportional signal from a variable range on the input?

Ask: How to get (with a fixed range and offset) linearly proportional signal from a variable range on the input? Conditions: There's a signal (to simplify, consider a sinusoid) with variable amplitude ...
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How to select the setup time and Hold time for the DDR3/4 SI analysis?

I am performing SI EYE analysis for the DDR3 interface. Following are my consideration for the DDR3 SI analysis:- Data rate= 800MHz/ 1600 MT/s Data UI = 0.625ns = 1/800MHz Address, command and control ...
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67 views

Floating LVDS Input

I am designing a FPGA based receiver for a specific IC, which communicates its data utilizing standard LVDS interface with 100 Ohm termination resistors. The IC has 10 channels (pairs) plus the clock. ...
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3answers
191 views

Will this shottky diode circuit protect my ADC, and if so, are there options with more than 2x channels?

I am trying to read 8x 12VDC digital inputs and 4x 5VDC analog inputs with my 3v3 Teensy 4.0 Microcontroller. In V1 of my design, I used a voltage divider circuit to drop down to 3v3. I would like to ...
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1answer
56 views

Use of twisted pairs with fundamentally single-ended DUT

Let's suppose I'm interested in measuring the voltage response of a DUT to some imposed voltages. The DUT takes V1, V2, V3 as inputs relative to some GND, and outputs V4 relative to the same GND. All ...
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3answers
136 views

A typical GPIO works at 150MHz without risk for EMI but why is there a risk of EMI at even 400KHz in I2C?

In I2C the fall time is restricted to around 20ns as a risk of EMI(Even at 400Khz) but even a normal GPIO works at 150 MHz.Why is this so?
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1answer
72 views

how to understand unparalleled transmission line?

in a normal transmission line example, shown as case-1 in below picture, the signal path and return path are parallel to each other, let's say it takes 1ns for the signal propagate from left side to ...
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1answer
71 views

Controlling a Brushed Motor with DC Voltage to Avoid EMI (no speed control needed)

I have a fairly simple project coming up. My task is to design a system which powers and controls a Pan and Tilt positioner for a camera. It has some weird and unavoidable requirements/constraints: ...
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1answer
36 views

About best way to perfom checksum

From my knowledge,checksum can be done using Xor or adding the bytes of the frame...i have to create a communication between ATmega32 microcontroller and matlab to perform some functions...which is ...
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1answer
2k views

Why are PCIE's coupling capacitors so large

I was looking at the PCIE specification, and I don't understand the requirement for coupling capacitors. For 2.5GT/s, the standard requires AC coupling capacitors of 75nF to 265nF. I tried to ...
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1answer
77 views

Decoupling capacitors on bottom layer in non-BGA packages?

Typical advice on decoupling techniques usually gives highest priority to: always place the decoupling capacitors on the top layer, next to the pins. BGAs of course are a separate issue; I'll come ...
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3answers
64 views

Do parallel LNAs at 90-degrees to eachother reduce the noise floor more than side-by-side?

Wiring amplifiers in parallel in a summing configuration improves the signal to noise ratio because amplifier noise in each LNA is uncorrulated. However, external noise sources will still be a factor ...
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1answer
42 views

How to avoid RF signal loss in a conductive cage acting like a Faraday shield?

I have a standard chip antenna mounted on a large ground PCB plane. The product is unfortunately encapsulated inside a relatively open (carbon-fiber) conductive cage. Unfortunately, I see an obvious ...
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0answers
81 views

Why DDR4 Specs recommend that Address, Control and Clock buses be referenced to VDD?

Micron's Technical Note TN-40-40: DDR4 Point-to-Point Design Guide, page 19, says (emphasis mine): Timing Budget Suggested practice is to look at the design from a timing budget standpoint to provide ...
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1answer
35 views

Should I avoid a switching frequency close to my target SPI or CAN frequency?

I have a kind of an open-ended question. If I'm designing a board with a buck converter and have picked out my peripherals, and say for example I want to run my CAN FD interface at 1MHz baud and maybe ...
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73 views

Is this differential pair routing OK?

I am working on a PCB layout on a very space constrained, 4-layer board. On the board is a MIPI-output image sensor (1 lane) which go to an FPGA. Layer 1: Image sensor Layer 2: Full Gnd plane Layer 3:...
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1answer
58 views

Should via use be used when it is not essential?

I am working on characterising a transistor at approximately Vds=1000V and Ids=100A pulsed at around tON=20ns. Should the power and ground paths (Top and Bottom layers) have vias connected to the ...
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2answers
36 views

Signal line current estimation and impedance matching

As far as I know, the input pins to ICs are typically just the gate of a MOSFET. I have always just take stuff for granted (like if you want to control a logic pin, just put a source voltage on it), ...
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1answer
34 views

How to make sure you have “adequate” ground in a self-enclosed portable circuit?

How to make sure you have "adequate" ground in a self-enclosed portable circuit? I read that a good ground ensures steady signals. But, if you run a circuit from a battery it is not connected to ...
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1answer
20 views

RS-485 device to RS-232 adapter MUXing not working as expected

I have a RS-485 device that returns serial ASCII constantly. As the device might near very high voltage or electromagnetic areas, I need to ensure the RS-485 to RS-232 adapters I've been supplied with ...
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3answers
112 views

How do bypass capacitors recharge in high-frequency if the PCB can't deliver high-frequency currents?

I understand the whole theory behind bypass capacitors, how they are necessary to deliver high-frequency currents to the IC, as the PCB in general has high-inductance, thus high-impedance in high-...
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1answer
18 views

Touching MOSI on RJ45 connector cleans bus noise

I am using a STM32F767ZI-Nucleo development board from ST. i'm using it to communicate by SPI with a UM7 orientation sensor board. There a register to read in the FW version. Normally I only receive ...
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1answer
208 views

When to Remove the Ground Plane under SMD components for High-Speed Signals?

I'm reading TI's recommendations on routing high-speed signals. Most of the guidelines are common sense, but there's one guideline that I haven't read before: It recommends completely removing the ...
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1answer
44 views

Self solder 8-pin din cable

a bit of specific question. I want to build my own cable based on pins stated in the manual of an old camera, so I can capture the video (composite video) and audio signal. Question: Is there ...
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1answer
277 views

Is it a good idea to connect ethernet cable's shielding to PCB GND?

Background My project is split over two PCBs for convenience. The first PCB adapts an input signal and converts it to a low-voltage differential signal. There are 4 channels to be measured, so 4 ...
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2answers
73 views

ADC signal conditioning circuit

I have a circuit that is fed into a ADC chip (adc128s022), that I am trying to understand. The sensors are inferred gas sensors. Could you please criticise my analysis. The way I am reading it: ...
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61 views

Quadrature Encoder output overshoot

I have a Faulhaber 1717T006SR DC motor with a build-in quadrature encoder. Here is the relevant bit of the datasheet for the encoder. The encoder outputs are 5V. I want to interface this with an ...
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3answers
136 views

Signal return path between circuits with separate full-bridge rectifiers

Edit: I think I've figured out WHY this is happening (see my answer below), but I still would love to hear ways to mitigate this issue. I've got two microcontrollers that are powered by the same dc ...
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1answer
196 views

Is it better to route Ethernet on the top layer, or to use vias?

I'm making a circuit board with Ethernet (PoE if that makes a difference) coming in through an M12 connector, passing through magnetics and a PHY and going to a micro. I've always heard that there are ...
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5answers
1k views

Detection of signals buried in noise

This is more of a general question to see which methods are the most common to improve the detection of a signal which is buried in noise. Currently, we are building an optical system for medical ...
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1answer
59 views

phy chip straping pins

as you can see options strapping pins are multiplexed with RXD# pins .. which are MII interface pins. this will make the PCB have "stubs" (connected to MAC + pullup resistors) which is not good in ...
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4answers
149 views

Why longer stubs cause more intense ringing?

Why connection of longer stub lengths cause more intense ringing in a Communication Network like CAN? As stub lengths increase won't the attenuation increase and lead to less ringing? Also the time ...
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4answers
162 views

Why is the amplitude of ringing in square wave independent of frequency of square wave?

Reflections in a transmission line is causing ringing in square wave because certain frequencies are getting enhanced, but when frequency of the square wave changes won't the amplitude of those ...
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1answer
84 views

Does the standard termination of 120 ohm really suppress reflections in recessive state in CAN?

Suppose we have a multi-node CAN network with the ends of transmission line terminated with the standard 120 ohm. When the recessive state is on the transmission line, the voltage on both CAN_H and ...
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5answers
3k views

Physics behind signal reflections and series termination

I have been looking for cause of signal reflections in transmission lines. Everywhere it is concluded that the reason is impedance mismatch. I can understand if the impedance changes in the path of ...
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70 views

Questions on ringing over square wave in transmission line

Considering a transmission line with open circuit termination at one end and a square wave voltage source with impedance not matching the characteristic impedance at the other end. Because of ...
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1answer
47 views

How will the proper termination at one end while the other end is kept open avoids reflections in transmission line?

Consider a transmission line which is terminated with characteristic impedance at one end but other end is kept open, the reflections are not observed. I don't understand the mechanism behind. Please ...
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1answer
58 views

9-pin micro-d connector for LVDS signals

Has anyone utilized 9-pin micro-d connectors for driving and receiving LVDS signals? I am running the LVDS at 100 Mbps for 20-30 inches. I am using a vertical pcb mounted connector 380-009-213 from ...

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