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Questions tagged [signal-integrity]

Questions regarding how to properly ensure Signal Integrity, protection from noise, shielding, proper pcb layout.

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Jumper on 100 Mbps Ethernet

Is it possible to pass a 100BASE-TX signal (100 Mbps Ethernet, over 2 differential pairs) through jumpers (one per wire), in order to allow the user to select Ethernet or serial for a given connector? ...
Sandro's user avatar
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2 votes
1 answer
129 views

Unexpected Loss In Signal Integrity

For a project I'm working on, I wanted to clone this e-paper driver board and eventually integrate it into my project's board. Here's a part of the schematic: However, with my custom prototype clone ...
uzumaki's user avatar
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3 votes
0 answers
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How are pad impedance discontinuities precisely compensated for in high speed PCB layouts?

I stumbled across a recommendation in an 850MHz opamp datasheet that said the following: All ground and power planes under the input and output pins must be cleared of copper to prevent the formation ...
Polynomial's user avatar
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2 votes
4 answers
108 views

Opamp dual package IC configuration

I have a question regarding the configuration of opamps for sensor signal amplification. I have a circuit with two sensors going through identical signal conditioning circuits (amplification and ...
enrico's user avatar
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1 vote
1 answer
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How to deal with routing of distributed signals

How to connect some signals that have many branches, such as SPI & I2C, such as clock? Does it have any special principles and methods? I have read some things, but my information is incomplete.
hossein hamzekhani's user avatar
2 votes
1 answer
182 views

Partially nice waveform on debugger pin

I am looking at the waveform on my SWDIO pin during programming and most edges look very nice, but some do not. Is this likely to be problematic? What are probable causes?
Alexander Ohm's user avatar
1 vote
1 answer
43 views

TDM signals crossing

I'm working on a 2-layer PCB design and trying to do the best I can for signal integrity. I have 2 TDM lines and at a certain point they cross between each other. See image below. Is this likely to ...
Emerson's user avatar
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0 votes
1 answer
67 views

Should I connect my mechanical spacer pad to GND?

Is there any advantages for connecting the mechanical spacer pads on the corners of the PCB to GND? 2D view: 3D view:
Andromeda's user avatar
  • 477
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2 answers
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Using transfer via in PCB

From which frequency we need to consider a transfer via, when there is a transition of a signal on different layer in a PCB? higher than 1GHz? I need to know the threshold for considering these types ...
Andromeda's user avatar
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0 answers
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Noise in audio amplifiers when touching the smartphone touchscreen as an audio source

While observing the audio output of my smartphone on the oscilloscope, I noticed a signal being generated when I touch the touchscreen. This signal is around 500Hz and appears in groups of 3 peaks, ...
boromyr's user avatar
  • 53
0 votes
1 answer
98 views

How can I measure a 100 MHz signal with unknown source impedance with an oscilloscope?

As a part of a device I designed, I have to measure multiple higher frequency square wave (and sinusodial) signals with unkown source impedance. The intended signal path is shown in the picture: My ...
Robert's user avatar
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2 answers
99 views

Differential line driver built with discrete components

I need to establish an SPI communication over one meter in a very noisy environment. To do this, I am planning on using differential communication over a twisted pair cable. I would use a dedicated IC ...
zeeman_effect's user avatar
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Operation amplifier optimized layout- Noise- Signal Integrity

I was watching a seminar from Fedevel academy, in this seminar as all the datasheet has mentioned, we need to remove GND and PWR plane underneath the negative inverting pin and the output pin of the ...
Andromeda's user avatar
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0 votes
2 answers
79 views

CAN Protocol traced routed with 90 ohm characteristic impedance

I am using ISO1042BDWV in my board. The schematic is given below. I know that the characteristic impedance of the CAN bus is 120 ohm. The layout team routed CANH and CANL as 90 Ω differential. The CAN ...
Confused's user avatar
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0 votes
2 answers
109 views

Reflection on PCB + antenna

I have a transducer with 64 outputs. I want to have 3 of the outputs on my amplifier input in a way that I can choose between them. My first idea for implementing this was to use jumpers as follows: ...
Andromeda's user avatar
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1 answer
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Sony IMX421 Eval board with IMX422 Sensor - produces odd repeating patterns instead of true images

I am working on an application that involves use of a Sony IMX422 CMOS image sensor - namely writing VHDL code to act as a receiver interface to the sensor over an SLVS bus. the setup involves a ...
CNfan's user avatar
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0 answers
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I need to drive 4 12v dc encoder motors from one controller

In addition to the motors, there are two momentary button switches for each, and an N/O limit switch. Each Motor is twelve feet from the controller. I plan to run a 10 conductor 22 ga cable to ...
WouldRatherBuildAMotor's user avatar
1 vote
1 answer
129 views

24MHz Clock Signal Distortion

I am measuring a 3.3 V 24.576 MHz clock signal coming from a CDCE913. The signal is used to drive 25 audio TDM receivers. The line is terminated in series with a 33 ohm resistor at the transmitter end ...
Semmelrinde's user avatar
3 votes
1 answer
265 views

Anti-aliasing filter for 3.3 V ADC at 1 MHz

I am designing an anti-aliasing LPF for a 16-channel ADC on a custom STM32F415-based board. This design will ultimately be put on a car and used as a DAQ. I am planning on running the ADC with a 30 ...
ABashara's user avatar
3 votes
3 answers
753 views

Return current on PCB

As PCB designers we all know that for high frequency signal (MHz), we should design return path (reference GND plane) underneath the signal as follows: https://www.allaboutcircuits.com/technical-...
Andromeda's user avatar
  • 477
1 vote
1 answer
51 views

Coax cables and input impedances

I'm doing a voltage measurement with the help of an Active Differential Probe (TESTEC TT-SI 9010) with an output voltage of +-7V. This voltages have rise times of the order 500ns. The set up looks ...
Santi Ospina's user avatar
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0 answers
42 views

EMI performances observed better for stripline routing with pth rather than stripline with blind via

The circuit is: A fast switching driver (Lvth buffer) is transmitting a signal to Leon processor receiver and it also has a series termination. Stackup: top(L1), gnd, sig1(inner lyr3), 2.5V plane, ...
Ankita Sinha's user avatar
22 votes
2 answers
5k views

100 MHz probe and 200 MHz probe show very different waveform on 1 MHz signal

Recently I purchased my very first scope and noticed something I'm really curious about its cause. It's a 100 MHz scope, when I was testing to see the ringing of a 1 MHz clock signal with different ...
Jimmy.D's user avatar
  • 569
1 vote
0 answers
62 views

3m unshielded 3V3 UART

I have a product that probably uses the wrong digital interface, but I'm trying to make it work anyway. Differential signalling, a better cable and other things would be desirable, but that is outside ...
Alexander Ohm's user avatar
0 votes
2 answers
98 views

Low drive strength of level shifter

What part of a level shifter datasheet indicates drive strength? I have an MCU and sensor connected over UART (115200 baud). The MCU is 3.3V and the sensor is 1.8 V, so I'm using a level shifter in ...
Alexander Ohm's user avatar
1 vote
0 answers
85 views

Most efficiently adapting IPEX-MHF1 (Wifi-Card) to IPEX-MHF4 (Antenna)?

We have a lot trouble with the windows driver our Intel Wi-Fi 6E AX211 Wifi-cards. It randomly looses connection and it's a general problem, that a lot of users ...
Tomblarom's user avatar
  • 111
1 vote
0 answers
27 views

Simulating and verifying DDR3L clock

Context I am working on a PCB that hosts a Zynq Ultrascale+ SoC and has 9 DDR3L SDRAMs (MT41K512M8DA) operating at 1866Mbps, and I have to verify the signal integrity of the DDR3L interface. I am ...
tklu123's user avatar
  • 11
0 votes
0 answers
34 views

Deembeding S-parameters

I have a deembed S2P(S-parameter) file of the probe and output waveform of the probe. I need to get back the waveform at the probe point by passing the output waveform through the deembed S2P file. ...
Ngprasad's user avatar
0 votes
2 answers
141 views

TFP401PZP: Unable to get proper video output, ghost screen/distorted pixels

I have designed my own display driver board using a TI TFP401PZP TMDS DVI receiver/deserializer which is connected to a 24-bit, parallel RGB, 7 inch capacitive touch display with a resolution of ...
Aryan's user avatar
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1 vote
0 answers
38 views

What on earth could be causing MIPI frame drops?

In a project I'm working on, we're seeing regular frame drops on a 1-lane, 900Mbps MIPI CSI-2 interface. After some investigating, I'm fairly sure that the problem is related to signal integrity. ...
Rocketmagnet's user avatar
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1 answer
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Do I need to provide a decoupling capacitor network for all the power pins of a microcontroller?

I am using PIC32CZ8110CA90208-I8MX-SL3 in my design.The power supply section is given below. You can see that it has: AVDD 1 pin VDDIO 15 pins VDDREG 3 pins Do I need to provide a separate ...
Confused's user avatar
  • 2,593
0 votes
1 answer
70 views

RCA coax end termination

I am building an amplifier that takes in an RCA output from a TV. From my general understanding, RCA coaxial cables typically have an impedance of either 50 Ω or 75 Ω and a small amount of capacitance ...
lemon's user avatar
  • 590
4 votes
3 answers
676 views

How to space stitching vias to avoid affecting the power plane?

On a four-layer with the standard sig gnd pwr sig stackup, when flooding top and bottom layers with copper and stitching them to the ground plane, I know the standard rule is lambda/20 spacing for the ...
John Arg's user avatar
  • 209
1 vote
0 answers
92 views

FRC (Ribbon Cable) vs CAT6 Cable Signal Integrity

How bad would a 10-pin FRC perform w.r.t. a CAT6 cable in terms of signal integrity? I know CAT6 is any day superior, but I want to know by how much. Using CAT6 has been a pain for me. Crimping those ...
Bubu's user avatar
  • 399
0 votes
3 answers
97 views

AD application note MT-097

Below is the statement from AD application note MT-097. I have see this explanation many places. But no one explains how transmission line effects comes when rise time is smaller than 2*times ...
Confused's user avatar
  • 2,593
0 votes
2 answers
173 views

What is the best way to use 0 ohm resistors for a large number of signals?

I'm fairly new to PCB design, so maybe I start with a basic 0 ohm resistor like this: I have both output pins (SLEEP & RESET) on the DAC chip. I want to have two options on my PCB, one with 3-pin ...
johnny_1010's user avatar
2 votes
1 answer
194 views

Simulation of pulse through transmission line with IC load with ringing

There is a pulse going through a transmission line. There is a phenomena where if we put a pulse through a transmission line then after it reaches the IC we can have ringing instead of good pulse. In ...
Josh23's user avatar
  • 1
1 vote
1 answer
138 views

Common mode choke placement for good EMC performance

I am interfacing a deserializer with Quectels smart module. The CSI lines of the deserializer are connected to the CSI lines of smart module. A common mode choke is placed in between them. The ...
Confused's user avatar
  • 2,593
2 votes
1 answer
168 views

Is it a good idea to place SMPS output capacitor close to inductor?

Is it okay to bend the output electrolytic filter capacitor right next to my SMPS inductor?
JoeyB's user avatar
  • 2,389
2 votes
1 answer
370 views

Does "heat" affect signal integrity?

I have a PCB that is having signal integrity issues. This is a four-layer board, the top and bottom layer is signals and power and the inner two layers is a solid ground plane with no breaks in it. My ...
JoeyB's user avatar
  • 2,389
0 votes
2 answers
116 views

TDM signal conditioning

I'm looking to transmit TDM signals (digital audio) over long-distance cables (around 5 meters). I did some tests with an oscilloscope and the signal is getting too much distortion. I was wondering if ...
Emerson's user avatar
  • 423
0 votes
0 answers
54 views

Fiber weave effect calculation for a PCB

How can I calculate the angle offset and maximum length? Here is my stack-up: You can consider my signal to be routed in layer 3. Please help in understanding the calculation and concept of it.
Ram_R's user avatar
  • 11
7 votes
5 answers
1k views

Signal integrity with a gap in the ground plane

I see many people with some knowledge of PCB design, says it is bad practice to run high-speed signals of a "disconnected" ground place adjacent to the signal. But no one shows practically ...
JoeyB's user avatar
  • 2,389
1 vote
1 answer
126 views

Problems with high frequency SPI

I have what I can best describe as an ASIC (TI's DLPC3420 digital micromirror device controller) communicating with an SPI flash (MX25L1606E). It first reads a part of the flash at low frequency of ...
DELTA12's user avatar
  • 868
2 votes
0 answers
60 views

Ground isolation in multichannel mixed-signal systems

There are some similar questions to mine but I have a few more specifications on top of them. Therefore, I am not 100% sure whether to ask as an iteration or present my own question on a clean slate. ...
falsterbo's user avatar
  • 121
0 votes
0 answers
121 views

Potential Reasons for Fault on RS-485 Transceiver

I am working with the MAX3441 RS-485 transceiver, but I have run into faults with the three transceivers I have tested, so I am wondering if anyone can shed some insight on potential reasons for the ...
SubjectFocused's user avatar
0 votes
0 answers
47 views

MOSI signal losing bandwidth in SPI communication

I am testing the SPI MOSI signal for signal integrity. The length of the PCB trace is 207 mm. Unfortunately, the signal is curved at the rising edge of the cycle. The frequency is 1Mhz. I think it is ...
Lifeshack Radio's user avatar
1 vote
1 answer
640 views

MIPI CSI2 DPHY interface on the long length cable

Now I'm working with MIPI CSI2 DPHY. The situation is the camera and the processor(SoC) are connected using long flex cable(with more than 2 connectors). Due to the MIPI-CSI spec (I ref. from NVIDIA ...
owl_hor's user avatar
  • 13
0 votes
1 answer
140 views

Termination of unused MDI pairs

I'm muxing Ethernet MDI between two PHYs – one of which is 10/100 (2-pair) and the other of which is 1+Gbps (4-pair). A single set of magnetics (4-pair) serves both PHYs via the mux. Does anybody have ...
foxtrot's user avatar
  • 167
0 votes
0 answers
50 views

Poor signal through USB 2.0 Hub IC

I’m using an FE1.1S, using only 2 ports which are connected to a Ublox GPS F9P and another to an STM32. Connecting it to a computer, the hub and com ports show up just fine and I can connect to them. ...
Sean's user avatar
  • 169

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