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Questions regarding how to properly ensure Signal Integrity, protection from noise, shielding, proper pcb layout.

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1answer
18 views

Difference between conventional Eye-diagram voltage plot and “Eye-density” plot in ADS Keysight Simulation

I know what is eye diagram. It is the sampled voltage plot at the clock frequency (Usually) of my circuit and superimposed. If the logic 0 corresponds ...
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4answers
42 views

Single voltage power supply to +/- rails

I have a wall wart coming into my circuit in the DC barrel jack shown in the picture. I want to have a positive and negative rail for my op amps as I am unsure of the effect of biasing my signal lines....
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1answer
54 views

Gounding for EMI and signal integrity - LED Matrix multiboard design

I would like to implement a LED Matrix circuit like this one, where the LED matrix enclosed within the blue dots will be on a seperate PCB than the rest of the circuit. Since this will be a ...
1
vote
1answer
74 views

How to route a nasty signal (200V/µs)?

I have to route this signal for a distance of ~70mm† through a dense (mostly digital) 2-sided board. The signal is generated externally and I have no control over its shape, it's basically a pulse ...
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2answers
105 views

What does it mean if eye diagram voltage (0 and 1 level) goes negative?

I have created a differential channel and was testing the channel with simple testbench to check the eye diagram. Now I know the channel performance is very bad (It of several PCB transmission lines, ...
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2answers
92 views

High Speed Signal on Large Circular Ring

It's frequently communicated that when working with signals in the Ghz range, routing is extremely important to signal integrity. Pretty much any inclusion of unnecessary stubs is out of the question, ...
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1answer
47 views

Connecting LVDS signal from one PCB to another

I am tryin to connect LVDS signals on one PCB to another. I am using an FFC cable and am trying to understand if signal integrity would become an issue. The shortest FFC cable that I could find is ...
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0answers
38 views

Remote triggering by using optoisolators

I need to hardware-trigger three modules from a pulse signal source. According to their data-sheet each module requires between 5 to 15V for trigger high and 0 to 5V for low. Each module draw around ...
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2answers
37 views

Understanding a common mode signal conditioning module

As far as I understand, normally an ideal differential amplifier(or an instrumentation amp) can reject common mode(CM) voltages up to around its rail voltages. Let's say the rails of the diff. amp ...
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4answers
97 views

Effect of cable capacitance to low frequency analog voltage signal transmission

Regarding sending a low freq. (<150Hz) analog voltage signal with CAT6 STP cable I have heard that: if the frequencies down the cable will be low, there may be an issue with it driving a capacitive ...
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5answers
100 views

Sensor question for low freq

A floating DC voltage output sensor will be powered locally and the signal will be sent outdoors 200 meters far away to a data acquisition board. I didn't receive the sensor yet and don't have the ...
1
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1answer
22 views

Output impedance imbalance and CM noise in truly floating sources

In the following Figure 1 and Figure 2, the sensor is the one in dashed box. The output impedance of the sensor is big and in this case is 1k Ohm. And as you see regardless of the sensors are bipolar ...
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1answer
25 views

Comparison of two configurations to balance source impedance

This is a generic question for about frequency sensors. But as an example I use this sensor which has around 1k output impedance. So in below drawing the source in dashed box has 1k output impedance: ...
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3answers
74 views

Should a trace be connected through multiple pins on a pin header?

I'm designing a modular board, where the two modules are connected through pin headers. For mechanical stability I have more pins than traces and my question is that which is the better: route each ...
2
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1answer
63 views

Why doesn't smaller Transmission Lines affect Signal Integrity? [duplicate]

I am reading High Speed Digital Design: A Handbook of Black Magic. It was mentioned that if length of transmission line (Microstrip or stripline) is less than 1/...
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2answers
129 views

Multiboard Grounding In High Frequency

How can ground loop be avoided when connecting two system with same ground. This happen in PC whith SATA cable or PCIe Card with seprated power cable. My System Board: I have two pcb each with a ...
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2answers
45 views

Signal Integrity

I am working on signal integrity of the PCBs. I have some misunderstanding in handling High frequency signals. Resistance and Inductance increases with high frequency signals. so we have to take while ...
5
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2answers
471 views

Ethernet RMII on two layer PCB

INTRODUCTION: I'm aiming to design an Ethernet connected system as a hobby ( ie. plenty of time but not wishing to spend much ). My design constraints would ideally be sticking to a 2 layer 100mm x ...
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4answers
115 views

How should I connect my PCBs? [closed]

I will need to connect several PCBs within a single enclosure for the project I am working on (They are split to reduce cost should there be a manufacturing error). I need to connect an I2C Bus, 5V , ...
0
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1answer
34 views

If two iBeacons are too close to eachother, could their signals get confused for one another?

I have a simple question that I can't find the answer to. I am testing an app with some iBeacons, and I observe that one of my iBeacons never begins to range...the region is monitored, its just not ...
0
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1answer
92 views

Connecting two USB 2.0 devices to a single USB port on an MCU

I'm designing a PCB where I need to have two possible USB 2.0 connectors (and hence 2 sets of diff pairs) connect to a single USB 2.0 port on an MCU. Only a single connector would be used at any given ...
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2answers
87 views

The probe and Oscilloscope selections for measurement

*I searched about the correct oscilloscope and probe to measure the a signal with a certain frequency. I read some documents and white papers about this topic. I have heard some "rule of thumbs" about ...
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0answers
50 views

Measured my PCB with Handheld LCR Meter - can you tell me anything?

This is a 5x4cm 8-layer PCB. It has 2 sets of dedicated VCC/GND planes plus ground plane polygons on top and bottom. It is not high speed. The top digital speed is 1Mhz SPI. It has 3 micros running on ...
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3answers
221 views

Connecting signal to multiple summing amplifiers

For a normal op-amp inverting summing amplifier, each signal is tied to the negative input of the op-amp. Imagine the scenario where I have three signals. In adder 1, I want to sum A and B. In adder 2,...
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1answer
117 views

Cyclone V data corruption at high frequency

I'm currently trying to implement a FPGA design using a 325 MHz clock, which writes to the SDRAM Controller of a Cyclone V 5CSEBA6U23I7 (Speed Grade 7). When running my IP Core with 2 MHz everything ...
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2answers
95 views

PL9823 data line corruption when using 3v3

This is my schematic: The PL9823 uses the same protocol as WS1012 (NeoPixel) When using 5V MCU and 5V to power the LED everything works OK. When using 3v3 MCU and 3v3 to power the LED everything ...
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1answer
57 views

Reflections of Low bit rate signal and High bit rate signal

I was reading wikipedia page on Signal Integrity and got stuck with this paragraph. It says: The channel flight time (delay) of the interconnect is roughly 1 ns per 15 cm (6 in) of FR-4 stripline (...
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2answers
1k views

Will a 75ohm cable work with (not break) a 50ohm gsm shield?

I need to have a long (100') stretch of cable from my antenna to a GSM box (remote control for heating via GPRS or SMS), and I need to minimize signal loss. In another (totally different) question ...
7
votes
1answer
141 views

USB 3.1 over PCIe board edge connector

I am designing a system with a carrier board that has all of active logic on one board and most connectors on a backplane board. The interface between the two boards is a x16 PCIe board edge connector....
11
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7answers
2k views

Good uses for 1:1 probe

We all know why using a properly compensated 10:1 probe is a must when viewing MHz-speed signals on a scope with a 1 MOhm input impedance. Now who can supply a good use for a 1:1 probe? These probes ...
6
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1answer
537 views

Why is the signal amplitude low on the oscilloscope even though the impedance is matched?

I have a photodetector with differential outputs that are each 50-ohm terminated. When I connect one output to the oscilloscope to look at the signal, I see a higher signal amplitude with higher ...
0
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1answer
58 views

ADC signal long trace voltage drop compensation using amp and return trace

I'm running a signal for an ADC a pretty good distance and through a connector. The voltage drops are not unsubstantial. The concept is to run an identical return trace and compare the post-loss ...
0
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1answer
40 views

SoC Digital Output Rise Time

I'm interested in calculating series termination resistors for my communication lines for a system I'm designing based on the Zynq-7000 SoC. The system runs on a 33 MHz clock but I'm sure the ...
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vote
1answer
223 views

RS485 waveform distortion

I was checking RS485 signals with an oscilloscope and saw some waveforms which look distorted (see right side of image PIC1). See schematic for test points TP1, TP2. Setup Probe 1:- TP2 and GND ...
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3answers
134 views

SAR ADC has non-linearity around the middle of the range

I'm using a SAR ADC in STM32L433 chip and it exhibits a strange nonlinearity around the middle of the range which I can't explain. It's a 12bit ADC with 64x oversampling and 2 bit shift which ...
0
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1answer
69 views

differential pair radiation

For experienced designers probably it is easy question but I am reading "Signal and Power integrity, E. Bogatin" and don't understand one thing. "The two most common sources of EMI are the ...
0
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1answer
64 views

How to select the model selector for TI IBIS model of DRA725?

Following is the IBIS model selector section for the DRA725 SoC in IBIS file. Currently, I do SI analysis of DRA725 with Mentor HyperLynx SI, Intention is to select the right model selector. What to ...
0
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1answer
122 views

JTAG Programmer using Zedboard - Signal Integrity problems?

I am trying to build my own JTAG programmer using the Zedboard but I am stuck with hardware issues. For the Zedboard side, I am using the Pins XADC-GIO0, XADC-GIO1, XADC-GIO2 and XADC-GIO3 as TCK, ...
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1answer
87 views

Confused with understanding a recommended signal conditioning interface

I will make an interface for a 10k wind-vane recommended in this document. I will follow the recommendations but I don't understand the explanations of the document and I have at the end four short ...
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0answers
54 views

HCMOS Oscillator pull up / down resistors

I am new in this forum, I will listen and thank all your support. My goal is to know how to design the oscillator output resistors to enhance / optimize clock signal performance. I have been working ...
0
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0answers
56 views

DDR threshold levels and timing constraints

I am new in field of DDR and high speed memories, i come across SSTL signaling level diagram, over there VIH & VIL are defined as both DC and AC. What is the difference between them, what is the ...
0
votes
0answers
70 views

Discrete DDR3 Layout Check

I have 8 chips of 512 Mb DDR3 interfaced with the processor with point to point Data & fly by Address/command topology. I need to remove 1 DDR3 & keep it unmount. The rest 7 DDRs should work ...
1
vote
2answers
2k views

Why is length matching important for high-speed signals?

Broadly speaking, I understand that PCB trace length matching is important from signal timing and signal integrity point of view, but I want to know some more specifics about these two parameters and ...
2
votes
1answer
297 views

Shielded breadboard jumper cable wires

Does it exist a shielded version of 2.54mm pitch breadboard jumper cable wires? Thin flexible wires, Gauge AWG 24-28. I want use shielded wires for JTAG cable, to reduce electrical noise from ...
1
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1answer
91 views

Slew rate limiting of bidirectional lines

Assuming the ICs in use don't offer an adjustable slew rate, if I want to limit the slew rate of a unidirectional digital data line, for example of SPI's MOSI-signal, I can put a series resistor at ...
2
votes
1answer
39 views

How can I control the route to analyse with HyperLynx in a switch?

Good day to everyone. I recently started using HyperLynx from Mentor and I'm having difficulties in analyzing the signal-integrity of the signals due to having switches in the circuit. When I load ...
11
votes
1answer
1k views

CAN bus signal integrity

The channels are CAN_H (red), CAN_L (blue), and CAN_H-CAN_L (brown). It can be observed in the diagram below that CAN_H-CAN_L has an acceptable signal shape. However, both CAN_H and CAN_L look poorly ...
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1answer
54 views

Compute loss/inch for (differential) T-line from s-parameters?

I have the 4-port s-parameters of 2 PCB boards, where each board consists of a differential transmission-line with SMA connectors on either end. The only difference between the boards is their trace ...
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3answers
589 views

Does a BNC splitter introduce defects into the signal?

I'm currently doing some contract work that includes finding and recommending a signal generator model for frequency measurement device verification. The verification scheme requires generating a ...
3
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1answer
459 views

SPI signal integrity issue

I have a custom four-layer PCB (Signal, Ground, Power, Signal) with an STM32F4 (72 MHz) connected to a Si4684 receiver and a Si4711 FM transmitter through SPI. It seems that my design has some ...