Questions tagged [signal-integrity]

Questions regarding how to properly ensure Signal Integrity, protection from noise, shielding, proper pcb layout.

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45
votes
3answers
30k views

Why are vias placed this way on a PCB?

I used to check complex commercial PCBs specially those of graphics cards to see how professional PCB designers do their layout and learn from their techniques. When I checked the card shown below I ...
35
votes
8answers
67k views

Why put a resistor in series with signal line?

A lot of times in circuits I see a resistor placed in series in a signal line and sometimes even in series with an MCU's VDD line. Is the intention of this to smooth out noise in the line? How is this ...
24
votes
4answers
10k views

Short Distance Board to Board Communication

My MCU runs a SPI bus with about 4 devices. I'd like to extend this bus to be off board as well i.e. have some PCBs connect to the "main" board and extend the functionality. The "pad to pad" distance ...
24
votes
5answers
60k views

How termination resistors work; what happens if I use lower values?

I am going to try to interface low-speed 8bit DDR2 chip to FPGA, and I've got some questions crucial to make it work :-) Is that correct that the idea of termination resistor is to sink most of the ...
18
votes
3answers
7k views

What problems could occur when chaining 40 shift registers?

I'm planning on chaining together 40 x 74HC595 shift registers. The whole chain of 74HC595s will be controlled by a 5 V microcontroller, which will generate the SDI,...
12
votes
7answers
10k views

Trace crossing splitted power plane

Most sources on the internet discuss routing signals over a split power plane and how to do this properly. The main solution here is to create a short return current path. I'm wondering whether ...
4
votes
1answer
1k views

Dealing with splits in my ground plane

Whenever I'm making a cheap, 2-sided PCB, I run into this problem: Where I have signal lines (on the top layer here) running over top of a big fat power trace (on the bottom layer). Now, this is ...
6
votes
4answers
9k views

PCB Signal Bus design

I have a pcb with a SPI bus with several sensors that have to be connected to this bus. Since 90 degree traces are not recommended in a proper PCB design I ask myself how to connect so many sensors ...
9
votes
3answers
8k views

What is the effect of supply voltage asymmetry in opamp amplifier topologies?

What is the effect of a \$\Delta V\$ voltage shift in one of the supply voltage inputs of an opamp on its functional behavior (\$\Delta V\$ can be positive or negative)? Suppose that, I'm designing a ...
1
vote
3answers
3k views

How to select source termination resistors by looking at signal?

If I have two devices that some distance apart on a fairly large PCB (could be 1 in, or it could be 20 in). If I arbitrary select a value for R1, lets say 33 ohms in this example and if my digital ...
1
vote
5answers
126 views

Sensor question for low freq

A floating DC voltage output sensor will be powered locally and the signal will be sent outdoors 200 meters far away to a data acquisition board. I didn't receive the sensor yet and don't have the ...
1
vote
2answers
167 views

digitaly controlled voltage divider for picky audio recording enthousiasts

I want to replace expansive multi-deck rotary switches with a micro-controller and digitally controlled (i2C or ISP) analog switches. It will be used in a vintage (1972) discreet transistor ...
0
votes
0answers
49 views

Remote triggering by using optoisolators

I need to hardware-trigger three modules from a pulse signal source. According to their data-sheet each module requires between 5 to 15V for trigger high and 0 to 5V for low. Each module draw around ...
16
votes
5answers
3k views

Physics behind signal reflections and series termination

I have been looking for cause of signal reflections in transmission lines. Everywhere it is concluded that the reason is impedance mismatch. I can understand if the impedance changes in the path of ...
13
votes
1answer
4k views

Why does reflection off a PCB via look like this?

My question is related to http://mobius-semiconductor.com/whitepapers/ISSCC_2003_SerialBackplaneTXVRs.pdf. On the page 18 there are a few figures of "TDR off Diferent Types off Vias". I am confused ...
11
votes
1answer
4k views

What separates a “good” eye diagram from a “bad” one?

I'm running some USB verification testing at work, and the Agilent oscilloscope I'm working with returns a nice summary of pass/fail statistics along with a pretty eye diagram. Since the pass/fail is ...
6
votes
4answers
3k views

Best way to learn Signal Integrity [closed]

I am currently working on ECAD. Just to add more technical values to my work, I want to learn Signal Integrity and Thermal Analysis. What are the books,links you would suggest me to learn it? I am ...
10
votes
4answers
8k views

Return path on a PCB

I've spent the weekend absorbing video lectures from Eric Bogatin and reading his book "Signal and Power Integrity - Simplified" He states that the the return path for the PCB may be any DC plane ...
19
votes
2answers
5k views

PCB routing: EMI and signal integrity, return current questions

If there's any EMI/SI lesson I've taken in, it's to minimize return loops as much as possible. You can work lots of EMI/SI guidelines from that one simple statement. However, not having or ever even ...
1
vote
2answers
3k views

Highly asymmetrical rise and fall times

I'm using a MOSFET to buffer my signals from a CPLD. The signals travel external to the PCB using long (from 1m to 10m) wires and then come back to the same PCB - the wires are actually the component ...
17
votes
1answer
2k views

Why are PCIE's coupling capacitors so large

I was looking at the PCIE specification, and I don't understand the requirement for coupling capacitors. For 2.5GT/s, the standard requires AC coupling capacitors of 75nF to 265nF. I tried to ...
10
votes
2answers
3k views

Ethernet RMII on two layer PCB

INTRODUCTION: I'm aiming to design an Ethernet connected system as a hobby ( ie. plenty of time but not wishing to spend much ). My design constraints would ideally be sticking to a 2 layer 100mm x ...
9
votes
3answers
4k views

DDR1 Layout Considerations - DOs and DONTs

I am novice to high speed design. Before getting in to DDR, I recently learned about impedance matching and how it is done, likewise I learned about length matching and how it is done.(Baby steps ...
7
votes
1answer
1k views

DDR bus design review

In our last build we had issues with DDR stability in our prototype, simply because of lack of experience with this type of high speed memory connections. We managed to get it working with halving the ...
7
votes
2answers
2k views

Returning Currents for two side boards and returning current questions

I have some questions these are I am not sure: I have designed a board that has classical 2 side PCB design. Frequency is not a big issue for me but with ESD my CPU resets itself. (CPU clock 20 Mhz, ...
5
votes
5answers
3k views

Why does differential signaling send complementary signals instead of just pairing the input and ground voltage?

I'm very new to EE, so please excuse me if this question is bad or has an obvious answer. After reading an overview of differential signalling, it left me wondering: Why does differential signalling ...
11
votes
1answer
2k views

SPI Bus Termination Issue

I've been working on a project where an OMAP Linux SPI master interacts with 6 SPI slaves peripherals (5x A/D converters and single magnetometer). I can set the SPI clock frequency and have ...
5
votes
2answers
2k views

Do I need a via or stitching cap when I transition between physical reference planes of the same potential?

I have the following layer stack up Signal Ground Signal Power Ground Signal Ground Signal Layer 1-2-3 are tightly coupled Layer 4-5 are tightly coupled Layer 6-7-8 are tightly coupled Total ...
4
votes
1answer
1k views

Benefits of top and bottom ground pour in multilayer boards with proper ground plane layers and stackup

I'm trying to get some analytical feeling for the use of ground pours on bottom and top layer in multilayer boards with proper stackups such as (for example). Top Gnd Sig1 Power Power Sig2 Gnd ...
9
votes
1answer
368 views

DDR3 Data Errors

I am looking for post layout solutions for DDR3 data errors. I have a PCB with a FPGA and a 2 banks (2 rank) DDR3 ram setup. Data errors occur either when the RAM (FPGA is not confirmed, but could ...
8
votes
2answers
2k views

What kind of effects does a relay have on signals?

Currently I'm working on a DDS based function generator. The idea is to use an AD9834 chip that will generate a triangle/sine or square wave. With some amplification electronics I want a configurable ...
8
votes
1answer
213 views

Separating Two High Speed Digital ICs

Previously, I've designed a PCB incorporating this ADC chip. It has a digital bus of 10 signals some of which are 40MHz. Right now we have a four layer PCB and the ADC is connected directly to a ...
6
votes
1answer
1k views

Why is the signal amplitude low on the oscilloscope even though the impedance is matched?

I have a photodetector with differential outputs that are each 50-ohm terminated. When I connect one output to the oscilloscope to look at the signal, I see a higher signal amplitude with higher ...
6
votes
3answers
2k views

Increasing Fall/Rise Times for Signal Integrity

I have a board that tests a wiring harness' continuity by outputting a set of test vectors onto the harness and reading it back. The wires in the harness can be as little as 1 m and as large as 10 m. ...
5
votes
1answer
470 views

LVDS signal distortion w.r.t switching power supply

We are using DC-DC switching regulators on board (switching freq. of regulators are ~540KHz). There is periodic noise in power/gnd at 540Khz. If we change the switching freq. of regulator, the ...
5
votes
2answers
3k views

Will a 75ohm cable work with (not break) a 50ohm gsm shield?

I need to have a long (100') stretch of cable from my antenna to a GSM box (remote control for heating via GPRS or SMS), and I need to minimize signal loss. In another (totally different) question ...
3
votes
1answer
191 views

Analogue (or digital) signal integrity with multiple sources of noise

tldr: Can I transmit an analog signal through a noisy environment without it being corrupted, or should I use a digital signal instead? My requirement is to transmit a signal from a MA3 absolute ...
3
votes
1answer
148 views

Need smaller pullups on i2c lines, but design is low power, what is best?

The pullups on my i2c lines are 4.7k. People are afraid of draining the battery by fixing this waveform with smaller pullups, like 2.2k. It doesn't seem much power is wasted considering the short ...
2
votes
3answers
476 views

SAR ADC has non-linearity around the middle of the range

I'm using a SAR ADC in STM32L433 chip and it exhibits a strange nonlinearity around the middle of the range which I can't explain. It's a 12bit ADC with 64x oversampling and 2 bit shift which ...
2
votes
2answers
109 views

What's the suitable wire size for 9VDC @25 Amps line?

I am trying to put together the requirements for a cable and I was wondering what would be the most suitable wire size to load the DUT with 25Amps @ 9VDC. I will have few other high current lines ...
1
vote
1answer
493 views

Will software-based DSSS work?

We are implementing a 2.4 GHz RF link using a TI CC2541 chip (http://www.ti.com/product/cc2541) and we are new to RF design. We want a robust, low-bandwidth, low-latency link. We were thinking of ...
1
vote
1answer
51 views

Output impedance imbalance and CM noise in truly floating sources

In the following Figure 1 and Figure 2, the sensor is the one in dashed box. The output impedance of the sensor is big and in this case is 1k Ohm. And as you see regardless of the sensors are bipolar ...
1
vote
3answers
265 views

Large number of termination resistors and bi-directional signals

I am designing PCB which has an FT601 for USB communication. No matter how hard I tried, I could not keep the traces short enough in order to avoid reflections and simulation was revealing significant ...
0
votes
2answers
1k views

Trace termination length limits

Are there any length limits to series termination ? If I have a trace that's 12 in or a trace that is 100 in, can the same series termination resistor be used (assuming that Zo = 50 ohm) ?
0
votes
1answer
118 views

Glitchy pulses in a data acquisition system

A single-ended -10V to +10V 16-bit data acquisition system is composed of 16 single-ended channels where two of the channels are analog outputs and the rest are analog input channels. The transducers ...
0
votes
2answers
562 views

Multiboard Grounding In High Frequency

How can ground loop be avoided when connecting two system with same ground. This happen in PC whith SATA cable or PCIe Card with seprated power cable. My System Board: I have two pcb each with a ...
0
votes
2answers
564 views

Improve signal integrity of Ethernet signals (if indeed is needed)

Actually it is nothing to do with Ethernet specific, but just to be accurate, I have several SS-SMII Interface signals between an FPGA and a Switch. The interface has 8 data signals, one ...
0
votes
1answer
56 views

Is there a problem connecting PSU grounds to earth for an isolated signal chain in this scenario?

For a precision and simultaneous analog signal data acquisition; several force, temperature and acceleration transducer outputs are coupled to a daq board input channels through signal conditioning ...
0
votes
1answer
247 views

Difference between conventional Eye-diagram voltage plot and “Eye-density” plot in ADS Keysight Simulation

I know what is eye diagram. It is the sampled voltage plot at the clock frequency (Usually) of my circuit and superimposed. If the logic 0 corresponds ...