Questions tagged [signal-integrity]

Questions regarding how to properly ensure Signal Integrity, protection from noise, shielding, proper pcb layout.

Filter by
Sorted by
Tagged with
0
votes
0answers
39 views

Use of common choke with more than 2 wires

I've been looking around and I couldn't really get a good answer to this question, not even in Henry Ott's book (so far), so here it goes: What is the best approach when there is the need to place a ...
0
votes
1answer
46 views

MUX chips only happy with one of the inputs

I have two MAX4533 quad SPDT chips, all outputs are behaving the same. NOn - a PWM pulse train at 25% generated by an Arduino Mega. NCn - a 5kHz square wave from a AD9833 signal generator. Switching ...
1
vote
1answer
64 views

Why there is capacitor in series in high speed designs like SGMII?

Why we are connecting capacitor in series in high speed designs like SGMII. If it is to remove DC voltages, why we are not using on other signals like I2C, SPI and so on. What is the major purpose. ...
0
votes
1answer
28 views

Reference layer for stripline / microstrip

I have a question. I read everywhere in manuals that for a stripline (or microstrip), the reference layer can be not only the ground plane, but also the power plane. Actually, I had a couple of ...
1
vote
2answers
59 views

Power path around 4 layer PCB

I'm designing a 4 layer PCB (Signal-GND-PWR-Signal) that has power input and motor connectors placed as seen in the picture. In order to avoid thick traces I traced a power path around the PCB ...
0
votes
0answers
11 views

The accumulative error on the crosstalk items (s23, s14) when cascading multiple 4-port s-parameter

I found there seems existing the accumulative errors on the xtalk items when doing large number of s4p cascading. Here is a brief summary: When it is two port network, ie, s2p, things are much better,...
0
votes
0answers
19 views

Problems with voltage supply in Altium IBIS simulation

I have a question regarding my project. I am designing high speed output from my microcontroller. Switching times should be around 450 MHz, so I found IBIS model for my microcontroller and line ...
3
votes
1answer
163 views

Why route signals orthogonally in adjacent layers?

I am investigating PCB stack-up. Everywhere I have seen it says to route signals on adjacent layers orthogonally to reduce the coupling. I have two questions: How does orthogonal routing reduces the ...
0
votes
0answers
23 views

What are the required Eye Specifications for SGMII+?

I am performing Signal Integrity Analysis for SGMII+ TX and RX lines operating at a frequency of 2500Mbps. Please let me know the minimum eye specifications such as eye height and eye width required ...
0
votes
1answer
31 views

Controlled Impedance Trace-reference plane Placement

I am new to high-speed PCB design. I was studying controlled impedance traces from the internet with the help of various documents. Everywhere it says controlled impedance traces need a reference ...
0
votes
1answer
37 views

Differential Pair Mode Conversion [closed]

What is the purpose of using these mode conversions? SCD Input: Differential Output: Common SDC Input: Common Output: Differential
3
votes
1answer
144 views

Noise Pick up in High Impedance nodes

I was making a non inverting amplifier,in the first iteration a provided a gain 1000 and at that time I can see the line voltage frequency 50Hz is coming at the output. I reduced the gain and made it ...
0
votes
2answers
67 views

Pseudo Periodic Signal

I am reading a research paper Eyer 1999 in which they used these terms so I want to know about them since there is no source on which I can learn about these terms so that's why asking it here, it ...
0
votes
1answer
74 views

Parallel Termination in a Transmission Line

Suppose we have a parallel termination like this on a high-speed trace: If the line impedance \$ Z_o \$ and \$R \$ are matched, then there are no reflections from load to cause any ringing at the ...
0
votes
1answer
41 views

Termination resistors for RAM vs drive strength

I'm considering using a RAM IC (S27K HyperRAM from Cypress). The layout guidelines document suggests adding series resistors "if necessary." However, the datasheet for the device has a ...
0
votes
1answer
52 views

Instrumentation Amp design for breaking ground loops between systems

We're in the midst of designing a device for measuring analog signals and have been testing our initial prototype. We had a single-ended gain stage before the ADC, but due to the connections in the ...
5
votes
5answers
2k views

What is the meaning of “longer electrical length = more wavelengths”?

Reading a Keysight-note, not sure what is the following selected line means? I read and understood the meaning of electrical length, how it is related to bit in flight and wavelength is not clear.
-1
votes
1answer
75 views

Difference in signal speed for a high speed signal when it is driven as single ended and differential?

This is a thought experiment. I would like know and what will be the bit-rate in differential channel when signal is driven differentially and in single ended mode? Lets there is differential trace ...
2
votes
1answer
356 views

What types of cables do ferrite beads/chokes have a beneficial effect on?

Ferrite beads prevent electromagnetic interference from affecting a cable. Without fundamentally understanding how EMI works, this is obviously a beneficial effect for the stability and integrity of ...
0
votes
1answer
29 views

Does it matter if the shunt resister in an audio Line Out L-Pad attenuator is 6 feet away from the series resister?

I am designing a 14dB L-Pad attenuator to be buried in a guitar instrument cable as per below. The placement of the 22K ohm series resister is to go inline inside the amplifier side of the 1/4" ...
0
votes
0answers
32 views

Eye diagram analyzing for SI analysis

I am performing SI analysis for the GTX transceiver interface. the FPGA that I am using is Xilinx Kintex-7 FPGA. I have received a reference SI analysis report done by customer which has eye width, ...
0
votes
1answer
37 views

How to select the correct CM choke?

Say I want to reduce noise on the data line for WS2812B led strips. Is it a viable option to use CM chokes to reduce this noise? According to the docs, WS2812B data speed is 800Kbs. Which I guess ...
1
vote
2answers
89 views

Why does FPGA PCI Express Tx output have on-chip termination of 100 Ohm?

The Intel Cyclone IV FPGA supports PCI Express (PCIe) generation 1, and the IO standard for the Tx output is PCML at 1.5 V. The Cyclone IV Device Handbook volume 2 page 1-13 describes that the Tx ...
0
votes
0answers
41 views

Overshoot and undershoot on clock signal missing in high frequency(HyperLynx)

I'm using it for my work in Hyperlynx SI to test high-speed signals. This is a general question but I read somewhere that the simulation in high freq could make a problem to identify some peaks in ...
0
votes
1answer
38 views

Advice on Noise in Square Input Signal

I am reading the following signal from an open drain output, and trying to read the signal frequency. However, I am getting short spikes in the wave as seen below, and this is messing with the reading ...
0
votes
1answer
46 views

Conditioning for automotive electronics [closed]

I have a simple application: convert an automotive throttle 0-5V line to 0-2.5V on a circuit near (and feeding into) a fan controller. Very loose maximum frequency is 10Hz. I reduced R1 because the ...
0
votes
3answers
59 views

Board to Board Cable Set-up

I've run into a connection between two PCBs, and it's not giving me a warm fuzzy feeling. The master is a carrier board, and the second board is a standalone sensor that communicates over SPI. This ...
1
vote
2answers
102 views

Reflection in low frequency conductors (not transmission line)

Is the reflection phenomenon common in RF work with unmatched source/load pairs also present at low frequencies? Or are the wavelengths so much longer than the physical conductor lengths that ...
1
vote
0answers
38 views

Location of Amplifier for Signal Integrity

Let's say I have a photodiode that outputs a current with respect to incident light on the die. If this photodiode will be located 12 inches or so away from the control board, would it be better for ...
1
vote
0answers
29 views

Does using a push only plug for and F connector in a coaxial cable decreases the signal or adds noise?

I'm intending to find a replacement cable for my cablemodem unit. The existing cable that the phone company installed is a screw in terminal on both ends of the coaxial cable with one end connected to ...
4
votes
2answers
575 views

Effects of test patterns

If I have an 8-bit high-speed interface say at 1GHz talking to memory and I want to do interface testing, I can send patterns like AA/55/00/FF. When I send a pattern like 55 i.e 01010101, every even ...
1
vote
1answer
39 views

Signal Integrity with Parallel Switch Control

Please excuse what is likely to be a very basic question, but I am an ME, and this stuff is somewhat magic to me. First, I'll provide a minimal, generic question, and then, for those interested, I'll ...
1
vote
1answer
65 views

How to get (with a fixed range and offset) linearly proportional signal from a variable range on the input?

Ask: How to get (with a fixed range and offset) linearly proportional signal from a variable range on the input? Conditions: There's a signal (to simplify, consider a sinusoid) with variable amplitude ...
0
votes
0answers
32 views

How to select the setup time and Hold time for the DDR3/4 SI analysis?

I am performing SI EYE analysis for the DDR3 interface. Following are my consideration for the DDR3 SI analysis:- Data rate= 800MHz/ 1600 MT/s Data UI = 0.625ns = 1/800MHz Address, command and control ...
0
votes
0answers
101 views

Floating LVDS Input

I am designing a FPGA based receiver for a specific IC, which communicates its data utilizing standard LVDS interface with 100 Ohm termination resistors. The IC has 10 channels (pairs) plus the clock. ...
3
votes
3answers
289 views

Will this shottky diode circuit protect my ADC, and if so, are there options with more than 2x channels?

I am trying to read 8x 12VDC digital inputs and 4x 5VDC analog inputs with my 3v3 Teensy 4.0 Microcontroller. In V1 of my design, I used a voltage divider circuit to drop down to 3v3. I would like to ...
0
votes
1answer
88 views

Use of twisted pairs with fundamentally single-ended DUT

Let's suppose I'm interested in measuring the voltage response of a DUT to some imposed voltages. The DUT takes V1, V2, V3 as inputs relative to some GND, and outputs V4 relative to the same GND. All ...
0
votes
3answers
157 views

A typical GPIO works at 150MHz without risk for EMI but why is there a risk of EMI at even 400KHz in I2C?

In I2C the fall time is restricted to around 20ns as a risk of EMI(Even at 400Khz) but even a normal GPIO works at 150 MHz.Why is this so?
4
votes
1answer
78 views

how to understand unparalleled transmission line?

in a normal transmission line example, shown as case-1 in below picture, the signal path and return path are parallel to each other, let's say it takes 1ns for the signal propagate from left side to ...
0
votes
1answer
81 views

Controlling a Brushed Motor with DC Voltage to Avoid EMI (no speed control needed)

I have a fairly simple project coming up. My task is to design a system which powers and controls a Pan and Tilt positioner for a camera. It has some weird and unavoidable requirements/constraints: ...
0
votes
1answer
37 views

About best way to perfom checksum

From my knowledge,checksum can be done using Xor or adding the bytes of the frame...i have to create a communication between ATmega32 microcontroller and matlab to perform some functions...which is ...
17
votes
1answer
2k views

Why are PCIE's coupling capacitors so large

I was looking at the PCIE specification, and I don't understand the requirement for coupling capacitors. For 2.5GT/s, the standard requires AC coupling capacitors of 75nF to 265nF. I tried to ...
3
votes
1answer
107 views

Decoupling capacitors on bottom layer in non-BGA packages?

Typical advice on decoupling techniques usually gives highest priority to: always place the decoupling capacitors on the top layer, next to the pins. BGAs of course are a separate issue; I'll come ...
1
vote
3answers
67 views

Do parallel LNAs at 90-degrees to eachother reduce the noise floor more than side-by-side?

Wiring amplifiers in parallel in a summing configuration improves the signal to noise ratio because amplifier noise in each LNA is uncorrulated. However, external noise sources will still be a factor ...
0
votes
1answer
43 views

How to avoid RF signal loss in a conductive cage acting like a Faraday shield?

I have a standard chip antenna mounted on a large ground PCB plane. The product is unfortunately encapsulated inside a relatively open (carbon-fiber) conductive cage. Unfortunately, I see an obvious ...
4
votes
0answers
208 views

Why DDR4 Specs recommend that Address, Control and Clock buses be referenced to VDD?

Micron's Technical Note TN-40-40: DDR4 Point-to-Point Design Guide, page 19, says (emphasis mine): Timing Budget Suggested practice is to look at the design from a timing budget standpoint to provide ...
2
votes
1answer
35 views

Should I avoid a switching frequency close to my target SPI or CAN frequency?

I have a kind of an open-ended question. If I'm designing a board with a buck converter and have picked out my peripherals, and say for example I want to run my CAN FD interface at 1MHz baud and maybe ...
1
vote
0answers
107 views

Is this differential pair routing OK?

I am working on a PCB layout on a very space constrained, 4-layer board. On the board is a MIPI-output image sensor (1 lane) which go to an FPGA. Layer 1: Image sensor Layer 2: Full Gnd plane Layer 3:...
0
votes
1answer
58 views

Should via use be used when it is not essential?

I am working on characterising a transistor at approximately Vds=1000V and Ids=100A pulsed at around tON=20ns. Should the power and ground paths (Top and Bottom layers) have vias connected to the ...
1
vote
2answers
43 views

Signal line current estimation and impedance matching

As far as I know, the input pins to ICs are typically just the gate of a MOSFET. I have always just take stuff for granted (like if you want to control a logic pin, just put a source voltage on it), ...

1
2 3 4 5
7