Questions tagged [signal-integrity]

Questions regarding how to properly ensure Signal Integrity, protection from noise, shielding, proper pcb layout.

Filter by
Sorted by
Tagged with
0
votes
0answers
58 views

Measured my PCB with Handheld LCR Meter - can you tell me anything?

This is a 5x4cm 8-layer PCB. It has 2 sets of dedicated VCC/GND planes plus ground plane polygons on top and bottom. It is not high speed. The top digital speed is 1Mhz SPI. It has 3 micros running on ...
0
votes
3answers
625 views

Connecting signal to multiple summing amplifiers

For a normal op-amp inverting summing amplifier, each signal is tied to the negative input of the op-amp. Imagine the scenario where I have three signals. In adder 1, I want to sum A and B. In adder 2,...
0
votes
1answer
246 views

Cyclone V data corruption at high frequency

I'm currently trying to implement a FPGA design using a 325 MHz clock, which writes to the SDRAM Controller of a Cyclone V 5CSEBA6U23I7 (Speed Grade 7). When running my IP Core with 2 MHz everything ...
0
votes
2answers
528 views

PL9823 data line corruption when using 3v3

This is my schematic: The PL9823 uses the same protocol as WS1012 (NeoPixel) When using 5V MCU and 5V to power the LED everything works OK. When using 3v3 MCU and 3v3 to power the LED everything ...
3
votes
1answer
75 views

Reflections of Low bit rate signal and High bit rate signal

I was reading wikipedia page on Signal Integrity and got stuck with this paragraph. It says: The channel flight time (delay) of the interconnect is roughly 1 ns per 15 cm (6 in) of FR-4 stripline (...
5
votes
2answers
3k views

Will a 75ohm cable work with (not break) a 50ohm gsm shield?

I need to have a long (100') stretch of cable from my antenna to a GSM box (remote control for heating via GPRS or SMS), and I need to minimize signal loss. In another (totally different) question ...
8
votes
1answer
498 views

USB 3.1 over PCIe board edge connector

I am designing a system with a carrier board that has all of active logic on one board and most connectors on a backplane board. The interface between the two boards is a x16 PCIe board edge connector....
11
votes
7answers
2k views

Good uses for 1:1 probe

We all know why using a properly compensated 10:1 probe is a must when viewing MHz-speed signals on a scope with a 1 MOhm input impedance. Now who can supply a good use for a 1:1 probe? These probes ...
6
votes
1answer
1k views

Why is the signal amplitude low on the oscilloscope even though the impedance is matched?

I have a photodetector with differential outputs that are each 50-ohm terminated. When I connect one output to the oscilloscope to look at the signal, I see a higher signal amplitude with higher ...
0
votes
1answer
135 views

ADC signal long trace voltage drop compensation using amp and return trace

I'm running a signal for an ADC a pretty good distance and through a connector. The voltage drops are not unsubstantial. The concept is to run an identical return trace and compare the post-loss ...
0
votes
1answer
84 views

SoC Digital Output Rise Time

I'm interested in calculating series termination resistors for my communication lines for a system I'm designing based on the Zynq-7000 SoC. The system runs on a 33 MHz clock but I'm sure the ...
1
vote
1answer
1k views

RS485 waveform distortion

I was checking RS485 signals with an oscilloscope and saw some waveforms which look distorted (see right side of image PIC1). See schematic for test points TP1, TP2. Setup Probe 1:- TP2 and GND ...
2
votes
3answers
479 views

SAR ADC has non-linearity around the middle of the range

I'm using a SAR ADC in STM32L433 chip and it exhibits a strange nonlinearity around the middle of the range which I can't explain. It's a 12bit ADC with 64x oversampling and 2 bit shift which ...
0
votes
1answer
172 views

differential pair radiation

For experienced designers probably it is easy question but I am reading "Signal and Power integrity, E. Bogatin" and don't understand one thing. "The two most common sources of EMI are the ...
0
votes
1answer
384 views

How to select the model selector for TI IBIS model of DRA725?

Following is the IBIS model selector section for the DRA725 SoC in IBIS file. Currently, I do SI analysis of DRA725 with Mentor HyperLynx SI, Intention is to select the right model selector. What to ...
0
votes
1answer
254 views

JTAG Programmer using Zedboard - Signal Integrity problems?

I am trying to build my own JTAG programmer using the Zedboard but I am stuck with hardware issues. For the Zedboard side, I am using the Pins XADC-GIO0, XADC-GIO1, XADC-GIO2 and XADC-GIO3 as TCK, ...
1
vote
1answer
152 views

Confused with understanding a recommended signal conditioning interface

I will make an interface for a 10k wind-vane recommended in this document. I will follow the recommendations but I don't understand the explanations of the document and I have at the end four short ...
0
votes
0answers
146 views

HCMOS Oscillator pull up / down resistors

I am new in this forum, I will listen and thank all your support. My goal is to know how to design the oscillator output resistors to enhance / optimize clock signal performance. I have been working ...
0
votes
0answers
265 views

DDR threshold levels and timing constraints

I am new in field of DDR and high speed memories, i come across SSTL signaling level diagram, over there VIH & VIL are defined as both DC and AC. What is the difference between them, what is the ...
0
votes
0answers
109 views

Discrete DDR3 Layout Check

I have 8 chips of 512 Mb DDR3 interfaced with the processor with point to point Data & fly by Address/command topology. I need to remove 1 DDR3 & keep it unmount. The rest 7 DDRs should work ...
1
vote
2answers
8k views

Why is length matching important for high-speed signals?

Broadly speaking, I understand that PCB trace length matching is important from signal timing and signal integrity point of view, but I want to know some more specifics about these two parameters and ...
3
votes
1answer
921 views

Shielded breadboard jumper cable wires

Does it exist a shielded version of 2.54mm pitch breadboard jumper cable wires? Thin flexible wires, Gauge AWG 24-28. I want use shielded wires for JTAG cable, to reduce electrical noise from ...
1
vote
2answers
236 views

Slew rate limiting of bidirectional lines

Assuming the ICs in use don't offer an adjustable slew rate, if I want to limit the slew rate of a unidirectional digital data line, for example of SPI's MOSI-signal, I can put a series resistor at ...
2
votes
1answer
70 views

How can I control the route to analyse with HyperLynx in a switch?

Good day to everyone. I recently started using HyperLynx from Mentor and I'm having difficulties in analyzing the signal-integrity of the signals due to having switches in the circuit. When I load ...
11
votes
1answer
3k views

CAN bus signal integrity

The channels are CAN_H (red), CAN_L (blue), and CAN_H-CAN_L (brown). It can be observed in the diagram below that CAN_H-CAN_L has an acceptable signal shape. However, both CAN_H and CAN_L look poorly ...
0
votes
1answer
65 views

Compute loss/inch for (differential) T-line from s-parameters?

I have the 4-port s-parameters of 2 PCB boards, where each board consists of a differential transmission-line with SMA connectors on either end. The only difference between the boards is their trace ...
0
votes
4answers
4k views

Does a BNC splitter introduce defects into the signal?

I'm currently doing some contract work that includes finding and recommending a signal generator model for frequency measurement device verification. The verification scheme requires generating a ...
3
votes
1answer
1k views

SPI signal integrity issue

I have a custom four-layer PCB (Signal, Ground, Power, Signal) with an STM32F4 (72 MHz) connected to a Si4684 receiver and a Si4711 FM transmitter through SPI. It seems that my design has some ...
0
votes
2answers
103 views

USB 2.0 High Speed Device with Input Power Filter

I am working on a USB 2.0 High Speed Data device that will have a power input filter for EMI and overall power integrity. The filter includes inductors on both the +V and GND. So this means there will ...
0
votes
1answer
170 views

is it possible to design high-speed PCBs in a modular way?

I'm going to design an Arm Cortex-A53 based core-board and this core-board will be used in many different projects with different applications. Sometime it will be used in a generic device to just run ...
0
votes
1answer
965 views

Ground pour under ESP8266 12-E

I want to pour ground under a ESP8266 12-E just for thermal reasons but I don't know if this can affect it somehow or if it's safe to do. The PCB is all under 5V, it's only 2 layers and it would have ...
1
vote
1answer
1k views

Shunt Current measurement noise

I was measuring current through shunt method. below is the SCH and waveform captured. PB5-AI will to ADC which has max 1 Volt limit. Waveform capture across R30 So why this much noise on output ...
28
votes
3answers
16k views

Why does VGA have so many ground pins (compared to DVI-I for example)?

If you look at the pinout for VGA, there are several ground pins: I was curious as to why, and I found this answer. To sum it up, the extra ground pins are so that each pin has its own ground in ...
0
votes
1answer
336 views

ODT Termination and driver impedance Question

I am analyzing signal integrity between an applications processor and DDR3 modules.I was looking at IBIS models for the device I am using. I was confused because certain IBIS models had "driver ...
1
vote
1answer
216 views

unwanted stimulus time offset in hyperlynx si

I am using hyperlynx-si to simulate the eye-diagram of a serial link in my design. I've took a 0.66 Gbps random pattern as the stimulus, but as can be seen in the picture, there is an unwanted 300ps ...
4
votes
2answers
488 views

Steps needed for low EMI PCB design

As a student, when I needed to make a PCB, I just placed the components & auto-routed on ARES, and they usually worked well. However, now a fresh graduate & novice engineer, I found that this ...
4
votes
1answer
1k views

Dealing with splits in my ground plane

Whenever I'm making a cheap, 2-sided PCB, I run into this problem: Where I have signal lines (on the top layer here) running over top of a big fat power trace (on the bottom layer). Now, this is ...
1
vote
2answers
263 views

Wiring 800kHz signal together with RS485 on Cat5

I'm planning to have short (~1m) RS485 runs @<500k baud to transmit some data between PCBs. These PCBs also have a few addressable LEDs (WS2812B) that send data at 800kHz. Would it be problematic ...
5
votes
1answer
2k views

Routing impedance controlled signal with a power plane as reference

Assuming i chose to route an impedance controlled signal with a power plane as a reference plane instead of ground (microstrip or stripline), and assuming i'll make sure the signal won't cross power ...
0
votes
0answers
80 views

Individually modulate two lasers diodes using sound - while using the same power suppy and preventing signal “bleed over”

I'm trying to individually modulate two lasers diodes using the same power supply. The modulation for each laser module is created by the left and right audio channels. Is there a way to do this ...
1
vote
1answer
3k views

What is difference between IBIS model and IBIS-AMI model and what are specific application of these two models?

I am working on PCIe 3.0 compliance testing from signal integrity and power integrity point of view. I would like to understand the difference between IBIS and IBIS-AMI model and which model is good ...
4
votes
2answers
217 views

Implications of routing same signal on top and bottom of PCB?

What are the implications of routing the same signal on the top and bottom of a PCB? I have a situation where it would save me a via to do this just for about 3mm. I'm routing an I2C signal to a ...
5
votes
1answer
471 views

LVDS signal distortion w.r.t switching power supply

We are using DC-DC switching regulators on board (switching freq. of regulators are ~540KHz). There is periodic noise in power/gnd at 540Khz. If we change the switching freq. of regulator, the ...
1
vote
1answer
5k views

Where should I place the series termination resistor for AVSBus?

I'm dealing with a AVSBus interface (like SPI, there are CLK/MOSI/MISO signals). The CLK may run up to 25MHz, so we'd like to add series resistors on the board, as a back up if we need to tune the SI ...
3
votes
1answer
417 views

How can I use the TDR result to evaluate the effect of impedance discontinuity?

Only the left half is relevant. Like mentioned before,I want to check out if reflection is one of the reason that deteriorates the signal integrity of high-speed signal.One way that has been come up ...
0
votes
1answer
83 views

Prerequisites for Power Integrity Analysis

I try to learn about the topic of Power Integrity Analysis of an PCB, i.e. analysing the Power Distribution network (PDN) of a PCB to locate the regions of biggest noise or DC voltage droop. ...
0
votes
3answers
272 views

What could probably go wrong in PCB if output PAM4 signal my look like this?

I've been recently testing a self-designed PAM4 transmitter(TX).The transmitter is intended to work at a data rate of 40Gbps,and it really does work in the simulation tool(Cadence)under various PVT,so ...
1
vote
0answers
136 views

Possible ground loop problem?

I'm facing a strange issue and I can only think of a ground loop but the problem seems excessive. I have a three pcbs, one for some supplies, one main and one optional that can be plugged on the main ...
1
vote
1answer
99 views

Laplace domain: poles on both sides of the jw and x plane

For a pole/zero plot, if a system has a pole on the left side only it is stable, and if the pole is on the right only it is not stable, but if the pole is on the right and left, would that be stable? ...
4
votes
2answers
899 views

Is FFC suitable for remote Ethernet jack?

I'm working on a product design which includes an Ethernet jack (with integrated magnetics) that will need to be remote from the controller. The controller and jack are contained in different parts of ...

1 2 3
4
5
7