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About tools to simulate circuits. Specify the tool used.

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Implementing triangular ramp in simulation

I am using the UCC256301 in a project (I know it says it is not recommended for new designs). I am trying to simulate my system using PLECS and it needs the controller IC's behaviour implemented. From ...
SM32's user avatar
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1 answer
89 views

How can I simulate driving a high capacitance MOSFET with a gate driver IC?

I'm trying to drive a MOSFET with approximately 2nF of capacitance, using a 1EDN7511B gate driver. Following the data sheet sample circuit, I created this: and tried to simulate it on LTSpice using ...
SRobertJames's user avatar
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1 answer
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How to model MOSFET in a continuous manner in circuit simulator with Early effect?

I'm implementing a power electronics circuit simulator. Currently I have all linear components including capacitors/inductors/transformers, switches, and as the only nonlinear component Shockley diode....
juhist's user avatar
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gtkwave not showing all signals in DUT [closed]

I am trying to switch from Vivado to GHDL for a project. Spoiler alert in case this is a rookie question : I am new to GHDL. This being said, this is my testbench : ...
lazerbeam's user avatar
2 votes
1 answer
80 views

Simulation problem in half bridge leg of an inverter

I am simulating Half Bridge Leg on an inverter. From the simulation, I could not understand why I was not getting proper dead time between high and low side fets. However, I set a delay time of 150ns ...
krunal patel's user avatar
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Why output voltage became an irregular sawtooth shape?

Why does the transient output voltage in PSpice simulation turn into an irregular sawtooth shape? Before today, it was a beautiful curve that could calculate the voltage gain, but suddenly it became ...
CalvinH's user avatar
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2 answers
77 views

LT spice, JK Flip Flop: Wrong behaviour when J K and Clock are high

Here's a picture of a JK Flip Flop I try to simulate with NAND gates: This is the behavior I would expect; if Clk, J and K are all high, Q_n+1 should be negated Q_n: However this is what I'm ...
haifisch123's user avatar
1 vote
0 answers
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Multiphysics EM Simulator software [closed]

I would like to simulate and evaluate the electric field generated as materials and geometries of generic electrodes change. I have never used simulation software, but I have heard of CST and HFSS. ...
KaleM's user avatar
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3 votes
2 answers
151 views

Why is my Thevenin voltage result wrong in LTspice?

I want to simulate the Thevenin voltage of the circuit below, where Z2 is the load, in LTspice. Does anyone know what is wrong here? The result is incorrect; the correct Thevenin voltage should be ...
internet's user avatar
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Interdependency Issue in Power Enable Circuits for Sensor and Modem Controlled by STM32L476RG

I have designed a power enable circuit to control the power supply to both a sensor and a modem, each with its own dedicated power enable circuit. The MCU used is the STM32L476RG, and the power enable ...
Hafiz's user avatar
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How to simulate ADS131 ADC ic, its simulator model is not available anywhere. Is there any software(proteus/altium/kicad) on which i can simulate it?

I want to simulate this ADS131 IC as a part of bigger circuit but I'm not able to find this IC's simulator model in the proteus than how to do simulation?
Meet's user avatar
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4 answers
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How to analyze a current sink for an ideal power amplifier

In preparing a design for a MOSFET RF Power Amplifier, I analyzed this idealized circuit: My analysis is in some ways consistent with simulation but in some ways gets very different results. Is my ...
SRobertJames's user avatar
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1 answer
31 views

Understanding the behavior of an emitter follower power supply

The Art of Electronics has the following exercise: Use a [single BJT transistor emitter] follower with the base driven from a voltage divider to provide a stiff source of +5V from an available ...
SRobertJames's user avatar
5 votes
2 answers
159 views

Band Pass Filter Design Simulation

I'm trying to simulate a bandpass filter in ltspice. bandpass filter should be in the 2-5 Hz frequency range I calculated the capacitor and resistor value for this range. However, the simulation ...
AEY's user avatar
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1 answer
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LTspice and ngspice simulation results differ by 5-6GHz

I simulated a basic CMOS inverter based 3 stage ring oscillator in both LTspice and ngspice, using the same model files (using NCSU's freepdk45 models (VTG slow slow corner)). I expected there to be ...
Koustubh Jain's user avatar
1 vote
1 answer
101 views

Designing circuit parameters with NPN-PNP transistors -LTspice simulation

Below is a part of the circuit I created to drive the MOSFET (it includes level shift, power stage etc.). Datasheet of 2SC2411K: https://fscdn.rohm.com/en/products/databook/datasheet/discrete/...
Mhan's user avatar
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The simulation in DipTrace 5

I have created a schematic, see attached screenshot. Now I am trying to simulate how it works in digital Spice simulator (built in DipTrace 5.0 beta). digital Spice simulator (built in DipTrace 5.0 ...
Kirchhoff's user avatar
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How to resolve errors in simulating a sigma-delta ADC design in LTspice?

I've been trying to learn how a sigma-delta ADC works. I've been through the block diagram mostly and tried simulating one myself by following this video lecture from "The Signal Path" ...
chethanRaj's user avatar
2 votes
2 answers
124 views

Circuit simulation is not functioning properly

I am a college level electrical physics student (and so I do not have a lot of knowledge on the topic of electronics) and I am in the midst of writing a report on a project that was done throughout ...
Boldumus's user avatar
2 votes
1 answer
38 views

Troubleshooting Voltage Sensing Issues in Buck-Boost Chip Simulations

I performed a simulation on a buck-boost chip (LT8390). I understand that the sensing resistor placed between LSP and LSN is supposed to sense the differential voltage. This voltage is then amplified ...
chami's user avatar
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Wireopt variable in cadence virtuoso ADE simulator window

I am wondering about a variable in my simulator & output window in cadence virtuoso. It is wireopt. It is there by default when I start any simulation in ADE/ADE XL window. And the value is this. ...
aguntuk's user avatar
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1 vote
2 answers
44 views

How to be sure that the SPICE simulation results are the exact results I will get when I build the circuit (especially an ASIC) in real?

I have been doing circuit simulation in HSPICE for research. The final stage of the research is to build an ASIC. The simulation results are often satisfactory. However, I am still in doubt if the ...
Wanderer's user avatar
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1 vote
3 answers
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Increase operation width during the operation without extra registers in Verilog

I have two signals of type "reg" with different bit lengths: reg [15:0] A; reg [11:0] B; I want to display the value of ...
Saeed Jazaeri's user avatar
1 vote
3 answers
66 views

Output Variable stays unintialised in my VHDL testbench

I am pretty new to VHDL and was trying to write a VHDL simulation for a simple master-slave toggle flip flop. Following is the VHDL code that I have written: ...
Rohan's user avatar
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0 votes
2 answers
52 views

Falstad Circuit Simulator: Issues Simulating a Peak Detector [closed]

I was attempting to simulate a peak detector circuit and noticed that when the input to the peak detector is a square wave, the simulator goes a little nuts and the voltage across the capacitor ends ...
user24331180's user avatar
1 vote
3 answers
78 views

Full wave bridge rectifier with Pi or T filter simulation won't converge

I'm designing a full wave bridge rectifier and want to compare a pi filter and T filter after the rectification. I intend to add a transformer at the input and a buck-boost converter on the output. ...
BTB18's user avatar
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1 vote
1 answer
38 views

ALTIUM SPICE Simulation: MOSFET switching power

I am trying to simulate a switching MOSFET circuit in Altium, and I'd like to get a energy measured during the conmutation. So far, I could simulate it properly, but I can't find the integral ...
Alber's user avatar
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3 votes
3 answers
257 views

LTSpice iteration limit reached for operating point simulation of many resistors and power load

I'm trying to simulate this long 14AWG cable with DC power to multiple loads. These loads expect about 12W of power and can therefore not really be modeled with a resistor easily. As the voltage ...
adamski93's user avatar
1 vote
1 answer
50 views

Verilog set bit counter

I'm trying to create a Verilog program that would display the digit with greater number of bits set. The code is working. However, it counts the bits from the previous values instead of its current ...
Paula Bianca Pascual's user avatar
1 vote
1 answer
79 views

Opamp and regulator not behaving the same on breadboard vs SPICE simulations

I am designing a circuit which is intended to map a signal in the 0-5V range to the 1.75-7.0V range. To do this I am using an LM317T voltage regulator in conjunction with a TLC2272 Rail-to-Rail opamp. ...
Jayson Okhman's user avatar
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0 answers
20 views

i have two patch antenna (coaxial ) and i want to put csrr

i have two patch antenna (coaxial ) and i want to put csrr and i dont get any result on Hfss i substract the Csrr from the ground and from the substract and still same result with and without
Fahd Le's user avatar
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0 answers
50 views

Why can't I get a value from this simulation?

Why doesn't the simulation show any value?
THINKER's user avatar
1 vote
2 answers
89 views

Confusion with a photodiode circuit

I'm using this photodiode with a simple circuit as follows: And in my setup the photodiode sees the same light input meaning same average power from a laser source which is less than a few mW ...
user1245's user avatar
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2 votes
2 answers
63 views

Passing Matrices (larger arrays) between modules

I'm trying to have my design be more compartmentalized and separate each task into different modules/source files. I basically want to pass a matrix and a vector into a module I created where I'll do ...
Samuel's user avatar
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1 vote
2 answers
40 views

Modeling Flip-Flops (RS, T, JK) in Verilog

I encountered an unusual behavior while simulating flip-flops in Verilog using Vivado. Take, for instance, a four-bit up counter where I used an RS flip-flop for the most significant bit (...
user97662's user avatar
  • 273
0 votes
0 answers
38 views

Transimpedance Amplifier Gain ac and S-parameter Analysis

I'm currently working on finding the transimpedance gain of a transimpedance amplifier. However, I've encountered an issue where I get different gains when performing AC analysis compared to S-...
Masood Salik's user avatar
2 votes
2 answers
71 views

Please help me with my verilog code for processor (extension)

This is an extension to my previous question. I am an undergraduate student and am new to Verilog. I am writing Verilog code which simulates a processor along with registerFiles and memory (...
Damstridium's user avatar
1 vote
1 answer
83 views

Can someone help me with this Verilog code for a processor?

I am an undergraduate student and am new to Verilog. I am writing Verilog code which simulates a processor along with registerFiles and memory (instruction + data memory). Here is the instruction ...
Damstridium's user avatar
1 vote
1 answer
53 views

Reusing an output in Falstad

I'm simulating a logic circuit in Falstad and a particular output X is used multiple times in the circuit. Can I take input as X without drawing many wires from X?
Shub's user avatar
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1 vote
1 answer
64 views

Error while building a MIPS ALU Controller Design

...
Zelda's user avatar
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5 votes
2 answers
730 views

What is this circuit? (FM detector?) - LTspice

I have this circuit from college (almost 15 years ago) that is through-hole components wired together and it picked up the strongest local radio station. I now can't get it to work, so I'm wondering ...
tlab's user avatar
  • 51
2 votes
1 answer
101 views

OPA656 Simulation works on TINA but not on LTspice

As mentioned in the title I use LTspice as my main workflow to simulate circuits. One of my circuits is using an OPA656 amplifier. I attach a picture of a simple schematic I made to test the issue. It ...
Victor's user avatar
  • 21
0 votes
1 answer
100 views

Investigating the effect of PCB layout parasitic in an op-amp amplifier by simulation

Would you please let me know what components I should add to my schematic as result of PCB parasitic to make my simulation more accurate? As an example, the following image shows an amplifier ...
Andromeda's user avatar
  • 399
1 vote
1 answer
87 views

Single-Digit BCD Adder

I have this code written in SystemVerilog. The module bcdadd1 is supposed to take in two 4-bit inputs A and B and a logic input carryin (...
David's user avatar
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2 votes
1 answer
53 views

Can't get the required simulation waveform of a quasi-z source inverter using Si MOSFET

This is the circuit I'm trying to replicate, with the waveform: I found it here. This is my attempt at it, but the waveform does not match: Update: This is the waveform I got. How do I get it ...
ADNAN KHASGEER's user avatar
1 vote
1 answer
58 views

SystemVerilog help, I'm stuck

Please help with this SystemVerilog code. The intended behavior is that the seven-segment displays 7 and 5 will show the current inputs, and the segment displays 0 and 1 will be the two-digit result ...
David's user avatar
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0 votes
0 answers
48 views

How to solve the LTspice error "Questionable use of curly braces in xxx."?

When I set up the following circuit, I ran into a question about the use of braces({}) The following are error messages: Why can't the first V be recognized by LTspice, or is something else wrong?
wxss's user avatar
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1 vote
1 answer
51 views

Getting HiZ for my output for a 5 to 1 mux

I'm having trouble with Verilog code for a 5 to 1 MUX. ...
Michael's user avatar
  • 13
1 vote
1 answer
60 views

A NAND gate with propagation delay in VHDL

I want to design a NAND gate (\$t_{PLH}\$ = \$t_{PHL}\$ = 10ns) with VHDL. \$t_{PLH}\$ = Propagation delay low to high \$t_{PHL}\$ = Propagation delay high to low This is first code. ...
Serkan Kaya's user avatar
1 vote
0 answers
55 views

How do I understand the reason behind the incorrect result in below LTspice simulation?

Shown below is the LTspice simulation for a full bridge rectifier. The simulation shows 'wrong' result for open load condition (Rload =1 GΩ). Ideally it should be same as other 2 cases. Why is the ...
Dynamic_equilibrium's user avatar

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