Questions tagged [simulation]
About tools to simulate circuits. Specify the tool used.
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Floating relay terminal in AC circuit causing simulation error
I'm trying to switch between two branches for my circuit. But as the relay switches, the other terminal is left floating. In an AC circuit, I cannot use a pull-down resistor.
I also have a feeling ...
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UART Transmitter implementation using Verilog
I am trying to implement the UART transmitter FSM using Verilog, but the FSM is stuck at IDLE state. Can someone tell what mistakes am I making? The code is as ...
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Simulation of Transistor - Ltspice
I produced spwm to drive high side mosfet.
I made a simple note gate from a pnp transistor to receive the inverse of the signal I produced.
PWM-A/ is the opposite of PWM-A and both are 5V. So far ...
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PWM is giving the Glitch [closed]
I have designed a PWM in Verilog. I am testing the PWM by setting a constant period that is equal to 40000 and changing the duty cycle from 157 to 39843 (with a gap of 157 between two numbers).
When I ...
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Toggling a relay using a 555 timer
I seem to be experiencing errors when trying to toggle the relay using a 555 timer. I have used two different simulation software packages already.
They both seem to crash. There appears to be some ...
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LTspice - simulation of SPWM is giving unexpected result
I am trying to make SPWM with op-amps. I also made a simple NOT gate with a simple transistor.
The first op-amp is working well when its output is not connected. When I directly connect the first op-...
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Can an event name be manipulated in Verilog/SystemVerilog?
In a Verilog testbench.v, there are commands that are used in a task.
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Post Synthesis Simulation in QuestaSim
I am attempting to perform post-synthesis simulation of a Verilog system designed in Vivado on QuestaSim. I am using QuestaSim 2021.2_1 and Vivado 2020.2. Here are the steps I have followed:
I ...
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How to connect multiple TLM ports to UVM Sequencer?
There is requirement to send transactions (tr) from a uvm_component to a BFM, a uvm_driver. But, there are multiple "imp&...
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LTspice repeating arb voltage (BV) block
I am trying to generate a rectified sinewave with a "flat" DC top. I managed to generate 1 cycle (shown).
I used an arb voltage (BV) block, now I just need to get this to repeat, for x ...
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Multism simulation for NMOS type circuit, why I am not getting the expected graph?
I am trying to simulate my circuit for one of the question problems. The question looks like this
I have written a MATLAB script to see the expected graph
...
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Interaction between multiple blocking assignment and non-blocking assignment running in separate procedural blocks in Verilog
Please refer to the following Verilog module:
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Validity of RLGC model for QTEM transmission lines with numerically calculated characteristic impedance and propagation constant
My problem
In my understanding, any system that supports a QTEM mode can be represented by an RLGC transmission line model with negligible error. Indeed, when I perform a calculation in CST microwave ...
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Non-inverting amplifier weird Vout values
I am doing a simulation in multisim to simulate an non inverting amplifier, but i have gotten values that is not what intended. From what i know, the gain for non inverting amplifier is Va = 1 + Rf/...
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Component in proteus
I want to make a rotary encoder in proteus since I don't have it in my proteus library but I can't find the schematic for it i dont know the components and layout needed to make it
https://uk.farnell....
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Verilog sum problem
I have an array named mixed_signal, and I need to sum of its elements in a register but it cannot be sequential. Can you help me?
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Isolated digital input for large variable input voltage (12-240)
In industrial applications, relays are used to send the signal to other parts and machinery. They switch 24 DC and 220 AC on, off signal.
Although there are plenty of circuits to read input signals, I ...
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Interface definition in package in SystemVerilog
I have a very simple interface definition in a package in SystemVerilog:
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Simulation Error (MULTISIM)
I am trying to make a basic invertor circuit using MESFETS the following figure shows the actual circuit but when i connect in multisim software it shows simulation error can anyone help me how to fix ...
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Circuit Simulator
I just recently started to study circuits. I have a homework assignment and I need to simulate some circuits, but I don't know what simulator should I use. I was using CircuitLab but as I don't know ...
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Fixed point multiplication circuit in HDL doesn't work as expected
I am implementing a fixed point multiplication circuit in SystemVerilog to multiply 2 64-bit numbers, each has 20 bits of decimal part (which remains 44 bits of integer part). The problem is the ...
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SIMPLIS (Elements version) - PWL Topologies Error Dialog Box = Annoying
Within the free version of SIMPLIS, there is an example "LLC_HALF_BRIDGE_CONVERTER". I can't seem to share the file, but it's free and anyone who downloads SIMPLIS has access to it. The ...
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Modelling a Floating Gate Transistor
Does anyone know of a simple circuit diagram to implement in the likes of LTspice to show the operation of a floating gate transistor?
Would a capacitor on the gate of a standard transistor do the ...
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How to design a T flipflop with NAND gates in Verilog (structural design)?
From a typical circuit diagram of T flip flops made of 3- and 2-input NAND gates, I tried to implement it with this code but could not figure out why am I not getting any answer in output terminal (...
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IR2110 LTspice high-side switching problem
I am working on a half-bridge simulation in LTspice. For the gate drive circuit I am working with an IR2110. My problem is that whatever I select Vin to be above 200 V output, it can't pass 200 V.
I ...
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SystemVerilog array initialization
I want to know what is the use of default initialization in SystemVerilog.
How are
int a[3] = '{3{2}};
and
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Optimizing AC capacitor coupling for enhanced DC filtering
I need assistance in refining my AC capacitor coupling circuit to effectively filter the DC component of my input signal.
The circuit consists of a current generator, a 1 Ω resistor, and an AC ...
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Why doesn't LTspice take the default model parameters for voltage controlled switch?
In the below example circuit, if I try to use the default model of voltage controlled switch, why does the simulation throw an error?
If I customise the model parameters using .MODEL command, it ...
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Emitter circuit on a breadboard
I am working on an emitter circuit that has a 2N3904 NPN transistor.
I have simulated the circuit before and got the results. I am trying to build it in the lab so I can compare the results to my ...
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How to find syntax error in RTL file quickly?
My company uses custom flow that is accessed via makefiles to compile the RTL and testbench code and run the simulation. The simulator cannot be accessed directly to open in GUI. The makefiles submit ...
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Behavior of parasitic capacitance of MOSFET at off-state
I'm totally a rookie to power electronics. I'm currently interested in the behavior of parasitic capacitance from MOSFET at off-state (especially for Cds). The most of the literature or videos in ...
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Verilog Double Counter Testbench Issues
I've been practicing writing some more advanced testbenches for my Verilog circuits. I thought I'd work with something simple: a double counter setup, where c0 is 3-bits long and c1 is 16-bits long. ...
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Why non-blocking assignments in Verilog sometimes do not provide a clock cycle delay?
Code for a counters Verilog file: (Go to: THE LINE OF ISSUE)
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How do you simulate a ferrite clamp in LT Spice?
Someone asked before how to get parameters for ferrite bead simulation.
The same method doesn't really work for clamps because almost all of them don't give information about resistance.
I began ...
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LTspice resistor value stepping
I have built a DC power supply circuit in LTspice with a current limiter and voltage foldback.
The circuit works, but I want to take a load resistor and set it to 1 Ω initially, then step it down ...
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How to Start Simulation (in specific turtorial) in Vivado with Custom FIR Using Xilinx DDS?
I’m following a guide (Here is the link to the guide:
https://www.hackster.io/whitney-knitter/dsp-for-fpga-using-xilinx-dds-with-custom-fir-f82447) for implementing a custom FIR filter in Vivado and ...
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Transimpedance amplifier: weird simulation results
I am working on a photodiode transimpedance amplifier based on an OPA2374 and decided to simulate it in TINA TI.
However, several unexpected issues arose.
AOL and GBW product vary significantly with ...
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Help troubleshooting Mosfets in Switching Circuit
I've been trying to design a simple circuit to switch between two Supply rails (3.3V_SW & Vbat) while giving one of them a higher priority (3.3V_SW). The circuit in simulation is showing to be not ...
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Help on LM324 SUBCKT model [closed]
I'm newbie in ngspice and having a hard time to understand the LM324 models downloaded from various sources.
Made an example with 4 different instances to demonstrate my doubt.
The idealOpAmp works as ...
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How do I run a frequency response analysis on a speaker cross-over circuit using Micro-Cap 12?
I've got a simple speaker cross-over network drawn in Micro-Cap 12, I'm using a resistor in series with an inductor to represent the speaker, I've got a sine source as a voltage source to the circuit. ...
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Beginner licensing mode error Ansys student version
I am an undergraduate student new to Ansys and would like to import a PCB design into Ansys to do some simulations. I get this error when attempting to import a .zip into the workspace:
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Is it possible to have a C language model of design in same simulation as the RTL itself and compare their outputs?
Assume that an algorithm exists in C language. It needs to be implemented in VHDL. One way to compare the two is to apply stimulus from file to model using another program or script and then store the ...
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TINA-TI - trouble with Digital-to-Analog Converter DAC161P997 Self-Powered Transmitter
I'm dealing with the DAC161P997 simulation on TINA-TI. Using the model from TI, the circuit appears to function correctly only if I leave out the capacitors on the pin.
Here's the setup – Data ...
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Transformer Model LTspice - Flyback Voltage Clamped on Primary but Still Present on Secondary Side
I'm simulating a circuit in LTspice using a pulse transformer to drive a JFET gate. The circuit is supposed to work as follows: We drive M1 (N channel FET) to pulse current from a 20V source through a ...
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By signal activating, an output should go to 1 and reset to 0 after 4 minutes, but it doesn't. Why not?
When an alarm signal is activated, the output should go 1 for 4 minutes and then reset to 0. Every posedge of clk_out comes ...
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Why won't this differential amplifier work without these two additional resistors?
I'm trying to measure a differential voltage in LTSpice using the following structure:
The simulation results are correct, the voltage at the output is very similar to the differential input voltage. ...
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SIMPLIS VPWL & IPWL resistor
I am trying to define RDS(on) to simulate the MOSFET to be used in one of the converter topologies in SIMPLIS.
There are two different types of resistor in SIMPLIS defined as below:
VPWL: The ...
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Delay in output relative to input
This is code for a lift (elevator). I am getting some delay in output. How can I get rid of these delays?
Code:
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Anyone have a Falstad simulation of a two transistor common-emitter amplifier? [closed]
I am trying to understand more fully how transistor amplifiers work and I've found the Falstad simulations to be very informative, especially the ability to place a mouse at any point and look at the ...