Questions tagged [simulation]

About tools to simulate circuits. Specify the tool used.

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Circuit Simulator

I just recently started to study circuits. I have a homework assignment and I need to simulate some circuits, but I don't know what simulator should I use. I was using CircuitLab but as I don't know ...
Nabucodonozor's user avatar
2 votes
2 answers
75 views

Fixed point multiplication circuit in HDL doesn't work as expected

I am implementing a fixed point multiplication circuit in SystemVerilog to multiply 2 64-bit numbers, each has 20 bits of decimal part (which remains 44 bits of integer part). The problem is the ...
Becker's user avatar
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SIMPLIS (Elements version) - PWL Topologies Error Dialog Box = Annoying

Within the free version of SIMPLIS, there is an example "LLC_HALF_BRIDGE_CONVERTER". I can't seem to share the file, but it's free and anyone who downloads SIMPLIS has access to it. The ...
RogerDodger's user avatar
1 vote
2 answers
60 views

Modelling a Floating Gate Transistor

Does anyone know of a simple circuit diagram to implement in the likes of LTspice to show the operation of a floating gate transistor? Would a capacitor on the gate of a standard transistor do the ...
starboy's user avatar
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2 votes
1 answer
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How to design a T flipflop with NAND gates in Verilog (structural design)?

From a typical circuit diagram of T flip flops made of 3- and 2-input NAND gates, I tried to implement it with this code but could not figure out why am I not getting any answer in output terminal (...
Dhrubajyoti Mandal's user avatar
1 vote
1 answer
61 views

IR2110 LTspice high-side switching problem

I am working on a half-bridge simulation in LTspice. For the gate drive circuit I am working with an IR2110. My problem is that whatever I select Vin to be above 200 V output, it can't pass 200 V. I ...
MSB's user avatar
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4 votes
2 answers
208 views

SystemVerilog array initialization

I want to know what is the use of default initialization in SystemVerilog. How are int a[3] = '{3{2}}; and ...
Kartikey's user avatar
3 votes
1 answer
72 views

Optimizing AC capacitor coupling for enhanced DC filtering

I need assistance in refining my AC capacitor coupling circuit to effectively filter the DC component of my input signal. The circuit consists of a current generator, a 1 Ω resistor, and an AC ...
Morena Fabozzi's user avatar
1 vote
1 answer
45 views

Why doesn't LTspice take the default model parameters for voltage controlled switch?

In the below example circuit, if I try to use the default model of voltage controlled switch, why does the simulation throw an error? If I customise the model parameters using .MODEL command, it ...
Divya K.S's user avatar
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1 vote
2 answers
153 views

Emitter circuit on a breadboard

I am working on an emitter circuit that has a 2N3904 NPN transistor. I have simulated the circuit before and got the results. I am trying to build it in the lab so I can compare the results to my ...
Ben Müller's user avatar
2 votes
2 answers
57 views

How to find syntax error in RTL file quickly?

My company uses custom flow that is accessed via makefiles to compile the RTL and testbench code and run the simulation. The simulator cannot be accessed directly to open in GUI. The makefiles submit ...
quantum231's user avatar
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Behavior of parasitic capacitance of MOSFET at off-state

I'm totally a rookie to power electronics. I'm currently interested in the behavior of parasitic capacitance from MOSFET at off-state (especially for Cds). The most of the literature or videos in ...
Vinny's user avatar
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1 vote
2 answers
61 views

Verilog Double Counter Testbench Issues

I've been practicing writing some more advanced testbenches for my Verilog circuits. I thought I'd work with something simple: a double counter setup, where c0 is 3-bits long and c1 is 16-bits long. ...
aofarmakis's user avatar
3 votes
2 answers
95 views

Why non-blocking assignments in Verilog sometimes do not provide a clock cycle delay?

Code for a counters Verilog file: (Go to: THE LINE OF ISSUE) ...
lousycoder's user avatar
1 vote
0 answers
44 views

How do you simulate a ferrite clamp in LT Spice?

Someone asked before how to get parameters for ferrite bead simulation. The same method doesn't really work for clamps because almost all of them don't give information about resistance. I began ...
Tony's user avatar
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1 answer
40 views

LTspice resistor value stepping

I have built a DC power supply circuit in LTspice with a current limiter and voltage foldback. The circuit works, but I want to take a load resistor and set it to 1 Ω initially, then step it down ...
Dereck's user avatar
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3 votes
1 answer
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How to Start Simulation (in specific turtorial) in Vivado with Custom FIR Using Xilinx DDS?

I’m following a guide (Here is the link to the guide: https://www.hackster.io/whitney-knitter/dsp-for-fpga-using-xilinx-dds-with-custom-fir-f82447) for implementing a custom FIR filter in Vivado and ...
Stuck_Between_Pixels's user avatar
0 votes
1 answer
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Transimpedance amplifier: weird simulation results

I am working on a photodiode transimpedance amplifier based on an OPA2374 and decided to simulate it in TINA TI. However, several unexpected issues arose. AOL and GBW product vary significantly with ...
Virgil_Tibbs's user avatar
0 votes
2 answers
56 views

Help troubleshooting Mosfets in Switching Circuit

I've been trying to design a simple circuit to switch between two Supply rails (3.3V_SW & Vbat) while giving one of them a higher priority (3.3V_SW). The circuit in simulation is showing to be not ...
Sultanpepper's user avatar
0 votes
1 answer
42 views

Help on LM324 SUBCKT model [closed]

I'm newbie in ngspice and having a hard time to understand the LM324 models downloaded from various sources. Made an example with 4 different instances to demonstrate my doubt. The idealOpAmp works as ...
Frederico Carlos Wilhelms's user avatar
0 votes
1 answer
32 views

How do I run a frequency response analysis on a speaker cross-over circuit using Micro-Cap 12?

I've got a simple speaker cross-over network drawn in Micro-Cap 12, I'm using a resistor in series with an inductor to represent the speaker, I've got a sine source as a voltage source to the circuit. ...
Peggy Schafer's user avatar
0 votes
1 answer
38 views

Beginner licensing mode error Ansys student version

I am an undergraduate student new to Ansys and would like to import a PCB design into Ansys to do some simulations. I get this error when attempting to import a .zip into the workspace: ...
Kemar Jordan's user avatar
0 votes
1 answer
36 views

Is it possible to have a C language model of design in same simulation as the RTL itself and compare their outputs?

Assume that an algorithm exists in C language. It needs to be implemented in VHDL. One way to compare the two is to apply stimulus from file to model using another program or script and then store the ...
gyuunyuu's user avatar
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0 votes
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39 views

TINA-TI - trouble with Digital-to-Analog Converter DAC161P997 Self-Powered Transmitter

I'm dealing with the DAC161P997 simulation on TINA-TI. Using the model from TI, the circuit appears to function correctly only if I leave out the capacitors on the pin. Here's the setup – Data ...
Morena Fabozzi's user avatar
1 vote
0 answers
54 views

Transformer Model LTspice - Flyback Voltage Clamped on Primary but Still Present on Secondary Side

I'm simulating a circuit in LTspice using a pulse transformer to drive a JFET gate. The circuit is supposed to work as follows: We drive M1 (N channel FET) to pulse current from a 20V source through a ...
L30LVC's user avatar
  • 21
1 vote
1 answer
82 views

By signal activating, an output should go to 1 and reset to 0 after 4 minutes, but it doesn't. Why not?

When an alarm signal is activated, the output should go 1 for 4 minutes and then reset to 0. Every posedge of clk_out comes ...
had's user avatar
  • 43
4 votes
2 answers
476 views

Why won't this differential amplifier work without these two additional resistors?

I'm trying to measure a differential voltage in LTSpice using the following structure: The simulation results are correct, the voltage at the output is very similar to the differential input voltage. ...
FernandoPT's user avatar
1 vote
0 answers
44 views

SIMPLIS VPWL & IPWL resistor

I am trying to define RDS(on) to simulate the MOSFET to be used in one of the converter topologies in SIMPLIS. There are two different types of resistor in SIMPLIS defined as below: VPWL: The ...
Mhan's user avatar
  • 95
1 vote
2 answers
99 views

Delay in output relative to input

This is code for a lift (elevator). I am getting some delay in output. How can I get rid of these delays? Code: ...
had's user avatar
  • 43
1 vote
1 answer
97 views

Anyone have a Falstad simulation of a two transistor common-emitter amplifier? [closed]

I am trying to understand more fully how transistor amplifiers work and I've found the Falstad simulations to be very informative, especially the ability to place a mouse at any point and look at the ...
rhody's user avatar
  • 308
0 votes
0 answers
59 views

Keysight ADS layout error "port pin not connected to conductive part of design"

I just designed a distributed element BPF using ADS and now I'm trying to put it into the layout to do an EM simulation. I created my distributed circuit using the dimensions of my components, then ...
TheBelgianWaffl _ Gaming's user avatar
1 vote
1 answer
79 views

Assign statement in testbench doesn't seem to work as it should

I have a small Verilog code example asked as an interview question. I am not sure why it prints "p=01" but not "00" since assign should update <...
totochan1965's user avatar
0 votes
0 answers
74 views

Increasing of Bow Tie Antenna Bandwidth

I designed different types of bowtie antenna in CST. But this type of antenna results s11 is not good. I want to increase of antenna bandwidth. I'm trying to get better bandwidth by changing antenna ...
Ahmet Enes YILDIRIM's user avatar
0 votes
0 answers
83 views

TINA-TI - trouble with boost converter based on LM5002

I wanted to recreate the LM5002 circuit in the TINA-TI program, which I encountered for the first time today. I was inspired by the circuit from the link below: LM5002 Unfortunately, the effects of ...
Proboszcz's user avatar
1 vote
0 answers
116 views

Having trouble simulating a two-stage differential amplifier in LTspice

The following is an LTspice simulation for a two-stage differential amplifier. The simulation takes hours. What am I doing wrong? Spice netlist: ...
kile's user avatar
  • 688
0 votes
2 answers
127 views

Why do some circuits work in LTspice, but not in Proteus?

Why do some circuits work in LTspice, but not in Proteus? I was playing with my amplifier circuits in LTspice by changing the values forth and back, I had calculated. I was thinking about a special ...
lastime's user avatar
  • 579
0 votes
2 answers
117 views

How to control the amplitude of a Wien-bridge oscillator?

I am trying to design a Wien-bridge oscillator and understood the basic working principle of it. Now I got to the point where I want to add a system which would make the gain >3 during startup and &...
Yordan Aleksandrov's user avatar
0 votes
1 answer
72 views

LTspice value of peak current and theoretical value in a circuit question

For the above question, after solving the circuit in frequency domain, I got the value of $$i_0(t) = 1.14\cos(3000t-55.3) mA $$ approximately (The calculations in the middle of steps was not ...
Nero's user avatar
  • 113
1 vote
0 answers
47 views

How do you fix this 'unlabeled value' error?

I'm really new at this and I can't understand what value is not labeled here.
andg23's user avatar
  • 11
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0 answers
13 views

Why am I getting completely different voltage and power results from Simscape phasor simulation and load flow simulation?

I am simulating the power system in the picture, with two generators and three PQ loads. My problem is that when I try to simulate it in Simscape, the load flow analysis gives me completely different ...
Jiří Nývlt's user avatar
1 vote
0 answers
152 views

How do I properly import a .lib description into a LTspice symbol?

I am trying to simulate the TI part TPS62808 in LTspice, Pspice for TI, and Tina TI. I managed to easily run the simulation in the latter two simulators, but the models were specifically made for them,...
Yordan Aleksandrov's user avatar
1 vote
1 answer
67 views

How can I utilize PSpice for ESD simulation?

Issue: I do not know how to build a ESD simulation model in PSpice Orcad capture. Question: What is wrong with the simulation circuit? The simulation result seems like the ESD is not discharging ...
Waterview Dodo's user avatar
1 vote
0 answers
72 views

LM27762 voltage regulator LTspice simulation error

LM27762 datasheet I imported the latest model from the Design tools & simulation for the component. I used the following layout from the datasheet as reference, capacitor values as defined in ...
AuFries's user avatar
  • 63
2 votes
1 answer
71 views

LTspice exception: Time step is too small in flip flop simulation

I have scheme with simple JK-trigger with Reset and Preset: But, I have error: Time step too small; initial timepoint; trouble with and-instance A7 (it can say any AND gate) when try to start ...
Everything's user avatar
3 votes
2 answers
134 views

Wrong LTspice simulation results when circuit has a large common mode potential to ground node

I'm trying to simulate the effects of a common mode signal on an optically isolated analog input circuit. I was seeing terrible common mode rejection ratios no matter what changes I made, and ...
jms's user avatar
  • 8,611
2 votes
1 answer
115 views

LTspice model file for new component

I would like to add some new components to the LTspice library. I have never done this before. The online SPICE forum discusses 3rd party component steps. It says I have to download the SPICE model ...
David Ab's user avatar
  • 129
0 votes
1 answer
113 views

BowTie Antenna Design in CST

I try to design bowtie antenna in CST simulation. This design include that substrate FR4 not with ground and top side is antenna(copper). This design's measurement is calculated online sites. Problem ...
Ahmet Enes YILDIRIM's user avatar
2 votes
1 answer
117 views

ANSYS - transformer issue (Convergence not achieved)

Whole day i am trying to simulate this converter to get current for transformer windings which will be than used for simulation (core + copper losses). But i am just not able to get this working. I ...
LinejHonzaCZ's user avatar
0 votes
4 answers
119 views

Where to place the capacitor when modelling a single long wire?

Consider a high-voltage power line that is hundreds of kilometers long. Such a wire has a capacitance, inductance and resistance. This answer to a previous similar question contains the following ...
Sibbo's user avatar
  • 103
1 vote
1 answer
76 views

Get a value from register file to analyzer

I'm trying to access register values from the analyzer in the test bench. Is there a way to access them without calling the register file module? (I don't want to call the rf module because accessing ...
ameer anas's user avatar

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