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Questions tagged [skew]

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Why do we add the positive clock skew to the minimum clock period?

Given the following circuit: I was told that the minimum clock period would be the sum of the setup time plus the propagation delay plus the clock skew for a positive clock skew. I was wondering as ...
EskimoJones's user avatar
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When is clock deskewing useful on an FPGA?

The UltraScale Architecture Clocking Resources User Guide (UG572) has a section on a MMCM configuration that enables skew removal, and says One of the predominant uses of the MMCM is for clock ...
Fra93's user avatar
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1 answer
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PCIe Gen4: inter-pair skew: any limits?

For PCIe (and more particularly PCIe Gen 4), is there any recommendation on the maximum inter-pair skew, i.e. the maximum time/length difference between either: 2 TX differential pairs (of different ...
Sandro's user avatar
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2 votes
1 answer
241 views

Skew in half-bridge dead time generator in LMG5200EVM

The eval board for the GaN half bridge module LMG5200 (datasheet) contains the following circuit to generate dead time from a single PWM input. The half-bridge module itself has good propagation ...
tobalt's user avatar
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Useful skew is a concept for what phase of physical back-end design?

The calculation of useful skew takes into account the shortest and longest logic paths. Does this mean that if I need to use useful skew during the CTS phase, then I need to routing the logic cells? ...
Dawn Li's user avatar
2 votes
0 answers
368 views

How is Alignment Marker Used for Deskew in Ethernet Protocol?

I've been reading through the 802.3 standards recently and am learning about alignment markers inserted as blocks in ethernet frames to deskew PCS channels. While I can find information about the bit-...
Dragonsheep's user avatar
3 votes
2 answers
1k views

Is there a maximum differential skew in Ethernet communication?

I am working on a device that runs 100 Base-T. When routing the differential pairs I was wondering if there is a maximum differential skew specified somewhere and if so, what is it? Is there a formula,...
VicTic's user avatar
  • 61
1 vote
1 answer
371 views

How much skew correction can typically be applied to DQS during DDR4 link training?

My understanding of the DDR4 calibration process is that DQS is derived from a common clock with a PLL, then passed through a DLL to apply deskew such that DQS and CK edges arrive in sync. Is there ...
Polynomial's user avatar
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1 answer
184 views

LVDS: Higher skew deviation or termination resistors as close as possible to the IC

I am designing a pcb with a video interface which runs lvds. LVDS has termination resistors and the datasheet states to have them put as close to the IC pins as possible. It's not 4k, but close to ...
PhreakShow's user avatar
1 vote
1 answer
1k views

PCIE Gen 2 Intra-Pair Skew

I am about to make a revision of a PCB that has 60 mills of Intra-Pair Skew in PCI-E (Gen 2) RX differential pair: Considering the capacitors the skew is ~50 mills: this is the relevant part of the ...
Firas Abd El Gani's user avatar
1 vote
0 answers
213 views

Lattice FPGAs -- How to control skew on signals routed to IO pins?

Working with: Lattice XP2-30 or XP2-40 Tentatively a BGA484; almost certainly some BGA 1mm-pitch package Synplify PRO, with SystemVerilog Skill level: Beginner / early-intermediate. If I have a ...
Cal-linux's user avatar
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1 vote
3 answers
2k views

Calculating phase angle from instantaneous voltage

For background info I am an EE/CE that is 10 years out of school and has since worked writing firmware and dealt mostly with digital communications and signals, so now I am having to reach back to my (...
Whistler's user avatar
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1 answer
121 views

Circuit not working: Differential impedance, or skew, or a different problem responsible?

For a hobby project, I am designing a circuit that converts displayport to APIX2, which is a serializer protocol used in cars' infotainment systems, mostly BMW. This is done by an INAP375T IC, APIX is ...
PhreakShow's user avatar
1 vote
1 answer
164 views

Which is better, less crosstalk or less skew?

I'm designing a board that has a LVDS 2.5V interface with 30 lanes clocked at 600MHz and DDR. This is going from one chip to another chip which could be placed right next to it, there are no other ...
Alex I's user avatar
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5 votes
2 answers
1k views

Routing USB, DVI and Ethernet signals on a large PCB vs using long cables

Properly routing USB, DVI and Ethernet signals over long distances (30 to 40 cm) on a PCB seems to be relatively challenging (skew, characteristic impedance, cross-talk, etc.). Yet using the standard ...
user110091's user avatar
1 vote
1 answer
471 views

Skew angle in 3-phase AC induction outer rotor motor

I am working on a motor like the above stated. I have 3-phase winding on a 24 slot stator. I am now designing the rotor part. What skew angle should i use for a very smooth rotational torque? Is there ...
J.K.'s user avatar
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0 votes
1 answer
3k views

Set the threshold voltage of CMOS inverter to VDD/2 for both rising and falling edge: possible?

Using 0.35u technology (VDD= 3.3v, Vt=0.7, Tox = 0.7 nm), I am trying to set the threshold voltage of an inverter to VDD/2. If I set the width ratio of PMOS/NMOS to 5 (means the Width of PMOS would ...
Dr. Ehsan Ali's user avatar
2 votes
1 answer
818 views

How to create a triple redundant clock tree in FPGA manually?

I am exploring a range of techniques to implement TMR clock trees as part of a global TMR design (all resources including i/o pins, clock trees, reset trees, logic and registers are implemented with ...
Happy Techy's user avatar
2 votes
2 answers
1k views

Combinational logic delay is greater than clock period

Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the ...
titan's user avatar
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4 votes
1 answer
1k views

Distributing a 40MHz clock to several PCBs

I need to run four PCBs with a very accurately synchronised clock. The source clock is 40MHz, but each PCB contains a 1GHz PLL, and will be timing events in the analogue domain with a final ...
Rocketmagnet's user avatar
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