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Questions tagged [skew]

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Circuit not working: Differential impedance, or skew, or a different problem responsible?

For a hobby project, I am designing a circuit that converts displayport to APIX2, which is a serializer protocol used in cars' infotainment systems, mostly BMW. This is done by an INAP375T IC, APIX is ...
1
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1answer
111 views

Which is better, less crosstalk or less skew?

I'm designing a board that has a LVDS 2.5V interface with 30 lanes clocked at 600MHz and DDR. This is going from one chip to another chip which could be placed right next to it, there are no other ...
5
votes
2answers
656 views

Routing USB, DVI and Ethernet signals on a large PCB vs using long cables

Properly routing USB, DVI and Ethernet signals over long distances (30 to 40 cm) on a PCB seems to be relatively challenging (skew, characteristic impedance, cross-talk, etc.). Yet using the standard ...
1
vote
1answer
356 views

Skew angle in 3-phase AC induction outer rotor motor

I am working on a motor like the above stated. I have 3-phase winding on a 24 slot stator. I am now designing the rotor part. What skew angle should i use for a very smooth rotational torque? Is there ...
0
votes
1answer
856 views

Set the threshold voltage of CMOS inverter to VDD/2 for both rising and falling edge: possible?

Using 0.35u technology (VDD= 3.3v, Vt=0.7, Tox = 0.7 nm), I am trying to set the threshold voltage of an inverter to VDD/2. If I set the width ratio of PMOS/NMOS to 5 (means the Width of PMOS would ...
2
votes
1answer
614 views

How to create a triple redundant clock tree in FPGA manually?

I am exploring a range of techniques to implement TMR clock trees as part of a global TMR design (all resources including i/o pins, clock trees, reset trees, logic and registers are implemented with ...
2
votes
2answers
602 views

Combinational logic delay is greater than clock period

Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the ...
4
votes
1answer
578 views

Distributing a 40MHz clock to several PCBs

I need to run four PCBs with a very accurately synchronised clock. The source clock is 40MHz, but each PCB contains a 1GHz PLL, and will be timing events in the analogue domain with a final ...